CN116009818A - Forward conversion device based on arbitrary residual number base - Google Patents

Forward conversion device based on arbitrary residual number base Download PDF

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CN116009818A
CN116009818A CN202211681261.5A CN202211681261A CN116009818A CN 116009818 A CN116009818 A CN 116009818A CN 202211681261 A CN202211681261 A CN 202211681261A CN 116009818 A CN116009818 A CN 116009818A
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modulo
processing module
data
remainder
forward conversion
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王天雄
刘飞扬
王明杰
纪金伟
马上
李博文
高恺
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University of Electronic Science and Technology of China
CETC 54 Research Institute
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University of Electronic Science and Technology of China
CETC 54 Research Institute
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Abstract

The invention discloses a forward conversion device based on any residual number base, and belongs to the technical field of wireless communication. The invention comprises a data segmentation module, an in-segment processing module and an out-segment processing module, and based on any residual number base, the forward conversion of converting binary numbers with larger bit width into RNS numbers with smaller bit width is realized. The invention provides a conversion mode for the RNS number at the data input end of the digital signal processing system by utilizing the characteristics of parallel calculation and no carry of the remainder system, reduces the hardware complexity of the DSP device and improves the data processing speed.

Description

Forward conversion device based on arbitrary residual number base
Technical Field
The invention belongs to the technical field of wireless communication, in particular to a forward conversion device based on any residual number base, which is suitable for a real-time determination phase generation process of a long-period spread spectrum code of a spread spectrum communication system and a long-period frequency hopping sequence of a frequency hopping communication system.
Background
The binary number is processed by modulo operation on the remainder base, the numerical representation system formed by the obtained remainder set is called a remainder system, and the remainder systems are parallel, unauthorized and carryless due to the fact that the remainder bases are mutually different in pairs and have completely independent structures. The remainder system can be utilized to decompose the operation with larger bit width into a plurality of operations with smaller bit width to be realized in parallel, and under the condition that the dynamic range of data processed by the DSP is certain, the number of the remainder base channels is properly increased, so that the length of a critical path can be correspondingly shortened, the time delay and the area of the system are reduced, and the complexity, the resource consumption and the power consumption of the DSP are further reduced. Compared with the traditional binary adder and multiplier, the performance of which is influenced by carry propagation delay, the characteristic of a remainder system can obviously improve the operation efficiency of an arithmetic unit, so that the binary adder and multiplier are widely applied to multiplication and addition intensive digital signal processing systems, such as FIR digital filters. Nowadays, the requirements on processing capacity, speed, real-time performance, power consumption and the like of a signal processing system are higher and higher, a remainder system introduces parallel advantages at the forefront end of a data or signal processing system, the complexity of operation is reduced, the realization of required resources and power consumption is reduced, and the working efficiency of the system is improved, so that the remainder system is a numerical representation system which accords with the expectations of a DSP (digital signal processor), and a DSP technology based on the remainder system also becomes one of hot spots of data channel design.
In the forward conversion method of binary RNS number, some methods limit the size of remainder base, if the remainder base is 11,17,19 and other smaller numbers are required; some methods define the formation of the remainder base, e.g. 2 n ±1，2 n 3, etc., or a fixed form of remainder base formed by variants or extensions thereof, e.g. r n ±1，r n 2, etc. This allows the developer to consider the numerical conversion of the front end of the algorithm in the design and optimization of the algorithmAnd characterization, or development design and optimization based on a specific numerical characterization form, greatly limit the flexibility and versatility of the application of the remainder system.
The forward conversion method of any residue can realize the conversion of binary numbers to RNS numbers of any residue, has no special requirements on the size and structural form of the data to be converted and the residue, increases the range of numerical representation, effectively avoids the limitation of forward conversion, is beneficial to the parallel realization of more common signal processing systems, and has important significance for the system design with low complexity, high speed, low power consumption and large dynamic range.
Disclosure of Invention
The invention provides a forward conversion device based on any residual number base, which can realize forward conversion from binary numbers of any residual number base to RNS numbers and can characterize the binary numbers as R NS numbers.
The invention adopts the technical scheme that:
a forward conversion device based on any residual basis comprises a data segmentation module, an intra-segment processing module and an extra-segment processing module;
the data segmentation module divides the binary representation form of the data to be processed into s segments and obtains the corresponding value K of each segment j J=0, 1,2,..s-1, and stores K to the corresponding register j The method comprises the steps of carrying out a first treatment on the surface of the Calculate and store into corresponding registers
Figure BDA0004019487920000021
q is m i The minimum number of bits required for the binary representation, < >>
Figure BDA0004019487920000022
Representation about m i Solving the remainder; calculating +.>
Figure BDA0004019487920000023
And store X to the corresponding register j ；
The intra-segment processing module processes each X j J=0, 1,2,..s-1 is represented by bits, converted to a binary representation (b 2q-1 b 2q-2 ...b 1 b 0 ) 2 The method comprises the steps of carrying out a first treatment on the surface of the Calculate and store into corresponding registers
Figure BDA0004019487920000031
By a 2-to-1 selector unit, according to X j The bit of 0 outputs 0 and the bit of 1 outputs the corresponding +.>
Figure BDA0004019487920000032
Through 2 input-modulo m i Adder unit outputting all bits of 1 to +.>
Figure BDA0004019487920000033
Modulo sum is obtained by a modulo adder to obtain +.>
Figure BDA0004019487920000034
Is a value of (2);
the out-of-segment processing module is input through 2-input-mode m i Adder unit for adding all
Figure BDA0004019487920000035
Modulo sum is obtained by a modulo adder to obtain +.>
Figure BDA0004019487920000036
The value of (i.e.)>
Figure BDA0004019487920000037
Is a value of (2).
The invention has the beneficial effects that:
1. the invention can decompose the data processing into a plurality of independent channels for parallel realization, reduce the complexity of a signal processing system, effectively improve the running speed of the system and reduce the power consumption of the system.
2. The invention can realize the forward conversion from binary numbers with any residual number base to RNS numbers, and can characterize the binary numbers as RNS (remainder system, residue Number System) numbers, namely, based on any residual number base, the forward conversion from binary numbers with larger bit width to RNS numbers with smaller bit width is realized.
3. The invention provides a conversion mode for the RNS number at the data input end of the Digital Signal Processing (DSP) system by utilizing the characteristics of parallel calculation and no carry of the remainder system, reduces the hardware complexity of the DSP device and improves the data processing speed. Wherein the size and structural form of the remainder base are not constrained (e.g. not necessarily 2 n 1 or other forms), the size of the data to be converted is not limited; the remainder base may be a specific integer number or a range of values.
Drawings
Fig. 1 is a schematic diagram of the present invention.
Fig. 2 is a schematic structural view of the present invention.
FIG. 3 is a 2-input-mode m of the present invention i Schematic of the adder.
Detailed Description
The invention will be described in further detail with reference to the accompanying drawings and the detailed description.
As shown in fig. 2, a forward conversion device based on any residual basis includes a data segmentation module, an intra-segment processing module and an extra-segment processing module, and the functions of the modules are as follows:
(1) Data segmentation module
1) Converting the data to be processed into a binary representation (when the data to be processed is in other representation);
2) Zero padding (when the number of binary representation bits of the data to be processed is less than an integer multiple of the number of base bits of the remainder);
3) Segmenting into s segments, and obtaining the corresponding value K of each segment j J=0, 1,2,..s-1, i.e. K 0 ,K 1 ,K 2 ,...,K s-1 And store K to the corresponding register j ；
4) Calculate and store into corresponding registers
Figure BDA0004019487920000041
5) 2-input 1-output multiplier unit, according to 3) and 4) calculations
Figure BDA0004019487920000042
And store X to the corresponding register j 。
(2) In-segment processing module
1) Each X is taken j J=0, 1,2,..s-1 is represented in bits, i.e. converted into binary representation, i.e. (b) 2q- 1 b 2q-2 ...b 1 b 0 ) 2 ；
2) Calculate and store into corresponding registers
Figure BDA0004019487920000043
3) 2-select 1 selector unit according to X j The bit value of (2) is 0, the bit of 0 outputs 0, the bit of 1 outputs corresponding
Figure BDA0004019487920000051
4) 2 input-modulo m i Adder unit for outputting all bits of 1
Figure BDA0004019487920000052
Modulo sum is obtained by a modulo adder to obtain +.>
Figure BDA0004019487920000053
Is a value of (2).
(3) Out-of-segment processing module
As shown in fig. 3, 2 input-modulo m i Adder unit for adding all
Figure BDA0004019487920000054
Modulo sum is obtained by a modulo adder to obtain +.>
Figure BDA0004019487920000055
The value of (i.e.)>
Figure BDA0004019487920000056
Is a value of (2).
The principle of the device is shown in fig. 1, and is specifically as follows:
step one: if the magnitude m of the residual number base value is known i ,2 q-1 ＜m i ＜2 q Q is m i The minimum number of bits required for the binary representation;
step two: knowing the data X,2 to be processed n-1 ＜X＜2 n N is the minimum number of bits required for a binary representation of X, the binary representation of X being x= (X) n-1 ...x 1 x 0 ) 2 ＝x n-1 2 n-1 +...+x 1 2 1 +x 0 20, wherein x i ∈{0,1},i＝0,1,...,n，(·) 2 A binary form representing a number;
step three: determining the total number of segments s in which X can be expressed in q bits per segment, i.e
Figure BDA0004019487920000057
The number of X insufficient bits is zero added at the upper position to obtain X ', and the number of the X' bits is n '=sq, and X' =x n′-1 ...x 1 x 0 ＝x n′-1 2 n′-1 +...+x n 2 n +...+x 1 2 1 +x 0 20，/>
Figure BDA0004019487920000058
Representing an upward rounding;
step four: taking out the corresponding value K of X' according to q bits of each segment 0 ,K 1 ,K 2 ,...,K s-1 ，K j The numerical range is [0,2 q -1]J=0, 1,2,..s-1, note X' =k s-1 *2 (s-1)q +...+K 1 *2 q +K 0 *2 0 Then X' (i.e. X) is based on Yu Shuji m i The RNS number of (1-1) is as shown in the formula,
Figure BDA0004019487920000061
wherein the method comprises the steps of
Figure BDA00040194879200000611
Representation about m i Solving the remainder;
step five: from step four, the sum type
Figure BDA0004019487920000062
Is->
Figure BDA0004019487920000063
In->
Figure BDA0004019487920000064
The numerical range of (2) is [0,2 ] 2q -1]Then each item X j Expressed as a 2 q-bit binary number, as shown in formula (1-2)>
Figure BDA0004019487920000065
Wherein b h ∈{0,1},h＝0,1,...,2q-1；
Step six: then step b h Corresponding to =1
Figure BDA0004019487920000066
As input to the 2-input modulo adder, all +.>
Figure BDA0004019487920000067
Step seven: all X's are taken j J=0, 1,2,..s-1 is taken as input to a 2-input modulo adder, and is determined according to equation (1-3)
Figure BDA0004019487920000068
Figure BDA0004019487920000069
Step eight: in particular, for step five, the power of 2 is not required to be spread out, and the power of 2 m corresponding to the n-1 bit to the 2q-1 bit is calculated i Namely, as shown in the formula (1-4),
Figure BDA00040194879200000610
b h ∈{0,1},h＝n-1,n,...,2q-2,2q-1；
step nine: if the number base value range (m min ,m max )，2a＜m min ,m max 2b, a and b are respectively bit numbers corresponding to binary representation forms of a residue base number range, and the numerical range can be any one of an open section, a closed section and a half-open and half-closed section; then for step five, it is not necessary to develop all powers of 2, and the power of 2 modulo m corresponding to the a-th bit through the 2 q-1-th bit is calculated i Namely, as shown in the formula (1-5),
Figure BDA0004019487920000071
b h ∈{0,1},h＝a,...,2q-2,2q-1。
in a word, the invention provides a conversion method for the RNS number at the data input end of a Digital Signal Processing (DSP) system by utilizing the characteristics of parallel calculation and no carry of a remainder system, and can realize forward conversion from binary numbers of any remainder base to the RNS number, namely, the binary numbers are represented as the RNS number. The invention reduces the hardware complexity of the DSP device and improves the data processing speed.

Claims (1)

1. The forward conversion device based on any residual number base is characterized by comprising a data segmentation module, an intra-segment processing module and an extra-segment processing module;
the data segmentation module divides the binary representation form of the data to be processed into s segments and obtains the corresponding value K of each segment j J=0, 1,2,..s-1, and stores K to the corresponding register j The method comprises the steps of carrying out a first treatment on the surface of the Calculate and store into corresponding registers
Figure FDA0004019487910000011
q is m i Minimum required for binary representationNumber of bits->
Figure FDA0004019487910000012
Representation about m i Solving the remainder; calculating +.>
Figure FDA0004019487910000013
And store X to the corresponding register j ；
The intra-segment processing module processes each X j J=0, 1,2,..s-1 is represented by bits, converted to a binary representation (b 2q- 1 b 2q-2 ...b 1 b 0 ) 2 The method comprises the steps of carrying out a first treatment on the surface of the Calculate and store into corresponding registers
Figure FDA0004019487910000014
By a 2-to-1 selector unit, according to X j The bit of 0 outputs 0 and the bit of 1 outputs the corresponding +.>
Figure FDA0004019487910000015
Through 2 input-modulo m i Adder unit outputting all bits of 1 to +.>
Figure FDA0004019487910000016
Modulo sum is obtained by a modulo adder to obtain +.>
Figure FDA0004019487910000017
Is a value of (2);
the out-of-segment processing module is input through 2-input-mode m i Adder unit for adding all
Figure FDA0004019487910000018
Modulo sum is obtained by a modulo adder to obtain +.>
Figure FDA0004019487910000019
The value of (i.e.)>
Figure FDA00040194879100000110
Is a value of (2). />
CN202211681261.5A 2022-12-27 2022-12-27 Forward conversion device based on arbitrary residual number base Pending CN116009818A (en)

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