CN115995423A - Semiconductor structure and forming method thereof, stacking structure and forming method thereof - Google Patents

Abstract

The embodiment of the disclosure provides a semiconductor structure and a forming method thereof, a stacking structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing an initial substrate; the initial substrate at least comprises an initial subsequent process layer and an initial wiring layer which is positioned on the initial subsequent process layer and provided with a first groove; etching the initial substrate along the first groove to form a wiring layer and a through hole; and filling conductive materials in the through holes to form conductive columns communicated with the wiring layer.

Description

Semiconductor structure and forming method thereof, stacking structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method of forming the same, a stacked structure and a method of forming the same.

Background

Through silicon via (Through Silicon Via, TSV) technology in dynamic random access memory (Dynamic Random Access Memory, DRAM) can stack 4X/8X DRAM chips for high speed and broadband applications. Larger TSVs (5 x 5/10 x 10 micrometers (μm)) filled with copper can degrade the chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process conditions; in addition, the Thermal Budget (Thermal Budget) of the bond makes the copper pillar to bump (bump) surface less process planarized. Accordingly, there is a need to provide a new method of forming through silicon vias.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same, a stacked structure and a method of forming the same.

In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing an initial substrate; the initial substrate at least comprises an initial subsequent process layer and an initial wiring layer which is positioned on the initial subsequent process layer and provided with a first groove; etching the initial substrate along the first groove to form a wiring layer and a through hole; and filling conductive materials in the through holes to form conductive columns communicated with the wiring layer.

In some embodiments, a portion of the initial routing layer has a thickness at the bottom of the first recess that is less than a thickness of a portion of the initial routing layer on the initial post process layer.

In some embodiments, the first recess of the initial wiring layer includes a first opening and a second opening, the first opening being on the second opening, the first opening having a larger opening size and/or tilt angle than the second opening.

In some embodiments, the initial base further comprises an initial device layer and an initial substrate underlying the initial post process layer; the providing an initial substrate includes: providing an initial substrate and forming an initial device layer on the initial substrate; sequentially forming a metal interconnection layer, an initial etching stop layer and an initial interlayer dielectric layer on the initial device layer; etching the initial interlayer dielectric layer to the initial etching stop layer to form a second groove so as to form the initial subsequent process layer; and forming the initial wiring layer in the second groove and on the initial interlayer dielectric layer.

In some embodiments, the initial wiring layer on the initial interlayer dielectric layer has a thickness in the range of 5 to 7 microns; the initial wiring layer thickness on the second recess ranges from 0.3 to 0.6 microns.

In some embodiments, etching the initial substrate along the first recess to form a wiring layer and a via hole, comprising: etching an initial wiring layer downwards based on the first groove, and forming the wiring layer while exposing the initial interlayer dielectric layer; etching the initial interlayer dielectric layer and the initial etching stop layer to expose the initial device layer; and etching the initial device layer and the initial substrate to form the through hole.

In some embodiments, before filling the via with conductive material, the method further comprises: forming an initial isolation layer and an initial barrier layer in the through hole in sequence; etching back the initial isolation layer and the initial barrier layer which are positioned on the top side wall of the through hole and the wiring layer to form an isolation layer and a barrier layer; wherein top surfaces of the isolation layer and the barrier layer are lower than top surfaces of the wiring layers.

In some embodiments, the thickness of the barrier layer ranges from 0.2 to 0.5 microns; the barrier layer has a thickness in the range of 100 to 500 angstroms.

In some embodiments, the first recess has a width in the range of 5 to 10 microns; the depth of the first groove ranges from 3 to 5 micrometers; the conductive pillars have a diameter in the range of 3 to 15 microns; the conductive pillars have a length in the range of 30 to 100 microns.

In a second aspect, embodiments of the present disclosure provide a semiconductor structure comprising: the substrate at least comprises a subsequent process layer and a wiring layer positioned on the surface of the subsequent process layer; conductive posts extend through the substrate, and the wiring layer includes portions surrounding and physically contacting the conductive posts.

In some embodiments, the post process layer comprises a first aperture and a second aperture, wherein the first aperture is located over the second aperture, the first aperture having an opening size that is greater than an opening size of the second aperture; the top surface of the conductive post is located between the top surface of the second hole and the top surface of the wiring layer.

In some embodiments, the second hole surface has a portion of the wiring layer, and a thickness of the portion of the wiring layer in the second hole sidewall direction gradually decreases with increasing depth.

In some embodiments, the portion of the wiring layer surrounding the conductive pillar includes a first opening and a second opening, the first opening being on the second opening, the first opening having a larger opening size and/or tilt angle than the second opening.

In a third aspect, an embodiment of the present disclosure provides a method for forming a stacked structure, including: providing a first chip and a second chip; wherein at least one of the first chip and the second chip is formed using the forming method described in any of the embodiments above; and bonding the first chip and the second chip.

In a fourth aspect, embodiments of the present disclosure provide a stacked structure, including: a first chip and a second chip, wherein at least one of the first chip and the second chip is formed using the forming method described in any of the embodiments above; the first chip and/or the second chip comprises a substrate and a conductive column; the substrate at least comprises a subsequent process layer and a wiring layer positioned on the surface of the subsequent process layer; the conductive pillars penetrate the substrate, and the wiring layer includes portions surrounding and physically contacting the conductive pillars; the first chip and the second chip are bonded through the conductive pillars.

In an embodiment of the present disclosure, first, an initial substrate is provided; the initial substrate at least comprises an initial subsequent process layer and an initial wiring layer which is positioned on the initial subsequent process layer and provided with a first groove; secondly, etching the initial substrate along the first groove to form a wiring layer and a through hole; finally, filling conductive material in the through hole to form a conductive column communicated with the wiring layer. Therefore, on one hand, when the initial substrate is etched to form the through hole, the initial wiring layer can be directly used as a mask, and the mask layer is not required to be additionally formed, so that the process flow can be simplified, and the cost can be reduced; on the other hand, since the size of the conductive post is limited by the width of the wiring layer when the conductive post is formed, the end area of the formed conductive post is small, so that parasitic capacitance between the conductive post and the metal interconnection layer in the subsequent process layer can be reduced.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 is a schematic implementation flow chart of a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 2 to 6 are schematic views illustrating a process of forming a semiconductor structure according to an embodiment of the disclosure;

fig. 7 is a schematic implementation flow chart of a method for forming a stacked structure according to an embodiment of the disclosure;

fig. 8 is a schematic structural diagram of a stacked structure according to an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Prior to describing the embodiments of the present disclosure, TSV and related terms in the related art will be described.

In the related art, two methods are adopted to form a TSV, namely, a middle process (TSV) is first manufactured, and then a metal interconnection layer M1 is formed on the TSV; another post process, namely, forming the metal interconnection layer M1, then turning the wafer over, and finally making the TSV. The TSVs formed in both Of these modes fall on the metal interconnect layer M1, and are then formed on the top metal, i.e., the Re-wiring layer (Re-Distribution Layer, RDL), by a Back End Of Line (BEOL), so that the contact/metal resistance is high.

Meanwhile, the TSV, M1 and the parasitic capacitance/resistance (RC/RS) of the subsequent process in the chip 1 and the bonding surface in the multi-chip stacked structure and the TSV, M1 and the parasitic capacitance/resistance of the subsequent process in the chip 2 form a passage, so that the parasitic capacitance and resistance of the whole stacked structure are larger.

In addition, due to the larger metal structure area at the two ends of the formed through silicon via, parasitic capacitance between the TSV and the metal interconnection layer can be increased.

The preceding process (Front End Of The Line, FEOL) includes: a region (Active Area) where a memory device (transistor) is fabricated, for example, is divided over a substrate, then ion implantation is performed to achieve N-type and P-type regions, then gate electrode is performed, and then ion implantation is performed to complete the Source (Source) and Drain (Drain) of each transistor. This part of the process flow is to form memory devices, such as N-type and P-type field effect transistors, on the substrate.

The intermediate step (Middle Of The Line, MOL) may be a step of forming a contact hole such as a source/drain contact, a gate contact, a via structure, or the like.

The subsequent process may be a process of establishing several layers of conductive metal lines, with interconnection between the different layers of metal lines being achieved by the columnar metal.

In view of this, an embodiment of the disclosure provides a method for forming a semiconductor structure, referring to fig. 1, the method includes steps S101 to S103, where:

step S101, providing an initial substrate; the initial substrate at least comprises an initial subsequent process layer and an initial wiring layer which is positioned on the initial subsequent process layer and provided with a first groove;

here, the initial subsequent process layer may be a generic term for a structural layer formed in a subsequent process, and thus may include a metal interconnection layer, a Via (Via), an initial interlayer dielectric layer (Inter Metal Dielectric, IMD), an initial etch stop layer, and the like. The number of metal interconnection layers can be set according to design requirements, for example, four metal interconnection layers, namely metal interconnection layers M0, M1, M2 and M3, can be set; the number of via layers may be designed according to the number of metal interconnect layers, for example, four metal interconnect layers may be provided with three via layers, i.e., via V0, V1, and V2, respectively.

The metal interconnect layer M1 functions to connect the vias V1 of different regions. The via V1 is a connection channel between the metal interconnect layer M1 and the metal interconnect layer M2 formed on the initial interlayer dielectric layer, and the via V2 is a connection channel between the metal interconnect layer M2 and the metal interconnect layer M3 formed on the initial interlayer dielectric layer. An initial etch stop layer may be located between the metal interconnect layer and the initial interlevel dielectric layer.

In some embodiments, the initial base further includes an initial device layer and an initial substrate underlying the subsequent process layer. Here, the initial device layer may include a structural layer formed by a previous process and a structural layer formed by an intermediate process, for example, the initial device layer may include a memory device (e.g., a transistor) and a contact hole. Wherein the contact hole is a connection channel between the memory device and the metal interconnection layer M0.

In some embodiments, step S101 may include steps S1011 to S1014, wherein:

step S1011, providing an initial substrate and forming an initial device layer on the initial substrate;

here, the initial substrate may be a single layer, and may be, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display; may also be multi-layered, such as a silicon-on-insulator (Silicon On Insulator, SOI) substrate, or a germanium-on-insulator (Germanium On Insulator, GOI) substrate, etc. In other embodiments, the initial substrate may also be an ion doped substrate, such as a P-doped substrate or an N-doped substrate.

In some embodiments, shallow trench isolation (Shallow Trench Isolation, STI) may also be formed in the initial substrate, where a number of active regions are isolated in an array or other distribution type. STI may be formed by forming a trench in the initial substrate and then filling the trench with a layer of isolation material. The material filled in the STI may include silicon nitride or silicon oxide, etc., and the silicon oxide may be formed by thermal oxidation.

Referring to fig. 2, an initial substrate 11a is provided, the initial substrate 11a including shallow trench isolation 111 therein; an initial device layer (not shown) is then formed on the initial substrate 11 a.

Step S1012, sequentially forming a metal interconnection layer, an initial etching stop layer and an initial interlayer dielectric layer on the initial device layer;

here, the resistivity of the interconnect material, the step coverage and surface flatness of the deposition process, electromigration and stress, etc. need to be considered in selecting the material of the metal interconnect layer. The low-resistivity material is used for interconnection, so that the loss and RC delay of the chip can be reduced, and the speed of the chip can be improved, wherein the RC delay refers to signal delay caused by Resistance (Resistance) and capacitance (capacitance) in the charge and discharge processes. The material of the metal interconnection layer may be a conductive material such as copper, tungsten or aluminum. The function of the initial etch stop layer is to reduce over-etching, and the material used may be silicon carbide nitride (SiCN) or silicon nitride (SiN).

The function of the initial interlayer dielectric layer is to isolate different metal interconnection layers, and the adopted material is low-k material or ultra-low-k material, such as carbon doped oxide (SiCOH) or silicon oxide.

In practice, a plating process may be used to form the metal interconnect layer; the initial etch stop layer and the initial interlayer dielectric layer may be formed by any of the following suitable deposition processes: a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, a spin-on process, or a coating process.

With continued reference to fig. 2, a metal interconnect layer M0/M1/M2/M3, an initial etch stop layer, and an initial interlayer dielectric layer 121a are sequentially formed on the initial device layer.

Step S1013, etching the initial interlayer dielectric layer to the initial etching stop layer to form a second groove so as to form an initial subsequent process layer;

here, the initial interlayer dielectric layer may be etched using a wet or dry etching process, which may include: reactive ion etching techniques, plasma etching techniques, etc., embodiments of the present disclosure do not limit the type of wet or dry etching process.

The second groove is a redistribution layer groove (Re-Distribution Layer Via, RDV). The sidewalls of the second recess may be vertical or sloped, as the embodiments of the present disclosure are not limited in this respect.

With continued reference to fig. 2, the initial interlayer dielectric layer 121a is etched to an initial etch stop layer, forming a second recess a, to form an initial post process layer 12a.

In step S1014, an initial wiring layer is formed in the second recess and on the initial interlayer dielectric layer.

Here, the initial wiring layer may be formed using a suitable deposition process such as physical vapor deposition. The material of the initial wiring layer may be aluminum or copper, and the resistivity of the wiring layer may be reduced.

Referring to fig. 3, an initial wiring layer 13a is formed on the initial interlayer dielectric layer 121a and the second recess, thus forming an initial substrate 10. It should be noted that, after the initial wiring layer 13a is formed by deposition, for example, physical vapor deposition, the topography in fig. 3 is automatically formed, that is, the initial wiring layer 13a has the first grooves B.

In some embodiments, with continued reference to fig. 3, a thickness d1 of a portion of the initial routing layer 13a at the bottom of the first recess B is less than a thickness d2 of a portion of the initial routing layer 13a on the initial post-process layer 12a. That is, the initial wiring layer includes three parts, a first part is located at the bottom of the first groove B, a second part is located on the initial post-process layer 12a, a third part is located at the sidewall of the first groove B, and the thickness of the first part is smaller than that of the second part.

In some embodiments, the thickness of the initial wiring layer 13a on the initial interlayer dielectric layer 121a ranges from 5 to 7 μm; the thickness of the initial wiring layer 13a located on the second groove a ranges from 0.3 to 0.6 μm.

Therefore, when the initial substrate is etched along the first groove subsequently, the initial wiring layer at the bottom of the first groove can be etched in a self-aligned mode without using a photomask, and therefore the process flow is simplified.

In some embodiments, the width of the first recess ranges from 5 to 10 μm; the depth of the first grooves ranges from 3 to 5 μm. This may be more advantageous for etching the initial substrate.

In some embodiments, with continued reference to fig. 3, the first groove B includes a first opening B1 and a second opening B2, the first opening B1 being on the second opening B2, the opening dimension L1 of the first opening B1 being greater than the opening dimension L2 of the second opening B2. In some embodiments, the inclination angle θ1 of the first opening B1 is greater than the inclination angle θ2 of the second opening B2. In other embodiments, the opening dimension L1 of the first opening B1 is larger than the opening dimension L2 of the second opening B2, and the inclination angle θ1 of the first opening B1 is larger than the inclination angle θ2 of the second opening B2. In the embodiment of the disclosure, the opening size and/or the inclination angle of the first opening are larger than those of the second opening, which is beneficial to etching the initial substrate or self-aligned etching the initial substrate.

Step S102, etching an initial substrate along a first groove to form a wiring layer and a through hole;

here, the initial substrate may be etched using a wet etching process or a dry etching process.

Referring to fig. 3 and 4 simultaneously, the initial substrate 10 is etched along the first groove B to form a wiring layer 13 and a via hole 20. While the via 20 is being formed, the remaining initial post process layer forms the post process layer 12, and it can be seen that the post process layer 12 includes two holes, a first hole 122 and a second hole 123, respectively; wherein the first hole 122 is located on the second hole 123, and an opening size of the first hole 122 is larger than an opening size of the second hole 123.

In some embodiments, the forming of the wiring layer and the via hole may include: etching the initial wiring layer downwards based on the first groove, and forming the wiring layer while exposing the initial interlayer dielectric layer; etching the initial interlayer dielectric layer and the initial etching stop layer to expose the device layer; and etching the initial device layer and the initial substrate to form a through hole.

After the initial wiring layer at the bottom of the first groove is etched, a wiring layer is formed, and after the initial interlayer dielectric layer, the initial etching stop layer, the initial device layer and the initial substrate are etched, the remaining initial interlayer dielectric layer, initial etching stop layer, initial device layer and initial substrate correspondingly form an interlayer dielectric layer 121, an etching stop layer, a device layer and a substrate 11.

And step S103, filling conductive materials in the through holes to form conductive columns communicated with the wiring layer.

Here, the conductive pillars are through silicon vias, and the conductive pillars may be used to realize electrical connection between two wafers after bonding the wafers, and the conductive material may be tungsten, aluminum, copper, or the like. The deposition processes used for different conductive materials are also different, for example, the (Chemical Vapor Deposition, CVD) method is used when tungsten is used as the conductive material; when aluminum is used as the conductive material, a CVD method and a PVD method are adopted; copper is used as a conductive material by Chemical Plating (CP) method.

In the embodiment of the disclosure, the wiring layer is mainly used for supplying power to the inside of the chip.

In practical application, because the aperture of the through hole is smaller, the depth is larger, the depth-to-width ratio is higher, and electroplating cavities are formed when copper plating is performed by adopting a uniform electroplating process, the bottom-up electroplating process can be adopted, the deposition rate inside the through hole and the deposition rate on the outer surface of the through hole are accelerated by utilizing special electroplating promoters and inhibitors, and the promoters and the inhibitors are balanced by adjusting the proportion of the promoters and the inhibitors, so that the generation of the electroplating cavities is prevented.

The wiring layer and the conductive post are both made of conductive materials, and the wiring layer surrounds the conductive post and physically contacts the conductive post, so that the wiring layer and the conductive post are communicated.

Referring to fig. 5, a conductive material is filled in the via hole 20 to form a conductive post 30 communicating with the wiring layer 13. In some embodiments, the conductive pillars 30 have a diameter in the range of 3 to 15 μm; the length of the conductive post 30 ranges from 30 to 100 μm.

In practical application, after the conductive column is formed, the upper surface of the interlayer dielectric layer is deposited with redundant conductive materials, so that some protrusions and grooves are formed on the upper surface of the interlayer dielectric layer, and the redundant conductive materials can be removed by adopting processes such as etching, grinding, polishing and the like.

In an embodiment of the present disclosure, first, an initial substrate is provided; the initial substrate at least comprises an initial subsequent process layer and an initial wiring layer which is positioned on the initial subsequent process layer and provided with a first groove; secondly, etching the initial substrate along the first groove to form a wiring layer and a through hole; finally, filling conductive material in the through hole to form a conductive column communicated with the wiring layer. Therefore, on one hand, when the initial substrate is etched to form the through hole, the initial wiring layer can be directly used as a mask, and the mask layer is not required to be additionally formed, so that the process flow can be simplified, and the cost can be reduced; on the other hand, since the size of the conductive post is limited by the width of the wiring layer when the conductive post is formed, the end area of the formed conductive post is small, so that parasitic capacitance between the conductive post and the metal interconnection layer in the subsequent process layer can be reduced.

In implementation, the material of the initial wiring layer can be aluminum, so that the material is easy to etch when the through holes are formed by etching, the influence on the flatness of the wiring layer formed subsequently is small, and the wiring layer with good flatness can be formed.

The conductive material in the conductive pillars may be copper, the material of the initial wiring layer may be aluminum, and the related art may require formation of solder balls when bonding two chips later, but the embodiment of the present disclosure may not require formation of solder balls, so bonding may be better.

In some embodiments, copper may be deposited in the via to form a conductive pillar in communication with the wiring layer; a seed layer may also be formed in the via prior to electroplating copper to form the conductive pillars.

In some embodiments, the method of forming the semiconductor structure further comprises, prior to filling the conductive material in the via:

step S104, forming an initial isolation layer and an initial barrier layer in sequence in the through hole;

it should be noted that the initial isolation layer and the initial barrier layer are not filled with the via holes. The initial isolation layer may be used to prevent conduction between the conductive material filled in a subsequent process and the substrate, thereby protecting the substrate from damage. The material of the initial isolation layer may be an oxide (e.g., silicon dioxide), a silicon nitride (e.g., silicon nitride), or the like. The initial isolation layer may be formed using PECVD, thermal oxidation techniques (Thermal Oxidation) or vacuum vapor deposition techniques. The PECVD method has high deposition rate, low process temperature and strong film covering capability, and is widely applied to deposition of isolation layer materials such as silicon dioxide, silicon nitride and the like.

The initial barrier layer can not only prevent the conductive material filled in the subsequent process from diffusing, but also improve the adhesive strength of the seed layer. Typical materials for the barrier layer may be titanium, titanium nitride, tantalum nitride, tungsten nitride, vanadium nitride, niobium nitride, or the like.

In practice, the following suitable processes may be employed: PVD, CVD, or plasma enhanced magnetron sputtering techniques (Plasma Enhanced Magnetron Sputtering, PEMS) and the like. When depositing the initial isolation layer and the initial barrier layer in the via hole, the initial isolation layer and the initial barrier layer are also deposited on the wiring layer and the interlayer dielectric layer.

Step S105, back etching the initial isolation layer and the initial barrier layer which are positioned on the top side wall of the through hole and the wiring layer to form the isolation layer and the barrier layer; wherein the top surfaces of the isolation layer and the barrier layer are lower than the top surface of the wiring layer.

Here, the initial isolation layer and the initial barrier layer on the top side wall of the through hole are etched back to conduct the conductive post formed in the subsequent process with the wiring layer. In practice, the top side wall and the initial isolation and initial barrier layers on the wiring layer may be etched back using a dry or wet etch process, for example, the initial isolation and initial barrier layers between 75 and 85 degrees (°) may be removed.

In some embodiments, the thickness of the barrier layer ranges from 0.2 to 0.5 μm; the thickness of the barrier layer ranges from 100 to 500 angstroms

Referring to fig. 6, the initial isolation layer and the initial barrier layer on the top side wall of the via hole and the wiring layer 13 are etched back to form the isolation layer 301 and the barrier layer 302, and it can be seen that the top surfaces of the isolation layer 301 and the barrier layer 302 are lower than the top surface of the wiring layer 13.

With continued reference to fig. 6, a seed layer may be formed on the barrier layer and the conductive layer 303 may be formed using an electroplating process such that the conductive stud 30 includes, in order from the inside to the outside, the conductive layer 303, the seed layer, the barrier layer 302, and the isolation layer 301. Wherein the seed layer is used to provide a bonding effect for the subsequent formation of the conductive layer 303 in the via. The material of the seed layer may be any conductive material, such as tungsten, cobalt, copper, aluminum, or any combination thereof. In practice, the method of forming the seed layer may be the same as the method of forming the barrier layer.

Embodiments of the present disclosure provide a semiconductor structure, referring to fig. 5 or 6, including:

a substrate 40, wherein the substrate 40 at least comprises a subsequent process layer 12 and a wiring layer 13 positioned on the surface of the subsequent process layer 12;

the conductive pillars 30, the conductive pillars 30 penetrate the substrate 40, and the wiring layer 13 includes a portion surrounding and physically contacting the conductive pillars 30.

In some embodiments, conductive post 30 includes, in order from inside to outside, a conductive layer 303, a seed layer, a barrier layer 302, and an isolation layer 301; in some embodiments, conductive post 30 may include, in order from inside to outside, conductive layer 303, barrier layer 302, and isolation layer 301; in some embodiments, the conductive post 30 may also include only the conductive layer 303.

In some embodiments, the base 40 further includes a device layer and substrate 11 underlying the post process layer 12 that is penetrated by the conductive pillars 30. The subsequent process layer 12 includes metal interconnect layers M1, M2, and M3, via V1 and via V2, and an initial interlayer dielectric layer 121, an etch stop layer, and the like.

The conductive posts in the embodiment of the disclosure are surrounded by the wiring layer, and the end areas of the conductive posts are smaller, so that parasitic capacitance between the conductive posts and the metal interconnection layer in the subsequent process layer can be reduced.

In some embodiments, with continued reference to fig. 5, the post-process layer 12 includes a first aperture 122 and a second aperture 123; wherein the first hole 122 is located on the second hole 123, and the opening size of the first hole 122 is larger than the opening size of the second hole 123; the top surface of the conductive post 30 is located between the top surface of the second hole 123 and the top surface of the wiring layer 13.

It should be noted that the opening size of the second hole 123 may be the same as the diameter of the conductive post.

In some embodiments, the top surface of the conductive post 30 may be flush with the top surface of the wiring layer 13.

In some embodiments, with continued reference to fig. 5, the second hole 123 has a portion of the wiring layer 13 on the surface thereof, and the thickness of the portion of the wiring layer 13 in the direction of the sidewall of the second hole 123 gradually decreases with increasing depth.

In some embodiments, referring to fig. 6, a portion of the wiring layer 13 surrounding the conductive pillar 30 includes a first opening B1 and a second opening B2, the first opening B1 being on the second opening B2, an opening size of the first opening B1 being larger than an opening size of the second opening B2; or the inclination angle of the first opening B1 is larger than the inclination angle of the second opening B2, or the opening size of the first opening B1 is larger than the opening size of the second opening B2 and the inclination angle of the first opening B1 is larger than the inclination angle of the second opening B2.

The embodiment of the present disclosure further provides a method for forming a stacked structure, referring to fig. 7, the method including step S201 and step S202, wherein:

step S201, providing a first chip and a second chip; wherein at least one of the first chip and the second chip is formed using the forming method in any of the above embodiments;

here, the first chip and the second chip may be the same chip or may be different chips. The first chip and the second chip may be memory chips or other chips formed by dicing wafers manufactured by a chip manufacturer, wherein one surface of the chips on which circuits or devices are formed is referred to as a front surface of the chips, i.e., a functional surface of the chips, and the opposite surface is referred to as a back surface of the chips.

Step S202, bonding the first chip and the second chip.

Here, the first chip and the second chip may be bonded through the conductive pillars, so that solder balls may not be formed, which may not only simplify the process flow, but also make the stacked structure thinner. In practice, face-to-face bonding, face-to-back, or back-to-back bonding may be employed; the bonding may be performed by thermal bonding, hybrid bonding, or the like.

In the embodiment of the disclosure, since at least one chip of the first chip and the second chip is formed by the forming method in the embodiment of the disclosure, when the first chip and the second chip are bonded, a via is formed between the conductive pillar, the wiring layer and the bonding surface of the first chip and the conductive pillar, the wiring layer and the bonding surface of the second chip, and compared with the via in the related art (the conductive pillar, the metal interconnection layer M1, the other metal interconnection layer in the subsequent process layer, the wiring layer and the bonding surface of the first chip and the conductive pillar, the metal interconnection layer M1, the other metal interconnection layer in the subsequent process layer, the wiring layer and the bonding surface of the second chip), the resistance and the parasitic capacitance in the via in the embodiment of the disclosure are smaller, that is, the method in the embodiment of the disclosure can reduce the parasitic capacitance and the resistance of the multi-chip stacked structure. In addition, the end area of the conductive column is smaller, so that parasitic capacitance between the conductive column and a metal interconnection layer in a later process layer can be reduced.

In some embodiments, a third chip may be formed on the front side of the first chip and/or a fourth chip may be formed on the back side of the second chip, such that a stacked structure including a plurality of chips may be formed.

The structures of the first chip and the second chip in the embodiments of the present disclosure may be understood by referring to the above semiconductor structures, and the structures of the first chip and the second chip have the same technical effects as the above semiconductor structures, which are not described herein.

The disclosed embodiments also provide a stacked structure, referring to fig. 8, comprising: a first chip 100 and a second chip 200, wherein at least one of the first chip and the second chip is formed using the forming method in any of the above embodiments;

the first chip 100 and/or the second chip 200 includes a substrate 40 and a conductive post 30; the substrate 40 includes at least the subsequent process layer 12 and the wiring layer 13 located on the surface of the subsequent process layer 12; the conductive pillars 30 penetrate the substrate 40, and the wiring layer 13 includes a portion surrounding and physically contacting the conductive pillars 30; the first chip 100 and the second chip 200 are bonded through the conductive posts 30.

The chips in the stacked structure in the embodiment of the disclosure are formed by adopting the forming method, so that on one hand, the parasitic capacitance and the resistance of the formed stacked structure are smaller; on the other hand, as the two chips are bonded through the conductive column, no solder balls are required to be formed, so that the stacked structure is thinner; in addition, since the size of the conductive post is limited by the width of the wiring layer when the conductive post is formed, the end area of the formed conductive post is small, so that parasitic capacitance between the conductive post and the metal interconnection layer in the subsequent process layer can be reduced.

In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of the units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.

While the foregoing is directed to embodiments of the present disclosure, the scope of the embodiments of the present disclosure is not limited to the foregoing, and any changes and substitutions that are within the scope of the embodiments of the present disclosure will be readily apparent to those skilled in the art. Therefore, the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:

providing an initial substrate; the initial substrate at least comprises an initial subsequent process layer and an initial wiring layer which is positioned on the initial subsequent process layer and provided with a first groove;

etching the initial substrate along the first groove to form a wiring layer and a through hole;

and filling conductive materials in the through holes to form conductive columns communicated with the wiring layer.

2. The method of claim 1, wherein a portion of the initial wiring layer has a thickness at the bottom of the first recess that is less than a thickness of a portion of the initial wiring layer on the initial subsequent process layer.

3. The method of claim 1, wherein the first recess of the initial routing layer includes a first opening and a second opening, the first opening being on the second opening, the first opening having a greater opening size and/or an angle of inclination than the second opening.

4. The method of forming of claim 1, wherein the initial base further comprises an initial device layer and an initial substrate underlying the initial post process layer;

the providing an initial substrate includes:

providing an initial substrate and forming an initial device layer on the initial substrate;

sequentially forming a metal interconnection layer, an initial etching stop layer and an initial interlayer dielectric layer on the initial device layer;

etching the initial interlayer dielectric layer to the initial etching stop layer to form a second groove so as to form the initial subsequent process layer;

and forming the initial wiring layer in the second groove and on the initial interlayer dielectric layer.

5. The method of forming of claim 4, wherein the initial wiring layer on the initial interlayer dielectric layer has a thickness in the range of 5 to 7 microns; the initial wiring layer thickness on the second recess ranges from 0.3 to 0.6 microns.

6. The method of forming of claim 4, wherein etching the initial substrate along the first recess to form a wiring layer and a via includes:

etching an initial wiring layer downwards based on the first groove, and forming the wiring layer while exposing the initial interlayer dielectric layer;

etching the initial interlayer dielectric layer and the etching stop layer to expose the initial device layer;

and etching the initial device layer and the initial substrate to form the through hole.

7. The method of any of claims 1 to 6, wherein prior to filling the via with conductive material, the method further comprises:

forming an initial isolation layer and an initial barrier layer in the through hole in sequence;

etching back the initial isolation layer and the initial barrier layer which are positioned on the top side wall of the through hole and the wiring layer to form an isolation layer and a barrier layer;

wherein top surfaces of the isolation layer and the barrier layer are lower than top surfaces of the wiring layers.

8. The method of claim 7, wherein the spacer layer has a thickness in the range of 0.2 to 0.5 microns; the barrier layer has a thickness in the range of 100 to 500 angstroms.

9. The method of forming according to any one of claims 1 to 6, wherein a width of the first groove ranges from 5 to 10 μm; the depth of the first groove ranges from 3 to 5 micrometers;

the conductive pillars have a diameter in the range of 3 to 15 microns; the conductive pillars have a length in the range of 30 to 100 microns.

10. A semiconductor structure, comprising:

the substrate at least comprises a subsequent process layer and a wiring layer positioned on the surface of the subsequent process layer;

conductive posts extend through the substrate, and the wiring layer includes portions surrounding and physically contacting the conductive posts.

11. The semiconductor structure of claim 10, wherein the post process layer comprises a first hole and a second hole, wherein the first hole is located over the second hole, the first hole having an opening size that is greater than an opening size of the second hole; the top surface of the conductive post is located between the top surface of the second hole and the top surface of the wiring layer.

12. The semiconductor structure of claim 11, wherein the second hole surface has a portion of the wiring layer, a thickness of the portion of the wiring layer in a direction of a sidewall of the second hole gradually decreasing with increasing depth.

13. The semiconductor structure of claim 11, wherein a portion of the wiring layer surrounding the conductive pillar comprises a first opening and a second opening, the first opening being over the second opening, an opening size and/or an inclination angle of the first opening being greater than the second opening.

14. A method of forming a stacked structure, comprising:

providing a first chip and a second chip; wherein at least one of the first chip and the second chip is formed using the forming method of any one of claims 1 to 9;

and bonding the first chip and the second chip.

15. A stacked structure, comprising: a first chip and a second chip, wherein at least one of the first chip and the second chip is formed using the forming method of any one of claims 1 to 9;

the first chip and/or the second chip comprises a substrate and a conductive column; the substrate at least comprises a subsequent process layer and a wiring layer positioned on the surface of the subsequent process layer; the conductive pillars penetrate the substrate, and the wiring layer includes portions surrounding and physically contacting the conductive pillars; the first chip and the second chip are bonded through the conductive pillars.

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