CN115993746B - Display panel and display device - Google Patents
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- CN115993746B CN115993746B CN202310179020.9A CN202310179020A CN115993746B CN 115993746 B CN115993746 B CN 115993746B CN 202310179020 A CN202310179020 A CN 202310179020A CN 115993746 B CN115993746 B CN 115993746B
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 230000000007 visual effect Effects 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000002349 favourable effect Effects 0.000 description 8
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 239000002131 composite material Substances 0.000 description 4
- HKBLLJHFVVWMTK-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti].[Ti] HKBLLJHFVVWMTK-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Abstract
The embodiment of the application provides a display panel and a display device, wherein in the display panel, a signal line group comprises a first signal line and a second signal line; a first pole of the first type switching transistor is electrically connected with the first signal line, and a second pole of the first type switching transistor is electrically connected with the sub-pixel; the display panel comprises a first edge and a second edge which are opposite, and the second signal line is positioned at one side of the first signal line close to the first edge in the same signal line group; the first type of switching transistors electrically connected with the same first signal line comprise a first transistor and a second transistor, wherein the first transistor is positioned at one side of the signal line group close to the first edge, and the second transistor is positioned at one side of the signal line group close to the second edge; wherein, along the thickness direction of the display panel, the active layer of the first transistor and the first signal line do not overlap, or the area of the active layer of the first transistor overlapping the first signal line is smaller than the area of the active layer of the second transistor overlapping the first signal line. The application can improve the problem of uneven visual effect of the display panel.
Description
[ Field of technology ]
The present application relates to the field of display technologies, and in particular, to a display panel and a display device.
[ Background Art ]
The liquid crystal display panel has the advantages of high brightness, large visual angle, low power consumption, high response speed, long service life and the like, and has wide application in the market.
In a liquid crystal display panel having a touch function, a touch signal line is generally required to transmit touch information. In the prior art, at least part of the touch signal lines are arranged in parallel with the data signal lines in the display panel, and when the sub-pixels electrically connected with the data signal lines are arranged in a zigzag manner, the problem of uneven display occurs due to different charging impedances of the sub-pixels at different positions. Thus, a solution is needed.
[ MEANS FOR SOLVING PROBLEMS ]
In view of the above, the embodiments of the present application provide a display panel and a display device to solve the above-mentioned problems.
In a first aspect, an embodiment of the present application provides a display panel, including a signal line group, a plurality of sub-pixels, and a first type switching transistor; the signal line group comprises a first signal line and a second signal line, the first signal line and the second signal line are arranged along a first direction, the first signal line and the second signal line extend along a second direction, and the first direction is intersected with the second direction; a first pole of the first type switching transistor is electrically connected with the first signal line, and a second pole of the first type switching transistor is electrically connected with the sub-pixel; the display panel comprises a first edge and a second edge which are arranged along a first direction, and the second signal line is positioned at one side of the first signal line close to the first edge in the same signal line group; the plurality of first-type switching transistors electrically connected with the same first signal line comprise a first transistor and a second transistor, wherein the first transistor is positioned at one side of the signal line group close to the first edge, and the second transistor is positioned at one side of the signal line group close to the second edge; wherein, along the thickness direction of the display panel, the active layer of the first transistor and the first signal line do not overlap, or the area of the active layer of the first transistor overlapping the first signal line is smaller than the area of the active layer of the second transistor overlapping the first signal line.
In an implementation manner of the first aspect, along a thickness direction of the display panel, the active layer of the first transistor does not overlap with the first signal line and the second signal line.
In one implementation manner of the first aspect, the display panel includes a plurality of jumper wires, one end of each jumper wire is electrically connected to a first pole of the first transistor, and the other end of each jumper wire is electrically connected to a first signal line in the signal line group; the jumper line overlaps with the first signal line and the second signal line in the signal line group in the thickness direction of the display panel.
In one implementation of the first aspect, the first pole of the first transistor is electrically connected to the first signal line through at least two jumpers.
In one implementation of the first aspect, the first pole of the first transistor is electrically connected to the first signal line through a jumper.
In one implementation of the first aspect, the square resistance of the jumper is smaller than the square resistance of the active layer of the first transistor.
In one implementation of the first aspect, the jumper wire comprises molybdenum.
In one implementation of the first aspect, the first pole of the first transistor is located on a side of the second pole of the first transistor near the signal line group.
In one implementation of the first aspect, the first pole of the first transistor is located on a side of the second pole of the first transistor remote from the signal line group.
In an implementation manner of the first aspect, the display panel further includes a plurality of gate lines extending along the first direction, and the gate lines overlap with the active layer of the first transistor along a thickness direction of the display panel; the first electrode of the first transistor is spaced apart from the gate line overlapped by the first transistor by a distance D1, D1 being 3.6 μm or less and D1 being 5.2 μm or less in the second direction.
In an implementation manner of the first aspect, the display panel further includes a third signal line and a second type switching transistor; the third signal lines and the signal line groups are arranged along the first direction, and the third signal lines extend along the second direction; the first pole of the second type switching transistor is electrically connected with the third signal line, and the second pole is electrically connected with the sub-pixel; an area of the active layer of the first transistor overlapping the first signal line is smaller than an area of the active layer of the second type switching transistor overlapping the third signal line in a thickness direction of the display panel.
In an implementation manner of the first aspect, the plurality of second-type switching transistors electrically connected to the same third signal line include a third transistor and a fourth transistor, where the third transistor is located on a side of the third signal line near the first edge, and the fourth transistor is located on a side of the third signal line near the second edge.
In a second aspect, an embodiment of the present application provides a display device including the display panel provided in the first aspect.
In the embodiment of the application, the active layer of the first transistor is arranged along the thickness direction of the display panel without overlapping with the first signal line, and the first electrode of the first transistor can be arranged on one side of the first signal line close to the first edge, so that the length of the active layer in the first transistor is smaller, the impedance of the first transistor is reduced, the difference between the loss of a signal transmitted to the sub-pixel electrically connected with the first transistor and the loss of a signal transmitted to the sub-pixel electrically connected with the second transistor on the first signal line is reduced, the brightness difference between the sub-pixel electrically connected with the first transistor and the sub-pixel electrically connected with the second transistor is reduced, the brightness uniformity of the display panel is improved, and the display quality of the display panel is improved.
And setting the overlapping area of the active layer of the first transistor and the first signal line to be smaller than the overlapping area of the active layer of the second transistor and the first signal line along the thickness direction of the display panel, so that the coupling capacitance of the active layer of the second transistor and the first signal line can be increased, the difference between the loss of the signal on the first signal line transmitted to the sub-pixel electrically connected with the first transistor and the loss of the signal transmitted to the sub-pixel electrically connected with the second transistor is reduced, the brightness difference between the sub-pixel electrically connected with the first transistor and the sub-pixel electrically connected with the second transistor is reduced, the brightness uniformity of the display panel is improved, and the display quality of the display panel is improved.
[ Description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic plan view of a display panel according to the related art;
FIG. 2 is an enlarged schematic view of the areas Q1 and Q2 in FIG. 1;
fig. 3 is a schematic plan view of a display panel according to an embodiment of the application;
FIG. 4 is an enlarged schematic view of the areas Q1 and Q2 in FIG. 3;
FIG. 5 is a schematic plan view of a display panel according to another embodiment of the present application;
Fig. 6 is a schematic connection diagram of a first transistor and a first signal line according to an embodiment of the present application;
fig. 7 is a schematic diagram of connection between a first transistor and a first signal line according to another embodiment of the present application;
FIG. 8 is a schematic diagram illustrating connection between a first transistor and a first signal line according to an embodiment of the present application
Fig. 9 is a schematic diagram of a display device according to an embodiment of the application.
[ Detailed description ] of the invention
For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the present specification, it is to be understood that the terms "substantially," "approximately," "about," "approximately," "substantially," and the like as used in the claims and embodiments of the application are intended to be inclusive of a reasonable process operation or tolerance and not an exact value.
It should be understood that although the terms first, second, etc. may be used in embodiments of the present application to describe directions, transistors, signal lines, etc., these directions, transistors, signal lines, etc. should not be limited to these terms. These terms are only used to distinguish one direction, transistor, signal line, etc. from another. For example, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction, without departing from the scope of embodiments of the present application.
Fig. 1 is a schematic plan view of a display panel in the related art, and fig. 2 is an enlarged schematic view of the region Q1 and the region Q2 in fig. 1.
In the field of display technology, a subpixel array in a display panel typically includes a plurality of columns of data lines and a plurality of rows of gate lines interleaved with the data lines. When a frame of picture is displayed, the grid line sequentially outputs an enable signal to control the switch transistor in the sub-pixel array to be turned on, and meanwhile, a data signal is provided for the sub-pixels of the corresponding row in the sub-pixel array through the data line.
In a display panel with a touch function, a touch signal line is generally required to transmit touch information. In the related art, at least a part of the touch signal lines are arranged in parallel with the data lines, and when the sub-pixels electrically connected with the data lines are arranged in a zigzag manner, the problem of uneven display occurs due to different charging impedances of the sub-pixels at different positions.
Specifically, as shown in fig. 1 and 2, the display panel 01 'includes a signal line group DL' composed of adjacent data lines DL1 'and touch signal lines DL2', and the data lines DL1 'and the touch signal lines DL2' are arranged along a row direction X 'of the display panel 01' and each extend along a column direction Y 'of the display panel 01'.
The display panel 01' further includes a plurality of sub-pixels 11' and a switching transistor 12', a first pole of the switching transistor 12' is electrically connected to the data line DL1', a second pole of the switching transistor is electrically connected to the sub-pixel 11', and the data line DL1' supplies a data signal to the corresponding sub-pixel 11' through the switching transistor 12 '. The first pole and the second pole of the switching transistor 12 'may be a source and a drain of the switching transistor 12', respectively, and the first pole and the second pole of the switching transistor 12 'may be turned on through the active layer YC'.
The display panel 01 'includes a first edge B1' and a second edge B2 'arranged along the row direction X', and in the same signal line group DL ', the touch signal line DL2' is located at a side of the data line DL1 'close to the first edge B1'. The plurality of switching transistors 12' electrically connected to the data line DL1' of the same signal line group DL ' include a first transistor 121' and a second transistor 122', the first transistor 121' being located at a side of the signal line group DL ' near the first edge B1', and the second transistor 122' being located at a side of the signal line group DL ' near the second edge B2 '. I.e. the first transistor 121 'and the second transistor 122' are arranged in a "zigzag" (zigzag) arrangement. Of course, the sub-pixel 11 'electrically connected to the first transistor 121' and the sub-pixel 11 'electrically connected to the second transistor 122' are also arranged in a "zigzag" (zigzag) arrangement.
As shown in fig. 2, since the touch signal line DL2 'is disposed on the side of the data line DL1' near the first edge B1', when the first electrode of the first transistor 121' is electrically connected to the data line DL1 'through the via hole along the thickness direction of the display panel 01', the active layer YC 'of the first transistor 121' needs to be connected to the data line DL1 'after passing through the touch signal line DL2', which results in the length of the first portion YC1 'of the active layer YC' of the first transistor 121 'being greater than the length of the first portion YC1' of the second transistor 122', and further results in the length of the active layer YC' of the first transistor 121 'being greater than the length of the active layer YC' of the second transistor 122', and the active layer YC' of the first transistor 121 'also overlapping the touch signal line DL2' to generate a coupling capacitance, thereby resulting in the data line DL1 'transmitting data signals to the sub-pixel 11' through the first transistor 121 'and the second transistor 122' transmitting data signals to the sub-pixel 11 'and the same luminance signal to the sub-pixel 11' which is connected to the second transistor 122 'and the luminance signal line 11' is different from the display panel 11.
According to the research, the inventor finds that the square resistance of the transistor active layer is generally larger, the square resistance of the transistor active layer doped with electrons can reach 960 omega/∈8, the square resistance of the transistor active layer doped with holes can reach 2000 omega/∈8, and the impedance of the transistor can be effectively changed by changing the length of the transistor active layer. It becomes a solution by differentially designing the active layers of the first transistor 121 'and the second transistor 122' such that the loss of the data signal through the first transistor 121 'and the second transistor 122' is the same.
The applicant has provided a solution to the problems existing in the prior art by intensive studies.
Fig. 3 is a schematic plan view of a display panel according to an embodiment of the present application, fig. 4 is an enlarged schematic plan view of a region Q1 and a region Q2 in fig. 3, and fig. 5 is a schematic plan view of a further display panel according to an embodiment of the present application.
The embodiment of the present application provides a display panel 01, and in combination with fig. 3 and 4, or as shown in fig. 5, the display panel 01 includes a signal line group DL, a plurality of sub-pixels 11, and a first type switching transistor 12. The signal line group DL includes adjacent first and second signal lines DL1 and DL2, the first and second signal lines DL1 and DL2 may be arranged in the same layer, and no sub-pixel 11 is arranged between the first and second signal lines DL1 and DL 2. The first and second signal lines DL1 and DL2 are arranged along a first direction X, and the first and second signal lines DL1 and DL2 extend along a second direction Y, the first direction X intersecting the second direction Y.
Optionally, the first direction X is a row direction of the display panel 01, the second direction Y is a column direction of the display panel 01, the first signal line DL1 is a data line for transmitting a data signal to the sub-pixel 11 in the display panel 01, and the second signal line DL2 is a touch signal line for transmitting touch information in the display panel 01.
The first pole of the first type switching transistor 12 is electrically connected to the first signal line DL1, and the second pole is electrically connected to the sub-pixel 11, and the first signal line DL1 transmits a signal to the sub-pixel 11 through the first type switching transistor 12. The first and second poles of the first type switching transistor 12 may be source and drain electrodes thereof, respectively, and the first and second poles of the first type switching transistor 12 may be turned on by the active layer YC of the first type switching transistor 12.
The display panel 01 further includes a first edge B1 and a second edge B2 arranged along the first direction X, and the second signal line DL2 is located on a side of the first signal line DL1 near the first edge B1 in the same signal line group DL. The plurality of first type switching transistors 12 electrically connected to the same first signal line DL include a first transistor 121 and a second transistor 122, wherein the first transistor 121 is located at a side of the signal line group DL near the first edge B1, and the second transistor 122 is located at a side of the signal line group DL near the second edge B2. Of course, the sub-pixel 11 electrically connected to the first transistor 121 is located on the side of the signal line group DL near the first edge B1, and the sub-pixel 11 electrically connected to the second transistor 122 is located on the side of the signal line group DL near the second edge B2.
Here, the first transistor 121 is located on a side of the signal line group DL near the first edge B1, which may mean that at least half of the first transistor 121 is located on a side of the signal line group DL near the first edge B1. The second transistor 122 is located at a side of the signal line group DL near the second edge B2, which may mean that at least half of the structure of the second transistor 122 is located at a side of the signal line group DL near the second edge B2.
In which, as shown in fig. 4, the active layer YC of the first transistor 121 does not overlap the first signal line DL1 in the thickness direction of the display panel 01, or, as shown in fig. 5, the area where the active layer YC of the first transistor 121 overlaps the first signal line DL1 is smaller than the area where the active layer YC of the second transistor 122 overlaps the first signal line DL 1.
In the embodiment of the present application, as shown in fig. 3 and fig. 4, the active layer YC of the first transistor 121 is disposed along the thickness direction of the display panel 01 without overlapping the first signal line DL1, and then the first electrode of the first transistor 121 may be disposed on the side of the first signal line DL1 near the first edge B1, so that the length of the active layer YC in the first transistor 121 is smaller, which is beneficial to reducing the impedance of the first transistor 121, reducing the difference between the loss of the signal transmitted to the sub-pixel 11 electrically connected to the first transistor 121 on the first signal line DL1 and the loss of the sub-pixel 11 electrically connected to the second transistor 122, thereby being beneficial to reducing the brightness difference between the sub-pixel 11 electrically connected to the second transistor 122 and the sub-pixel 11 electrically connected to the first transistor 121, improving the brightness uniformity of the display panel 01, and improving the display quality of the display panel 01.
As shown in fig. 5, in the thickness direction of the display panel 01, the area where the active layer YC of the first transistor 121 overlaps the first signal line DL1 is smaller than the area where the active layer YC of the second transistor 122 overlaps the first signal line DL1, so that the coupling capacitance between the active layer YC of the second transistor 122 and the first signal line DL1 can be increased, the difference between the loss of the signal on the first signal line DL1 transmitted to the sub-pixel 11 electrically connected to the first transistor 121 and the loss transmitted to the sub-pixel 11 electrically connected to the second transistor 122 can be reduced, thereby being beneficial to reducing the brightness difference between the sub-pixel 11 electrically connected to the first transistor 121 and the sub-pixel 11 electrically connected to the second transistor 122, improving the brightness uniformity of the display panel 01, and improving the display quality of the display panel 01.
In an embodiment of the present application, referring to fig. 3 and 4, the active layer YC of the first transistor 121 does not overlap with the first signal line DL1 and the second signal line DL2 along the thickness direction of the display panel 01.
Specifically, the active layer YC of the first transistor 121 is located on the side of the second signal line DL2 near the first edge B1. Here, the active layer YC of the first transistor 121 is located on a side of the second signal line DL2 near the first edge B1 may mean that all active layers YC of the first transistor 121 are located on a side of the second signal line DL2 near the first edge B1, that is, the first pole and the second pole of the first transistor 121 may be located on a side of the second signal line DL2 near the first edge B1.
The embodiment of the application can greatly reduce the length of the active layer YC in the first transistor 121, is beneficial to greatly reducing the impedance of the first transistor 121, and is beneficial to further reducing the difference between the loss of the signal on the first signal line DL1 transmitted to the sub-pixel 11 electrically connected with the first transistor 121 and the loss of the signal transmitted to the sub-pixel 11 electrically connected with the second transistor 122, and improving the brightness difference between the sub-pixel 11 electrically connected with the first transistor 121 and the sub-pixel 11 electrically connected with the second transistor 122.
In an embodiment of the present application, please further combine fig. 3 and fig. 4, the display panel 01 includes a plurality of jumper wires SL, one end of each jumper wire SL is electrically connected to the first electrode of the first transistor 121, and the other end of each jumper wire SL is electrically connected to the first signal line DL1 in the signal line group DL.
In the thickness direction of the display panel 01, the jumper line SL overlaps the first signal line DL1 and the second signal line DL2 in the signal line group DL.
That is, after the first and second poles of the first transistor 121 are located at the side of the second signal line DL2 near the first edge B1, the first pole of the first transistor 121 may be electrically connected to the first signal line DL1 through the jumper line SL.
The square resistance of the jumper line SL is smaller than the square resistance of the active layer YC of the first transistor 121.
Optionally, the jumper SL includes molybdenum.
Alternatively, the jumper SL includes titanium aluminum titanium composite metal.
Of course, it is also possible to provide that part of the tracks of the jumper SL comprise molybdenum and the other part of the tracks comprise titanium aluminium titanium composite metal.
It is understood that the sheet resistance of molybdenum is about 0.4Ω/≡and that the sheet resistance of titanium aluminum titanium composite metal is about 0.07 Ω/≡, both of which are much smaller than the sheet resistance of the transistor active layer YC.
In this technical solution, when the length of the active layer YC of the first transistor 121 is set to be smaller, the jumper line SL with smaller sheet resistance is used to electrically connect the first electrode of the first transistor 121 with the first signal line DL1, which is favorable to ensuring that the signal loss of the sub-pixel 11 electrically connected to the first transistor 121 is smaller when the first signal line DL1 is transmitted to the sub-pixel 11 electrically connected to the first transistor 121, so that the difference between the signal loss of the sub-pixel 11 electrically connected to the first transistor 121 and the signal loss of the sub-pixel 11 electrically connected to the second transistor 122 is favorable to reducing, thereby being favorable to reducing the brightness difference between the sub-pixel 11 electrically connected to the first transistor 121 and the sub-pixel 11 electrically connected to the second transistor 122.
In one embodiment of the present application, please continue to refer to fig. 4, the first pole of the first transistor 121 may be electrically connected to the first signal line DL1 through at least two jumper lines SL.
It should be noted that fig. 4 only illustrates that the first pole of the first transistor 121 is electrically connected to the first signal line DL1 through two jumper lines SL, and in some other embodiments, the first pole of the first transistor 121 may also be electrically connected to the first signal line DL1 through three or more jumper lines SL.
The embodiment of the application can reduce the resistance of the total jumper line SL between the first transistor 121 and the first signal line DL1, which is beneficial to reducing the voltage drop of the first signal line DL1 for transmitting the electric signal to the first transistor 121.
Fig. 6 is a schematic diagram of connection between a first transistor and a first signal line according to an embodiment of the present application.
In one embodiment of the present application, as shown in fig. 6, the first pole of the first transistor 121 is electrically connected to the first signal line DL1 through a jumper line SL.
Since the jumper line SL overlaps the second signal line DL2, a coupling capacitance is generated between the jumper line SL and the second signal line DL 2. Therefore, in the embodiment of the present application, the first pole of the first transistor 121 is electrically connected to the first signal line DL1 through the jumper line SL, so that the overlapping area of the jumper line SL and the second signal line DL2 can be reduced, which is beneficial to reducing the coupling capacitance between the jumper line SL and the second signal line DL2, and further reducing the loss of the first signal line DL1 transmitting the electrical signal to the first transistor 121.
In one embodiment of the present application, please continue to refer to fig. 4 and 6, the first pole of the first transistor 121 is located at a side of the second pole of the first transistor 121 near the signal line group DL.
That is, the first pole of the first transistor 121 electrically connected to the first signal line DL1 is close to the first signal line DL1 with respect to the second pole of the first transistor 121.
In the embodiment of the application, the distance between the first electrode of the first transistor 121 and the first signal line DL1 is shorter, which is favorable for reducing the length of the jumper line SL between the first electrode of the first transistor 121 and the first signal line DL1, so as to be favorable for ensuring that the signal loss of the first signal line DL1 transmitted to the sub-pixel 11 after passing through the jumper line SL and the first transistor 121 is less, and reducing the brightness difference between the sub-pixel 11 electrically connected by the first transistor 121 and the sub-pixel 11 electrically connected by the second transistor 122.
Fig. 7 is a schematic diagram of connection between a first transistor and a first signal line according to another embodiment of the present application. In some other embodiments, as shown in fig. 7, the first pole of the first transistor 121 may also be located at a side of the second pole of the first transistor 121 away from the signal line group DL. At this time, most of the wirings of the jumper SL electrically connected to the first electrode of the first transistor 121 may be made of titanium-aluminum-titanium composite metal material, so as to greatly reduce the sheet resistance of the jumper SL.
Fig. 8 is a schematic diagram of connection between a first transistor and a first signal line according to another embodiment of the present application.
In one embodiment of the present application, as shown in connection with fig. 3 and 8, the display panel 01 further includes a plurality of gate lines SP extending in the first direction X, the plurality of gate lines SP being arranged in the second direction Y. The gate line SP overlaps the active layer YC of the first transistor 121 in the thickness direction of the display panel 01. Of course, the active layer YC of the second transistor 122 also overlaps the gate line SP in the thickness direction of the display panel 01. Also, in the thickness direction of the display panel 01, the first transistors 121 and the second transistors 122 of different rows overlap with different gate lines SP, respectively.
Here, a portion of the gate line SP overlapping the active layer YC of the first transistor 121 may be a gate electrode of the first transistor 121.
The distance of the gate line SP overlapped by the first electrode of the first transistor 121 and the active layer YC of the first transistor 121 in the second direction Y is D1,3.6 μm and D1 and 5.2 μm.
In one layout design of the first transistor 121, as shown in fig. 8, the first and second poles of the first transistor 121 may be located at the same side of the gate line SP overlapped by the first transistor 121, and in order to ensure that the active layer YC of the first transistor 121 overlaps the gate line SP extending in the first direction X in the thickness direction of the display panel 01, the active layer YC of the first transistor 121 generally includes a portion extending in the first direction X and a portion extending in the second direction Y. Also, a portion of the active layer YC extending in the second direction Y protrudes beyond an edge of the gate line SP in the second direction Y.
In the embodiment of the present application, setting 3.6 μm is less than or equal to D1 is less than or equal to 5.2 μm, so that the length of the portion extending along the second direction Y in the active layer YC of the first transistor 121 is not excessively long under the condition that the process condition is satisfied, which is favorable for reducing the total length of the active layer YC in the first transistor 121, thereby being favorable for reducing the difference between the signal loss transmitted from the first signal line DL1 to the sub-pixel 11 electrically connected to the first transistor 121 and the signal loss transmitted to the sub-pixel 11 electrically connected to the second transistor 122, and further favorable for reducing the brightness difference between the sub-pixel 11 electrically connected to the second transistor 122 and the sub-pixel 11 electrically connected to the first transistor 121.
Preferably d1=3.6 μm in order to reduce the total length of the active layer YC in the first transistor 121 to a large extent.
With continued reference to fig. 5, in an embodiment of the present application, the display panel 01 further includes a third signal line DL3 and a second type switching transistor 13, the third signal line DL3 and the signal line group DL are arranged along the first direction X, and the third signal line DL3 extends along the second direction Y. The third signal line DL3 may be a data line transmitting a data signal to the sub-pixel 11 in the display panel 01.
The third signal line DL3 may be different from the first signal line DL1 in that the second signal line DL2 is not provided around the third signal line DL3, and the sub-pixel 11 is generally provided between the third signal line DL3 and the second signal line DL2 in the signal line group DL.
The first pole of the second type switching transistor 13 is electrically connected to the third signal line DL3, and the second pole is electrically connected to the sub-pixel 11. The third signal line DL3 transmits a signal to the sub-pixel 11 through the second type switching transistor 13. The first pole and the second pole of the second type switching transistor 13 may be a source and a drain thereof, respectively, and the first pole and the second pole of the second type switching transistor 13 may be turned on by the active layer YC of the second type switching transistor 13.
Optionally, the plurality of second-type switching transistors 13 electrically connected to the same third signal line DL3 include a third transistor 131 and a fourth transistor 132, where the third transistor 131 is located on a side of the third signal line DL3 near the first edge B1, and the fourth transistor 132 is located on a side of the third signal line DL3 near the second edge B2. I.e. the third and fourth transistors 131, 132 may be arranged in a "zigzag" (zigzag) arrangement. Of course, the sub-pixel 11 electrically connected to the third transistor 131 and the sub-pixel 11 electrically connected to the fourth transistor 132 are also arranged in a "zigzag" (zigzag) arrangement.
In the thickness direction of the display panel 01, an area where the active layer YC of the first transistor 121 overlaps the first signal line DL1 is smaller than an area where the active layer YC of the second type switching transistor 13 overlaps the third signal line DL 3.
It will be appreciated that in the related art, the length of the active layer YC of the second type switching transistor 13 is generally smaller than that of the first transistor 121, resulting in a difference in brightness between the sub-pixel 11 to which the first transistor 121 is electrically connected and the sub-pixel 11 to which the second type switching transistor 13 is electrically connected.
In the embodiment of the present application, the overlapping area of the active layer YC of the first transistor 121 and the first signal line DL1 is smaller than the overlapping area of the active layer YC of the second type switching transistor 13 and the third signal line DL3 along the thickness direction of the display panel 01, so that the coupling capacitance between the second type switching transistor 13 and the third signal line DL3 can be increased, the loss of the signal on the first signal line DL1 through the first transistor 121 and the loss difference of the signal on the third signal line DL3 through the second type switching transistor 13 can be reduced, thereby being beneficial to reducing the brightness difference between the sub-pixel 11 electrically connected with the first transistor 121 and the sub-pixel 11 electrically connected with the second type switching transistor 13, further improving the brightness uniformity of the display panel 01, and improving the display quality of the display panel 01.
It should be noted that, in the embodiment of the present application, along the thickness direction of the display panel 01, the overlapping area of the active layer YC of the first transistor 121 and the first signal line DL1 may be smaller than the overlapping area of the active layer YC of the second transistor 122 and the first signal line DL1, and the overlapping area of the active layer YC of the second transistor 122 and the first signal line DL1 may be approximately the same as the overlapping area of the active layer YC of the second switching transistor 13 and the third signal line DL3, so that the brightness between the sub-pixel 11 electrically connected to the first transistor 121, the sub-pixel 11 electrically connected to the second transistor 122, and the sub-pixel 11 electrically connected to the second switching transistor 13 may be approximately the same, thereby achieving the effect of uniform viewing effect of the display panel 01.
Fig. 9 is a schematic diagram of a display device according to an embodiment of the application.
An embodiment of the present application provides a display device 02, as shown in fig. 9, including a display panel 01 provided in the above embodiment. The display device 02 provided in the embodiment of the present application may be an electronic device such as a mobile phone, a vehicle-mounted display, a computer, a television, and the like, which is not limited by the present application.
In the display device 02, if the active layer YC of the first transistor 121 is disposed without overlapping the first signal line DL1 along the thickness direction of the display panel 01, the first electrode of the first transistor 121 may be disposed on the side of the first signal line DL1 near the first edge B1, so that the length of the active layer YC in the first transistor 121 is smaller, which is beneficial to reducing the impedance of the first transistor 121, reducing the difference between the loss of the signal on the first signal line DL1 transmitted to the sub-pixel 11 electrically connected to the first transistor 121 and the loss transmitted to the sub-pixel 11 electrically connected to the second transistor 122, thereby being beneficial to reducing the brightness difference between the sub-pixel 11 electrically connected to the first transistor 121 and the sub-pixel 11 electrically connected to the second transistor 122, improving the brightness uniformity of the display panel 01, and improving the display quality of the display panel 01.
In the thickness direction of the display panel 01, the overlapping area of the active layer YC of the first transistor 121 and the first signal line DL1 is smaller than the overlapping area of the active layer YC of the second transistor 122 and the first signal line DL1, so that the coupling capacitance between the active layer YC of the second transistor 122 and the first signal line DL1 can be increased, the difference between the loss of the signal transmitted to the sub-pixel 11 electrically connected to the first transistor 121 and the loss of the signal transmitted to the sub-pixel 11 electrically connected to the second transistor 122 on the first signal line DL1 can be reduced, the brightness difference between the sub-pixel 11 electrically connected to the first transistor 121 and the sub-pixel 11 electrically connected to the second transistor 122 can be reduced, the brightness uniformity of the display panel 01 can be improved, and the display quality of the display panel 01 can be improved.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (13)
1. A display panel, comprising:
A signal line group including a first signal line and a second signal line, the first signal line and the second signal line being arranged in a first direction, and the first signal line and the second signal line extending in a second direction, the first direction intersecting the second direction;
a plurality of sub-pixels;
A first-type switching transistor having a first pole electrically connected to the first signal line and a second pole electrically connected to the sub-pixel;
The display panel comprises a first edge and a second edge which are arranged along the first direction, and the second signal line is positioned at one side of the first signal line close to the first edge in the same signal line group; the plurality of first type switching transistors electrically connected with the same first signal line comprise a first transistor and a second transistor, wherein the first transistor is positioned on one side of the signal line group close to the first edge, and the second transistor is positioned on one side of the signal line group close to the second edge;
Wherein, along the thickness direction of the display panel, the active layer of the first transistor and the first signal line are not overlapped or overlapped; when the active layer of the first transistor overlaps the first signal line, an area of the active layer of the first transistor overlapping the first signal line is smaller than an area of the active layer of the second transistor overlapping the first signal line.
2. The display panel according to claim 1, wherein an active layer of the first transistor does not overlap with the first signal line and the second signal line in a thickness direction of the display panel.
3. The display panel according to claim 2, wherein the display panel includes a plurality of jumper wires, one end of the jumper wires being electrically connected to a first pole of the first transistor, and the other end being electrically connected to a first signal line of the signal line group;
The jumper line overlaps with the first signal line and the second signal line in the signal line group in a thickness direction of the display panel.
4. A display panel according to claim 3, wherein a first pole of the first transistor is electrically connected to the first signal line through at least two of the jumper lines.
5. A display panel according to claim 3, wherein the first pole of the first transistor is electrically connected to the first signal line through one of the jumper lines.
6. The display panel according to claim 3, wherein a sheet resistance of the jumper is smaller than a sheet resistance of an active layer of the first transistor.
7. The display panel of claim 6, wherein the jumper wire comprises molybdenum.
8. A display panel according to claim 3, wherein the first pole of the first transistor is located on a side of the second pole of the first transistor adjacent to the signal line group.
9. A display panel according to claim 3, wherein the first pole of the first transistor is located on a side of the second pole of the first transistor remote from the signal line group.
10. The display panel according to claim 1, further comprising a plurality of gate lines extending in the first direction, the gate lines overlapping the active layer of the first transistor in a thickness direction of the display panel;
The distance between the first pole of the first transistor and the grid line overlapped by the first transistor in the second direction is D1, D1 which is more than or equal to 3.6 mu m and less than or equal to 5.2 mu m.
11. The display panel according to claim 1, the display panel is characterized in that the display panel further comprises:
A third signal line arranged along the first direction with the signal line group, the third signal line extending along the second direction;
a second type switching transistor having a first electrode electrically connected to the third signal line and a second electrode electrically connected to the sub-pixel;
an area of the active layer of the first transistor overlapping the first signal line is smaller than an area of the active layer of the second type switching transistor overlapping the third signal line in a thickness direction of the display panel.
12. The display panel according to claim 11, wherein among the plurality of the second-type switching transistors electrically connected to the same third signal line, a third transistor and a fourth transistor are included, the third transistor being located on a side of the third signal line close to the first edge, and the fourth transistor being located on a side of the third signal line close to the second edge.
13. A display device comprising a display panel according to any one of claims 1-12.
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| CN202310179020.9A CN115993746B (en) | 2023-02-28 | 2023-02-28 | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112289267A (en) * | 2020-10-30 | 2021-01-29 | 昆山国显光电有限公司 | Pixel circuit and display panel |
| CN113066868A (en) * | 2021-04-25 | 2021-07-02 | 厦门天马微电子有限公司 | Thin film transistor, display panel and display device |
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| JP6167374B2 (en) * | 2014-06-13 | 2017-07-26 | 株式会社Ｊｏｌｅｄ | Display panel inspection method and display panel manufacturing method |
| KR20210001277A (en) * | 2019-06-27 | 2021-01-06 | 엘지디스플레이 주식회사 | Display device |
| KR20220031289A (en) * | 2020-09-04 | 2022-03-11 | 엘지디스플레이 주식회사 | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112289267A (en) * | 2020-10-30 | 2021-01-29 | 昆山国显光电有限公司 | Pixel circuit and display panel |
| CN113066868A (en) * | 2021-04-25 | 2021-07-02 | 厦门天马微电子有限公司 | Thin film transistor, display panel and display device |
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