CN115987999A

CN115987999A - Master-slave competition method and device for multi-machine system, ARM and storage medium

Info

Publication number: CN115987999A
Application number: CN202211526429.5A
Authority: CN
Inventors: 徐晓翔; 陈景; 董丽芳
Original assignee: Xiamen Kecan Information Technology Co ltd; Kehua Data Co Ltd
Current assignee: Xiamen Kehua Digital Energy Tech Co Ltd
Priority date: 2022-11-30
Filing date: 2022-11-30
Publication date: 2023-04-18

Abstract

The invention provides a master-slave competition method and device of a multi-machine system, an ARM and a storage medium. The method is applied to ARM and comprises the following steps: acquiring a communication ID of the user, and sending a heartbeat frame containing the communication ID of the user; receiving heartbeat frames sent by other ARM; the heartbeat frames sent by other ARM contain the communication ID of the corresponding other ARM; if the received communication IDs meet the preset conditions within the first preset time, determining that the communication IDs are the ARM standby host; sending a host confirmation frame to the DSP host; wherein, the DSPs of at least two devices comprise a DSP host; after receiving the host confirmation frame, the DSP host replies a successful confirmation frame; and when a successful confirmation frame replied by the DSP host is received, determining the DSP host as the ARM host. The invention can realize automatic election of the ARM hosts among the plurality of ARM hosts so as to facilitate the communication with the outside and ensure the communication reliability of a multi-machine system.

Description

Master-slave competition method and device for multi-machine system, ARM and storage medium

Technical Field

The invention relates to the technical field of master-slave competition, in particular to a master-slave competition method and device of a multi-machine system, an ARM and a storage medium.

Background

For stand-alone systems, communication is made with one or more units through a single device. When the single device fails, the single device cannot communicate with each unit any more, and the reliability of the single-machine system is poor.

In order to solve the problem of poor reliability of the single-computer system, a multi-computer system is proposed, however, for the multi-computer system, one host needs to be selected for external communication, and therefore the multi-computer system needs to have a master-slave competition mechanism. At present, a master-slave competition method for a multi-computer system is lacked to ensure the reliability of external communication of the multi-computer system.

Disclosure of Invention

The embodiment of the invention provides a master-slave competition method and device for a multi-computer system, an ARM (advanced RISC machine) and a storage medium, and aims to solve the problem that the conventional method lacks a master-slave competition method for the multi-computer system so as to ensure the reliability of external communication of the multi-computer system.

In a first aspect, an embodiment of the present invention provides a master-slave contention method for a multi-machine system, where the multi-machine system includes at least two devices, each device includes an ARM and a DSP, each ARM is in communication connection, and each ARM is in communication connection with the DSP; the master-slave competition method of the multi-machine system is applied to ARM and comprises the following steps:

acquiring a communication ID of the user, and sending a heartbeat frame containing the communication ID of the user;

receiving heartbeat frames sent by other ARM; the heartbeat frames sent by other ARM contain the communication ID of the corresponding other ARM;

if the received communication IDs meet the preset conditions within the first preset time, determining that the communication IDs are the ARM standby host;

sending a host confirmation frame to the DSP host; wherein, the DSPs of at least two devices comprise a DSP host; after receiving the host confirmation frame, the DSP host replies a successful confirmation frame;

and when a successful confirmation frame replied by the DSP host is received, determining the DSP host as the ARM host.

In one possible implementation, the preset conditions include: the received communication IDs are all smaller than the own communication ID, or the received communication IDs are all larger than the own communication ID.

In a possible implementation manner, after receiving heartbeat frames sent by other ARM, the multi-machine system master-slave contention method further includes:

and if the communication ID which does not meet the preset condition is received within the first preset time, determining that the communication ID is the ARM slave machine.

In one possible implementation manner, acquiring a communication ID of itself and sending a heartbeat frame including the communication ID of itself includes:

and if the heartbeat frame containing the ARM host identity is not received within the second preset time length, acquiring the own communication ID and sending the heartbeat frame containing the own communication ID.

In a possible implementation manner, after determining that the host is an ARM host, the master-slave contention method of the multi-computer system further includes:

setting the desynchronization flag bit of each ARM slave machine to inform each ARM slave machine of parameter synchronization, so that each ARM slave machine and the ARM master machine keep parameter synchronization; after keeping parameter synchronization with the ARM host, each ARM slave machine sends a synchronization flag bit clearing instruction to the ARM host;

and when receiving a command of clearing the synchronous flag bit sent by the ARM slave machine, resetting the asynchronous flag bit of the ARM slave machine.

In one possible implementation manner, after determining that the host is an ARM host, the master-slave contention method of the multi-computer system further includes:

when the offline ARM slave machine is detected to exist, setting the desynchronizing flag bit of the offline ARM slave machine so as to synchronize parameters when the offline ARM slave machine is recovered to be online; and when the ARM host does not receive the heartbeat packet of the ARM slave machine within the third preset time length, judging that the ARM slave machine is offline.

In a possible implementation mode, the ARM and the DSP are in communication connection through a first CAN bus;

and each DSP is also in communication connection through a second CAN bus.

In a second aspect, an embodiment of the present invention provides a master-slave competition device for a multi-machine system, where the multi-machine system includes at least two devices, each device includes an ARM and a DSP, each ARM is in communication connection, and each ARM is in communication connection with the DSP; the master-slave competition device of the multi-machine system is applied to the ARM and comprises the following components:

the acquisition module is used for acquiring the communication ID of the acquisition module and sending the heartbeat frame containing the communication ID of the acquisition module;

the receiving module is used for receiving heartbeat frames sent by other ARM; the heartbeat frames sent by other ARM contain the communication ID of the corresponding other ARM;

the standby host judgment module is used for determining that the standby host is an ARM standby host if the received communication IDs meet the preset conditions within a first preset time length;

the system comprises a confirmation frame sending module, a DSP host and a host, wherein the confirmation frame sending module is used for sending a host confirmation frame to the DSP host; wherein, the DSPs of at least two devices comprise a DSP host; after receiving the host confirmation frame, the DSP host replies a successful confirmation frame;

and the host judgment module is used for determining the host to be the ARM host when receiving the successful confirmation frame replied by the DSP host.

In a third aspect, an embodiment of the present invention provides an ARM, including a processor and a memory, where the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory, and execute the master-slave contention method of the multi-computer system according to the first aspect or any possible implementation manner of the first aspect.

In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored, and the computer program, when executed by a processor, implements the steps of the master-slave contention method of a multi-computer system according to the first aspect or any one of the possible implementations of the first aspect.

The embodiment of the invention provides a master-slave competition method and device for a multi-machine system, an ARM and a storage medium, wherein automatic master-slave competition among the ARM is carried out through communication IDs of the ARM, the successfully-competitive ARM is used as an ARM standby host, then secondary arbitration is carried out through a DSP host, and the ARM standby host becomes the ARM host after the DSP host is successfully confirmed, so that the ARM hosts are automatically selected out among the ARM hosts, communication with the outside is facilitated, and the communication reliability of the multi-machine system is ensured.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a schematic diagram of a multi-machine system provided by an embodiment of the present invention;

fig. 2 is a flowchart illustrating a master-slave contention method of a multi-computer system according to an embodiment of the present invention;

fig. 3 is a flowchart illustrating a master-slave contention method of another multi-computer system according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a master/slave competition device of a multi-machine system according to an embodiment of the present invention;

fig. 5 is a schematic diagram of an ARM according to an embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

To make the objects, technical solutions and advantages of the present invention more apparent, the following description will be made by way of specific embodiments with reference to the accompanying drawings.

Referring to fig. 1, a schematic diagram of a multi-machine system is shown, wherein only the parts relevant to the embodiment of the present invention are shown for convenience of illustration.

The multi-machine system comprises at least two devices, each device comprises an ARM (Advanced RISC Machines) and a DSP (Digital Signal Processor), the ARM and the DSP are in communication connection, and the ARM can be used as a local controller. A DSP host exists among all DSPs of the multi-machine system, and other DSPs are all DSP slave machines. An ARM host exists among all ARM of the multi-machine system, and other ARM are all ARM slave machines. The master-slave competition method of the multi-machine system is applied to the ARM and used for competing out of the ARM host so that the multi-machine system can communicate with the outside through the ARM host. Because the multi-machine system is presented as a whole, the ARM is required to have a master-slave competition mechanism, only one host responds to north communication at the same time, and master-slave switching can be performed when the current ARM host is abnormal, so that the reliability of north-south communication control is ensured.

Each ARM is separately powered along with the complete machine, and the ARM is redundant and backup mutually. The ARM and the DSP communicate and multiplex a CAN (Controller Area Network) bus, which is called a first CAN bus, that is, CAN1 in fig. 1, and a ring connection. An independent CAN bus, namely a second CAN bus, CAN2 in figure 2 is also arranged between the DSPs, and is used for the DSPs to communicate with each other and compete out a DSP host, so that the communication reliability CAN be improved. The competing host between the DSPs may adopt any existing method, and is not limited herein.

In some possible implementations, the devices in the multi-machine system may be in a parallel relationship. The devices in the multi-machine system may be devices such as an energy storage converter, and are not limited herein.

Referring to fig. 2, it shows a flowchart of an implementation of a master-slave contention method of a multi-machine system according to an embodiment of the present invention. The multi-machine system comprises at least two devices, wherein each device comprises an ARM and a DSP, the ARM is in communication connection with the DSP, and the ARM and the DSP are in communication connection with each other; the master-slave competition method of the multi-machine system is applied to the ARM, namely the execution main body of the method can be the ARM.

Referring to fig. 2, the master-slave contention method of the multi-machine system includes:

in S101, the own communication ID is acquired, and the heartbeat frame including the own communication ID is transmitted.

After the ARM is powered on, the communication ID of the ARM can be read from the database. The communication ID of each ARM is different, and the communication ID can be used for uniquely identifying each ARM. The communication ID may be a number.

After the ARM acquires the communication ID of the ARM, the heartbeat frame of the ARM is generated according to the communication ID of the ARM, and the heartbeat frame of the ARM is sent through the CAN bus. The heartbeat frame may also be referred to as a heartbeat packet.

In S102, receiving heartbeat frames sent by other ARM; the heartbeat frames sent by other ARM contain the communication ID of the corresponding other ARM.

Each ARM will send a new adjustment containing its own communication ID and receive heartbeat frames sent by other ARMs. The other ARM refers to all the ARMs except the ARM currently used as the execution subject in the multi-machine system.

In S103, if the received communication IDs all satisfy the preset condition within the first preset time period, it is determined that the host is an ARM standby host.

The setting of the first preset time length meets the condition that when all the ARM works normally, the current ARM can receive heartbeat frames containing communication IDs of all other ARM in the first preset time length.

If the communication IDs contained in all the received heartbeat frames meet the preset condition within the first preset time length of the ARM, the ARM standby host can be determined to be the ARM standby host, and the ARM standby host mode can be entered.

The preset condition may be set according to actual requirements, and is not specifically limited herein.

In S104, sending a host confirmation frame to the DSP host; wherein, the DSP of at least two devices comprises a DSP host; and the DSP host replies a successful confirmation frame after receiving the host confirmation frame.

When the host is switched to the ARM standby host, the host can be switched to the ARM host formally only by confirming the host by the DSP host. Therefore, the host acknowledgement frame is sent to the DSP host to instruct the DSP host to reply to the successful acknowledgement frame. The DSP host will reply with a successful acknowledgment frame as long as it can receive the host acknowledgment frame.

ARM and DSP share the same communication bus, rely on the principal and subordinate competition mechanism of DSP, because DSP has only a DSP host computer at the same time, the final decision authority of ARM host computer is handed over by the DSP host computer in this application, can prevent that many host computers appear when the circuit disconnection forms more than 2 islands between the ARM, utilize the single host computer of DSP, carry out the secondary and confirm, guarantee that only has a host computer in the system, can solve the problem of many host computers of ARM.

In S105, when a successful acknowledgement frame returned by the DSP host is received, it is determined that the DSP host is an ARM host.

After the host confirmation frame is sent, if the successful confirmation frame replied by the DSP host is received, the ARM standby host is switched to the ARM host, and the mode of the ARM host is entered.

In some possible implementation modes, after the ARM host is determined, a master-slave switching log is generated and recorded.

The master-slave competition method shown in S101 to S105 may be used when the multi-machine system is just powered on, to start master-slave competition from a state without a host machine to compete for the ARM host machine; the method can also be used for carrying out master-slave competition by other ARM hosts after the current ARM host is abnormal or fails and cannot be continuously used as the ARM host during power-on, so as to compete out a new ARM host.

According to the embodiment, automatic master-slave competition among the ARM is carried out through the communication ID of each ARM, the successfully-competed ARM serves as the ARM standby host, secondary arbitration is carried out through the DSP host, and after the DSP host is successfully confirmed, the ARM standby host becomes the ARM host, so that the ARM host can be automatically competed and selected among the ARM hosts, communication with the outside is facilitated, and the communication reliability of a multi-machine system is guaranteed.

In some possible implementation manners, in order to meet different wiring applications and debugging conditions in the field, the method of S101 to S105 may be adopted in the embodiment to implement ARM master-slave competition in the automatic mode, and the ARM host may be set in the manual mode.

In the manual mode, the ARM can operate according to a preset master-slave mode. In the operation process, each ARM can send a master-slave mark and a manual/automatic mode in heartbeat, and when the modes are not matched, no host computer exists and the states of multiple host computers exist, corresponding alarm needs to be given. Wherein, the staff can set up the master-slave mode of each ARM through the web or corresponding display screen.

In some embodiments, in S103, the preset condition includes: the received communication IDs are all smaller than the own communication ID, or the received communication IDs are all larger than the own communication ID.

It should be noted that the preset condition may be set according to the contention logic of the ARM host. For example, if the ARM host is an ARM with the minimum communication ID, the preset condition is that the received communication IDs are all larger than the communication ID of the ARM host; assuming that the ARM host is the ARM with the largest communication ID, the preset condition is that the received communication IDs are all smaller than the communication ID of the ARM host. The preset condition may also be other conditions that can be realized, and is not particularly limited herein.

In some embodiments, after the S102, the multi-computer system master-slave competition method further includes:

Within the first preset time length, as long as the communication ID which does not meet the preset condition is received, the self can be determined to be the ARM slave machine, and the ARM slave machine mode is entered.

In some embodiments, the S101 may include:

Under normal conditions, the ARM slave machine may periodically receive a heartbeat frame containing an ARM host machine identifier sent by the ARM host machine, and if the heartbeat frame containing the ARM host machine identifier is not received within a certain time period, for example, within a second preset time period, it is determined that the ARM host machine is abnormal (damaged or powered off, etc.), and the host machine needs to be reselected, at this time, the methods of S101 to S105 may be executed to perform master-slave competition, and compete out a new ARM host machine.

The second preset time period may be set according to actual requirements, and is not limited specifically here. The ARM host identifier may be a preset ARM host tag or an ARM host ID.

In some embodiments, after determining itself to be an ARM master, the master-slave contention method of the multi-machine system further includes:

setting the desynchronization flag bit of each ARM slave machine to inform each ARM slave machine to carry out parameter synchronization so that each ARM slave machine and the ARM host machine keep parameter synchronization; after keeping parameter synchronization with the ARM host, each ARM slave machine sends a synchronization flag bit clearing instruction to the ARM host;

and when receiving a command of clearing the synchronous zone bit sent by the ARM slave machine, resetting the asynchronous zone bit of the ARM slave machine.

The asynchronous flag bit of each ARM slave machine is used for indicating whether each ARM slave machine needs to synchronize the parameters of the ARM master machine. After the flag bit is set, the corresponding ARM slave machine needs to synchronize the parameters of the ARM master machine, so that the ARM slave machine and the ARM master machine keep parameter synchronization, namely the parameters are consistent; when the flag bit is reset, the corresponding ARM slave computer does not need to synchronize the parameters of the ARM master computer.

After the ARM master machine is competed, the ARM master machine can set the desynchronization flag bit of each ARM slave machine and send a broadcast frame to each slave machine to prompt each ARM slave machine to carry out parameter synchronization. Each ARM slave machine sends a parameter request frame to request synchronous parameters after detecting that the ID of the ARM slave machine is out of synchronization, sends a command of clearing synchronous flag bits to the ARM master machine after synchronization is completed, and stores the synchronous parameters into a database. After receiving the command of clearing the synchronous flag bit of the ARM slave machine, the ARM master machine resets the asynchronous flag bit of the ARM slave machine.

The parameters to be synchronized between the ARM master and the ARM slave may include: ARM quantity, network parameters, northbound communication parameters, planning curves, electricity price setting and the like.

In some possible implementation manners, when the ARM host receives the system setting parameters issued by northbound, QT and web, the desynchronization flag bit of each ARM slave can be set, and each ARM slave is notified to resynchronize.

The ARM host computer needs to detect the communication state of each ARM slave computer in real time, and when the ARM slave computers are offline, the position of the asynchronous mark of the ARM slave computers needs to be started so as to ensure that the ARM slave computers can resynchronize parameters when communication is recovered. And judging that the ARM slave machine is offline if the heartbeat packet of the ARM slave machine is not received within a certain time. The third preset time period may be set according to actual requirements, and is not limited specifically here.

In some embodiments, referring to fig. 1, each ARM and DSP are communicatively connected via a first CAN bus CAN 1; and all the DSPs are also in communication connection through a second CAN bus CAN 2.

Referring to fig. 1, the ring-shaped wiring between the ARM and the DSP performs communication through a first CAN bus CAN1. In addition, the DSPs CAN communicate with each other through a second CAN bus, namely a communication standby path.

And master-slave competition CAN be carried out between the ARM through the first CAN bus CAN1 to obtain the ARM standby host, and the ARM standby host CAN communicate with the DSP host through the first CAN bus CAN1.

And the DSP CAN carry out master-slave competition through a second CAN bus to obtain a DSP host. The communication reliability CAN also be increased by means of the second CAN bus CAN 2.

In a specific application scenario, the flow of ARM master-slave contention is shown in fig. 3, in which an ARM with the smallest communication ID serves as a master.

In some possible implementations, when the CAN master-slave contention thread detects that the master-slave flag changes, the local IP needs to be switched, and the master-slave flag is written into the shared memory. And other processes detect the master-slave marks in real time and carry out mode switching aiming at related functions.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

The following are embodiments of the apparatus of the invention, reference being made to the corresponding method embodiments described above for details which are not described in detail therein.

Fig. 4 shows a schematic structural diagram of a master-slave competition device of a multi-machine system provided by an embodiment of the present invention, and for convenience of description, only parts related to the embodiment of the present invention are shown, and detailed descriptions are as follows:

the multi-machine system comprises at least two devices, wherein each device comprises an ARM and a DSP; the master-slave competition device of the multi-machine system is applied to the ARM, the ARM is in communication connection, and the ARM and the DSP are in communication connection; as shown in fig. 4, the master-slave competition device 30 of the multi-machine system may include: the device comprises an acquisition module 31, a receiving module 32, a standby host judgment module 33, an acknowledgement frame sending module 34 and a host judgment module 35.

An obtaining module 31, configured to obtain a communication ID of itself and send a heartbeat frame including the communication ID of itself;

a receiving module 32, configured to receive heartbeat frames sent by other ARM; the heartbeat frames sent by other ARM contain the communication ID of the corresponding other ARM;

the standby host judgment module 33 is configured to determine that the host is an ARM standby host if the received communication ID meets the preset condition within the first preset time period;

a confirmation frame sending module 34, configured to send a host confirmation frame to the DSP host; wherein, the DSPs of at least two devices comprise a DSP host; after receiving the host confirmation frame, the DSP host replies a successful confirmation frame;

and the host judgment module 35 is configured to determine that the host is an ARM host when receiving a successful acknowledgement frame returned by the DSP host.

In one possible implementation manner, in the standby host determination module 33, the preset conditions include: the received communication IDs are all smaller than the own communication ID, or the received communication IDs are all larger than the own communication ID.

In a possible implementation manner, the standby host determination module 33 may further be configured to:

In a possible implementation manner, the obtaining module 31 is specifically configured to:

In one possible implementation, the master-slave competition device 30 of the multi-machine system may further include a parameter synchronization module.

A parameter synchronization module to:

after the ARM master machine is determined, setting the desynchronizing flag bit of each ARM slave machine to inform each ARM slave machine to carry out parameter synchronization, so that each ARM slave machine and the ARM master machine keep parameter synchronization; after keeping parameter synchronization with the ARM host, each ARM slave machine sends a synchronization flag bit clearing instruction to the ARM host;

In a possible implementation manner, the master-slave competition device 30 of the multi-machine system may further include an offline synchronization module.

An offline synchronization module to: when the offline ARM slave machine is detected to exist, setting an out-of-synchronization flag bit of the offline ARM slave machine so as to synchronize parameters when the offline ARM slave machine is recovered to be online; and when the ARM host does not receive the heartbeat packet of the ARM slave machine within the third preset time period, judging that the ARM slave machine is offline.

In a possible implementation mode, the ARM and the DSP are in communication connection through a first CAN bus; and all the DSPs are also in communication connection through a second CAN bus.

Fig. 5 is a schematic diagram of an ARM according to an embodiment of the present invention. As shown in fig. 5, the ARM4 of this embodiment includes: a processor 40 and a memory 41. The memory 41 is configured to store a computer program 42, and the processor 40 is configured to call and run the computer program 42 stored in the memory 41, and execute the steps in the master-slave contention method embodiments of the multi-computer system, such as S101 to S105 shown in fig. 2. Alternatively, the processor 40 is configured to call and run the computer program 42 stored in the memory 41, so as to implement the functions of the modules/units in the above-mentioned device embodiments, for example, the functions of the modules/units 31 to 35 shown in fig. 4.

Illustratively, the computer program 42 may be partitioned into one or more modules/units that are stored in the memory 41 and executed by the processor 40 to implement the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 42 in the ARM 4. For example, the computer program 42 may be divided into the modules/units 31 to 35 shown in fig. 4.

The ARM4 may include, but is not limited to, a processor 40, a memory 41. Those skilled in the art will appreciate that figure 5 is merely an example of ARM4 and does not constitute a limitation of ARM4 and may include more or fewer components than shown, or some components in combination, or different components, e.g., the ARM may also include input output devices, network access devices, buses, etc.

The Processor 40 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 41 may be an internal storage unit of the ARM4, such as a hard disk or a memory of the ARM 4. The memory 41 may also be an external storage device of the ARM4, such as a plug-in hard disk equipped on the ARM4, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 41 may also include both an internal storage unit and an external storage device of the ARM 4. The memory 41 is used to store the computer program and other programs and data required by the ARM. The memory 41 may also be used to temporarily store data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the above embodiments, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described or recited in any embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided herein, it should be understood that the disclosed apparatus/ARM and method may be implemented in other ways. For example, the above-described apparatus/ARM embodiments are merely illustrative, and for example, the division of the modules or units is only one type of logical function division, and other division manners may exist in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium and used by a processor to implement the steps of the master-slave contention method embodiments of the above-mentioned multi-computer system. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, read-Only Memory (ROM), random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media which may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.

The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A master-slave competition method of a multi-machine system is characterized in that the multi-machine system comprises at least two devices, each device comprises an ARM and a DSP, the ARM is in communication connection with the DSP, and the ARM is in communication connection with the DSP; the master-slave competition method of the multi-machine system is applied to the ARM and comprises the following steps:

receiving heartbeat frames sent by other ARM; the heartbeat frames sent by the other ARM comprise communication IDs of the other corresponding ARM;

sending a host confirmation frame to the DSP host; the DSP of the at least two devices comprises a DSP host; after receiving the host confirmation frame, the DSP host replies a successful confirmation frame;

and when a successful confirmation frame replied by the DSP host is received, determining the DSP host as an ARM host.

2. The master-slave competition method for the multi-computer system as claimed in claim 1, wherein the preset conditions include: the received communication IDs are all smaller than the own communication ID, or the received communication IDs are all larger than the own communication ID.

3. The master-slave competition method for multi-computer systems as claimed in claim 1, wherein after receiving the heartbeat frames sent by other ARM, the master-slave competition method for multi-computer systems further comprises:

and if the communication ID which does not meet the preset condition is received within the first preset time, determining that the communication ID is an ARM slave machine.

4. The master-slave contention method of a multi-computer system according to claim 1, wherein the obtaining of the own communication ID and the sending of the heartbeat frame including the own communication ID comprises:

5. The master-slave competition method for multi-computer systems of claim 1, wherein after determining itself to be an ARM master, the master-slave competition method for multi-computer systems further comprises:

6. The master-slave competition method for multi-computer systems as claimed in claim 1, wherein after determining that the self is an ARM master, the master-slave competition method for multi-computer systems further comprises:

when an offline ARM slave computer is detected to exist, setting an out-of-synchronization flag bit of the offline ARM slave computer so as to synchronize parameters when the offline ARM slave computer is recovered to be online; and when the ARM host does not receive the heartbeat packet of the ARM slave machine within the third preset time length, judging that the ARM slave machine is offline.

7. The master-slave competition method for the multi-machine system according to any one of claims 1 to 6, wherein the ARM and the DSP are connected through first CAN bus communication;

and all the DSPs are also in communication connection through a second CAN bus.

8. A master-slave competition device of a multi-machine system is characterized in that the multi-machine system comprises at least two devices, each device comprises an ARM and a DSP, the ARM is in communication connection with the DSP, and the ARM is in communication connection with the DSP; the master-slave competition device of the multi-machine system is applied to the ARM and comprises the following steps:

the receiving module is used for receiving heartbeat frames sent by other ARM; the heartbeat frames sent by the other ARM comprise communication IDs of the other corresponding ARM;

the system comprises a confirmation frame sending module, a DSP host and a host, wherein the confirmation frame sending module is used for sending a host confirmation frame to the DSP host; the DSP of the at least two devices comprises a DSP host; after receiving the host confirmation frame, the DSP host replies a successful confirmation frame;

and the host judgment module is used for determining the host as an ARM host when receiving the successful confirmation frame replied by the DSP host.

9. An ARM comprising a processor and a memory, the memory storing a computer program, the processor calling and running the computer program stored in the memory to perform the master-slave contention method of the multi-machine system according to any one of claims 1 to 7.

10. A computer-readable storage medium, in which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of a master-slave contention method for a multi-machine system according to any one of the preceding claims 1 to 7.