CN115987308B - Spurious signal suppression method and spurious signal suppression circuit - Google Patents
Spurious signal suppression method and spurious signal suppression circuit Download PDFInfo
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- CN115987308B CN115987308B CN202310119753.3A CN202310119753A CN115987308B CN 115987308 B CN115987308 B CN 115987308B CN 202310119753 A CN202310119753 A CN 202310119753A CN 115987308 B CN115987308 B CN 115987308B
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Abstract
The invention provides a spurious signal suppression method and a spurious signal suppression circuit, wherein the spurious signal suppression method is applied to a transmitter and comprises the following steps: detecting whether a signal sent by a power amplifier in the transmitter contains a first spurious signal; acquiring a first conversion signal, wherein the frequency of the first conversion signal is equal to the difference value between the ideal signal and the frequency of the first spurious signal; and acquiring a first digital signal corresponding to the first conversion signal, judging whether the first digital signal meets a first preset condition, and if not, performing inhibition processing on the first spurious signal until the first digital signal corresponding to the first spurious signal meets the first preset condition. The invention can obtain visual and convenient analysis results without being influenced by process deviation and environmental temperature.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and a circuit for suppressing spurious signals.
Background
Generally, as shown in fig. 1, the transmitter includes a digital-to-analog converter (Digital to analog converter, DAC) 101, a Low-pass filter (LPF) 102, a Mixer (MX) 103, a Power Amplifier (PA) 104, a BALUN (BALUN) 105, a data processing module 106, and a phase-locked loop (phase locked loop, PLL) 107, a power management unit (Power management unit, PMU) 108, a temperature sensor (temperature sensor, tsensor) 109. Assuming an intermediate frequency (intermediate frequency, IF) of fbb and a Local Oscillator (lo) frequency of flo, the transmit frequency obtained by up-conversion should be the sum of the intermediate frequency and the Local Oscillator frequency, i.e. flo+ fbb, in a transmitter, especially nonlinear distortion of an amplifier, intermodulation distortion will occur, even-order intermodulation distortion will generally be filtered away from the intermediate frequency, and a portion of odd-order intermodulation distortion will not be filtered out in the immediate vicinity of the intermediate frequency, wherein especially the third-order intermodulation distortion has the largest amplitude and the largest influence, resulting in signal band expansion, causing adjacent channel interference, and destroying the linear relationship between the output voltage and the input voltage of each frequency component in the band. Of course, the spurious signals are generated not only due to nonlinear distortion of the amplifier, but also due to other reasons. The more representative spurious signals obtained for these reasons are those having frequencies of flo-3fbb, flo-fbb and flo, which are designated as CIM3, image and carrier, respectively, and those having frequencies of flo+ fbb, respectively, for ease of description, and are distributed as shown in fig. 2.
The mathematical model of the mixer is shown in fig. 3. CIM3 is produced for several reasons:
1) The 3 rd order harmonics carried by the intermediate frequency. Referring to fig. 1 and 3, assume that the I-way signal is
Q is
Lo is->
And->
The signal obtained after the mixer is
. Due to the non-linearity of the baseband frequency, the I-path will generate +.>
I.e. +.>
The method comprises the steps of carrying out a first treatment on the surface of the Similarly, Q will generate +.>
I.e.
. I.e. after passing through the mixer, a size of
I.e. CIM3.
2) 3 rd order harmonics carried by the local oscillator frequency. As shown in FIG. 5, in general, the lo signal on the mixer is a square wave, according to the Fourier transform, except
Besides, there are->
A component. After the processing of the mixer, the following steps are generated
Although this component is not at the frequency point of CIM3, it is considered that the PA of the subsequent stage tends to be nonlinear, +.>
Intermodulation with the signal, will result in
I.e. CIM3.
In order to reduce spurious signals like CIM3, in the transmitter design, the current solution is that it is possible to produce by reducing the non-linearity of the baseband frequency, e.g. by an amount of 3 fbb; it is also possible to reduce the 3 rd order harmonics of the mixer, such as 3flo; the 3flo-fbb component after the mixer can also be reduced; of course, the purpose of spurious signal reduction can also be achieved by increasing the linearity of the PA.
Especially in LTE, CIM3 is often required to be less than-60 dBc. Therefore, due to SEM requirements of the transmission protocol, especially in LTE, high demands are placed on the high linearity of the device in order to reduce the spurious signals. Current solutions for reducing spurious signals are subject to process variations and ambient temperature, which makes their achievement less than ideal.
Therefore, the invention provides a spurious signal suppression method and a spurious signal suppression circuit, so as to reduce the influence of process deviation and ambient temperature on spurious signal suppression and realize the purpose of spurious signal reduction.
Disclosure of Invention
The invention provides a spurious signal suppression method and a spurious signal suppression circuit, which are used for solving the technical problem that the suppression effect is not ideal because the scheme for reducing spurious signals is influenced by process deviation and environmental temperature in the prior art.
In a first aspect, the present invention provides a method for suppressing spurious signals, applied to a transmitter, including: detecting whether a signal sent by a power amplifier in the transmitter contains a first spurious signal, wherein the first spurious signal is a signal with the frequency of flo-3fbb when the frequency of an ideal signal is flo+ fbb; when the frequency of the ideal signal is flo-fbb, the first spurious signal is a signal with the frequency of flo+3 fbb; the flo is the size of local oscillation frequency, and the fbb is the size of intermediate frequency; the ideal signal is a theoretical value of the transmitting frequency of the power amplifier obtained by an up-conversion mode or a down-conversion mode; acquiring a first conversion signal, wherein the frequency of the first conversion signal is equal to the difference value between the ideal signal and the frequency of the first spurious signal; and acquiring a first digital signal corresponding to the first conversion signal, judging whether the first digital signal meets a first preset condition, and if not, performing inhibition processing on the first spurious signal until the first digital signal corresponding to the first spurious signal meets the first preset condition.
The beneficial effects are that: because the local oscillation frequency is relatively large, the spurious signals are inconvenient to directly analyze, the spurious signals with high frequency are converted into low frequency by acquiring the conversion signals corresponding to the spurious signals, the result convenient to analyze can be obtained, whether the spurious signals meet the requirement can be intuitively judged by converting the spurious signals into the digital signals, and the spurious signals are adjusted according to the result of the analog-to-digital converter. Because the frequency of the converted signal is smaller, the invention can obtain visual and convenient analysis results without being influenced by process deviation and environmental temperature.
Optionally, the method for suppressing the spurious signals further includes: detecting whether a signal sent by the power amplifier contains a second spurious signal, wherein when the frequency of an ideal signal is flo+ fbb, the second spurious signal is a signal with the frequency of flo-fbb; when the frequency of the ideal signal is flo-fbb, the second spurious signal is a signal with the frequency of flo+ fbb; acquiring a second conversion signal, wherein the frequency of the second conversion signal is equal to the difference value between the ideal signal and the frequency of the second spurious signal; and acquiring a second digital signal corresponding to the second conversion signal, judging whether the second digital signal meets a second preset condition, and if not, performing inhibition processing on the second spurious signal until the second digital signal corresponding to the second spurious signal meets the second preset condition.
Optionally, the method for suppressing the spurious signals further includes: detecting whether a signal sent by the power amplifier contains a third spurious signal or not, wherein the third spurious signal is a signal with the frequency of flo; acquiring a third conversion signal, wherein the frequency of the third conversion signal is equal to the difference value between the ideal signal and the frequency of the third spurious signal; and acquiring a third digital signal corresponding to the third conversion signal, judging whether the third digital signal meets a third preset condition, and if not, performing inhibition processing on the third spurious signal until the third digital signal corresponding to the third spurious signal meets the third preset condition.
In a second aspect, the present invention provides a spurious signal suppression circuit for performing the spurious signal suppression method according to any one of the first aspects, comprising: the device comprises a first suppression unit, a square circuit, an analog-to-digital converter and a judgment module; the squaring circuit is electrically connected with the power amplifier to detect whether the output of the power amplifier is doped with spurious signals, wherein the spurious signals comprise at least one of a first spurious signal, a second spurious signal and a third spurious signal; when the frequency of the ideal signal is flo+ fbb, the first spurious signal is a signal with the frequency of flo-3fbb, and the second spurious signal is a signal with the frequency of flo-fbb; when the frequency of the ideal signal is flo-fbb, the first spurious signal is a signal with the frequency of flo+3fbb, and the second spurious signal is a signal with the frequency of flo+ fbb; the third spurious signal is a signal with the frequency size of flo; the flo is the size of local oscillation frequency, and the fbb is the size of intermediate frequency; the ideal signal is a theoretical value of the transmitting frequency of the power amplifier obtained by an up-conversion mode or a down-conversion mode; and the squaring circuit is further configured to generate a converted signal corresponding to the detected spurious signal, the converted signal having a frequency equal to a difference in frequency between the ideal signal and the detected spurious signal; the analog-to-digital converter is electrically connected with the square circuit to acquire a conversion signal generated by the square circuit and output a digital signal corresponding to the conversion signal generated by the square circuit; the judging module is electrically connected with the power amplifier through the first suppressing unit, and is used for judging whether the digital signal output by the analog-to-digital converter meets a preset condition or not, and if the digital signal does not meet the preset condition, the first suppressing unit is controlled to suppress spurious signals corresponding to the digital signal which does not meet the preset condition until the digital signal corresponding to the spurious signals meets the preset condition.
The beneficial effects are that: because the local oscillation frequency is relatively large, the spurious signals are inconvenient to directly analyze, the spurious signals with high frequency are converted into low frequency by acquiring the conversion signals corresponding to the spurious signals, the result convenient to analyze can be obtained, whether the spurious signals meet the requirement can be intuitively judged by converting the spurious signals into the digital signals, and the spurious signals are adjusted according to the result of the analog-to-digital converter. The suppression effect of the prior art can be changed along with the process deviation and the environmental temperature, and the suppression circuit for the stray signals can adjust the suppression effect to achieve the required suppression effect, so that even if the influence of the process deviation and the environmental temperature exists, the influence of the process deviation and the environmental temperature can be corrected and compensated back through the suppression circuit, and the suppression circuit can obtain visual and convenient analysis results without being influenced by the process deviation and the environmental temperature.
Optionally, the first suppressing unit includes: the first branch is provided with a first inductor and a first adjustable capacitor which are connected in parallel, and the second branch is provided with a second inductor and a second adjustable capacitor which are connected in parallel; the mixer is electrically connected with the first input end of the power amplifier through the first branch circuit, and the mixer is electrically connected with the second input end of the power amplifier through the second branch circuit. The beneficial effects are that: the values of the inductance and the capacitance change due to the influences of process deviation and temperature, so that the resonance frequency changes, and the inhibition effect is further influenced. The first suppression unit designed by the invention has a simple structure, and the resonance of the first suppression unit can meet the frequency requirement of the spurious signals by adjusting the capacitance of the first adjustable capacitor or the second adjustable capacitor so as to achieve the purpose of suppressing the corresponding spurious signals.
Optionally, the squaring circuit includes: the first P-type transistor, the second P-type transistor, the first N-type transistor, the second N-type transistor, the third N-type transistor, the first resistor and the second resistor; the source electrode of the first P-type transistor is connected with a power supply; the drain electrode of the first P-type transistor is connected with the first end of the first resistor, the drain electrode of the first N-type transistor and the drain electrode of the second N-type transistor; the grid electrode of the first P-type transistor is connected with the grid electrode of the second P-type transistor, the second end of the first resistor and the first end of the second resistor; the source electrode of the second P-type transistor is connected with a power supply; the drain electrode of the second P-type transistor is connected with the second end of the second resistor and the drain electrode of the third N-type transistor; the source electrode of the first N-type transistor is grounded; the grid electrode of the first N-type transistor is connected with the first output end of the power amplifier; the source electrode of the second N-type transistor is grounded; the grid electrode of the second N-type transistor is connected with the second output end of the power amplifier; the source electrode of the third N-type transistor is grounded; the grid electrode of the third N-type transistor is used for receiving bias voltage; the first end of the first resistor is also connected with the first input end of the analog-to-digital converter; the second end of the second resistor is also connected with the second input end of the analog-to-digital converter. The beneficial effects are that: the squaring circuit can convert the spurious signals into corresponding converted signals so as to facilitate analysis of subsequent processes.
Optionally, the spurious signal suppression circuit further comprises a linearity adjustment circuit; the linearity adjusting circuit is electrically connected with the power amplifier, and the linearity adjusting circuit adjusts the linearity of the power amplifier by adjusting the magnitude of the bias voltage input to the power amplifier.
Optionally, the linearity adjustment circuit includes: a first bias current source and a second bias current source, the first bias current source comprising: a first current source and an eighth N-type transistor; the second bias current source includes: the second current source, the ninth N-type transistor, the third capacitor and the fifth resistor; the drain electrode of the eighth N-type transistor is connected with the first current source and the grid electrode of the eighth N-type transistor; the source electrode of the eighth N-type transistor is grounded; a grid electrode of the eighth N-type transistor is connected with the second end of the third resistor and the second end of the fourth resistor; the drain electrode of the ninth N-type transistor is connected with the second current source and the grid electrode of the ninth N-type transistor; the source electrode of the ninth N-type transistor is connected with the first end of the fifth resistor, and the second end of the fifth resistor is grounded; a grid electrode of the ninth N-type transistor is connected with the first end of the third capacitor; the second end of the third capacitor is grounded.
Optionally, the spurious signal suppression circuit further includes a second suppression unit, where the power amplifier is electrically connected to the square circuit through the second suppression unit, and the second suppression unit is configured to perform suppression processing on the spurious signal carried by the output of the power amplifier; the second suppressing unit includes: the third branch is provided with a third inductor and a third adjustable capacitor which are connected in parallel, and the fourth branch is provided with a fourth inductor and a fourth adjustable capacitor which are connected in parallel.
Drawings
FIG. 1 is a schematic diagram of a prior art transmitter;
FIG. 2 is a diagram illustrating a spurious signal distribution;
FIG. 3 is a schematic diagram of a mathematical model of a mixer;
FIG. 4 is a schematic diagram of a mathematical model of yet another mixer;
FIG. 5 is a schematic diagram of a mathematical model of yet another mixer;
FIG. 6 is a schematic diagram of a method for suppressing spurious signals according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a spurious signal suppression circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a structural embodiment of a first suppressing unit according to the present invention;
FIG. 9 is a schematic diagram of a square circuit according to an embodiment of the present invention;
Fig. 10 is a schematic diagram of an embodiment of a power amplifier structure according to the present invention;
FIG. 11 is a schematic diagram of a structure of a linearity adjustment circuit according to an embodiment of the present invention;
fig. 12 is a schematic view of a terminal embodiment provided in the present invention;
FIG. 13 is a schematic diagram of an embodiment of a transmitter structure according to the present invention;
fig. 14 is a schematic diagram of an embodiment of a signal distribution of the conversion according to the present invention.
Description of the embodiments
The technical solutions in the embodiments of the present application are described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, the terminology used in the embodiments below is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary. It should also be understood that in the various embodiments herein below, "at least one", "one or more" means one or more than two (including two). The term "and/or" is used to describe an association relationship of associated objects, meaning that there may be three relationships; for example, a and/or B may represent: a alone, a and B together, and B alone, wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise. The term "coupled" includes both direct and indirect connections, unless stated otherwise. The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
In the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
The method aims to solve the technical problem that the inhibition effect is not ideal because the scheme for reducing the stray signals is influenced by process deviation and ambient temperature in the prior art. The invention provides a spurious signal suppression method and a spurious signal suppression circuit, which are applied to a transmitter.
The flow of the spurious signal suppression method is shown in fig. 6, and includes:
s601: detecting whether a signal sent by a power amplifier in the transmitter contains a first spurious signal;
in this step, when the frequency of the ideal signal is flo+ fbb, the first spurious signal is a signal with a frequency of flo-3 fbb; when the frequency of the ideal signal is flo-fbb, the first spurious signal is a signal with the frequency of flo+3 fbb; the flo is the size of local oscillation frequency, and the fbb is the size of intermediate frequency; the ideal signal is a theoretical value of the transmitting frequency of the power amplifier obtained by an up-conversion mode or a down-conversion mode;
s602: acquiring a first conversion signal, wherein the frequency of the first conversion signal is equal to the difference value between the ideal signal and the frequency of the first spurious signal;
s603: and acquiring a first digital signal corresponding to the first conversion signal, judging whether the first digital signal meets a first preset condition, and if not, performing inhibition processing on the first spurious signal until the first digital signal corresponding to the first spurious signal meets the first preset condition.
Because the local oscillation frequency is relatively large, the spurious signals are inconvenient to directly analyze, the spurious signals with high frequency are converted into low frequency by acquiring the conversion signals corresponding to the spurious signals, the result convenient to analyze can be obtained, whether the spurious signals meet the requirement can be intuitively judged by converting the spurious signals into the digital signals, and the spurious signals are adjusted according to the result of the analog-to-digital converter. Because the frequency of the converted signal is smaller, the invention can obtain visual and convenient analysis results without being influenced by process deviation and environmental temperature.
In some embodiments, the method for suppressing spurious signals further comprises: detecting whether a signal sent by the power amplifier contains a second spurious signal, wherein when the frequency of an ideal signal is flo+ fbb, the second spurious signal is a signal with the frequency of flo-fbb; when the frequency of the ideal signal is flo-fbb, the second spurious signal is a signal with the frequency of flo+ fbb; acquiring a second conversion signal, wherein the frequency of the second conversion signal is equal to the difference value between the ideal signal and the frequency of the second spurious signal; and acquiring a second digital signal corresponding to the second conversion signal, judging whether the second digital signal meets a second preset condition, and if not, performing inhibition processing on the second spurious signal until the second digital signal corresponding to the second spurious signal meets the second preset condition.
In some embodiments, the method for suppressing spurious signals further comprises: detecting whether a signal sent by the power amplifier contains a third spurious signal or not, wherein the third spurious signal is a signal with the frequency of flo; acquiring a third conversion signal, wherein the frequency of the third conversion signal is equal to the difference value between the ideal signal and the frequency of the third spurious signal; and acquiring a third digital signal corresponding to the third conversion signal, judging whether the third digital signal meets a third preset condition, and if not, performing inhibition processing on the third spurious signal until the third digital signal corresponding to the third spurious signal meets the third preset condition.
The first preset condition, the second preset condition and the third preset condition are that the corresponding spurious signals are smaller than preset thresholds, the preset thresholds in different preset conditions are different, the preset thresholds are specifically set according to actual conditions, and the application is not specifically limited.
To describe the spurious signal suppression method provided in the present application in more detail, the frequency of the ideal signal is flo+ fbb, which is illustrated as follows:
Example one:
detecting whether a signal sent by a power amplifier in the transmitter contains CIM3; if CIM3 is included, the square circuit obtains a first conversion signal with the frequency of 4fbb by performing difference on the CIM3 and the signal; and acquiring a first digital signal corresponding to the first conversion signal through an analog-to-digital converter, judging whether the first digital signal is smaller than a first preset threshold value, and if not, performing inhibition processing on the CIM3 until the first digital signal corresponding to the CIM3 is smaller than the first preset threshold value. The first preset threshold is specifically set according to actual conditions, and the application is not limited.
Example two: detecting whether a signal sent by a power amplifier in the transmitter contains CIM3 and image, if so, the squaring circuit respectively obtains a first conversion signal with the frequency of 4fbb and a second conversion signal with the frequency of 2fbb by differencing CIM3 and signal and differencing image and signal. Acquiring a first digital signal corresponding to the first conversion signal and a second digital signal corresponding to the second conversion signal through an analog-to-digital converter, judging whether the first digital signal is smaller than a first preset threshold value, if not, performing inhibition processing on the CIM3 until the first digital signal corresponding to the CIM3 is smaller than the first preset threshold value; and judging whether the second digital signal is smaller than a second preset threshold value, if not, performing inhibition processing on the image until the second digital signal corresponding to the image is smaller than the second preset threshold value. The first preset threshold and the second preset threshold are specifically set according to actual conditions, and the application is not limited.
Example three: detecting whether a signal sent by a power amplifier in the transmitter includes CIM3, image and carrier, if so, the squaring circuit respectively obtains a first conversion signal with a frequency of 4fbb, a second conversion signal with a frequency of 2fbb and a third conversion signal with a frequency of fbb by differencing CIM3 from signal, differencing image from signal and differencing carrier from signal. Acquiring a first digital signal corresponding to the first conversion signal, a second digital signal corresponding to the second conversion signal and a third digital signal corresponding to the third conversion signal through an analog-to-digital converter; judging whether the first digital signal is smaller than a first preset threshold value, if not, performing inhibition processing on the CIM3 until the first digital signal corresponding to the CIM3 is smaller than the first preset threshold value; judging whether the second digital signal is smaller than a second preset threshold value, if not, performing inhibition processing on the image until the second digital signal corresponding to the image is smaller than the second preset threshold value; and judging whether the third digital signal is smaller than a third preset threshold value, if not, performing inhibition processing on the carrier until the second digital signal corresponding to the carrier is smaller than the third preset threshold value. The first preset threshold, the second preset threshold and the third preset threshold are specifically set according to actual conditions, and the application is not limited.
The conversion process of the signal by the squaring circuit SQR and the correspondence of the generated converted signal are shown in fig. 14. CIM3 with the frequency of flo-3fbb is converted by a square circuit SQR to obtain a signal with the frequency of 4 fbb; after the image with the frequency of flo-fbb is converted by a square circuit SQR, a signal with the frequency of 2fbb is obtained; after the carrier with the frequency of flo is subjected to SQR conversion by a square circuit, a signal with the frequency of fbb is obtained; after the signal with the frequency of flo+ fbb is converted by the square circuit SQR, a signal with the frequency of DC is obtained.
The method comprises the following steps: when the ideal signal has a frequency of flo+ fbb, i.e
CIM3 has a frequency of flo-3fbb, i.e. +.>
Then after the square circuit, the method comprises the following steps:
wherein the high frequency part is filtered out by the characteristics of the circuit itself, leaving DC and +.>
Part of which is collected by an analog-to-digital converter, i.e.
. Wherein->
It is the converted signal 4fbb that we need. The conversion process of other signals is the same and will not be described again.
When the signal emitted by the mixer comprises: CIM3, image, carrier, signal, the squaring circuit cannot obtain the corresponding converted signal only by the above conversion process, but may also obtain the signal contained in the coordinate system on the right in fig. 14 by mixing other signals, specifically referring to the following table:
Tone1 and Tone2 represent the signals required for conversion in the squaring circuit, and it can be found from the above table that 3fbb can also be generated during conversion, and that converted signals are not necessarily limited by the spurious signal suppressing method, but may be other combinations, but because the intensities of the other combinations are weaker than those of the signals limited by the spurious signal suppressing method, the obtained converted signals can be considered to correspond to the respective spurious signals by the combinations of the signals limited by the spurious signal suppressing method.
When the frequency of the ideal signal is flo-fbb, the spurious signal suppression process is the same, and no description is given here.
Based on the method for suppressing the spurious signals according to any one of the foregoing embodiments, the present invention provides a spurious signal suppressing circuit, configured to perform the method for suppressing the spurious signals according to any one of the foregoing embodiments, as shown in fig. 7, where the spurious signal suppressing circuit, as shown in fig. 7, includes: a first suppressing unit 701, a square circuit 702, an analog-to-digital converter 703, and a judging module 704; the squaring circuit 702 is electrically connected to a power amplifier to detect whether an output of the power amplifier is doped with a spurious signal, the spurious signal including at least one of a first spurious signal, a second spurious signal, and a third spurious signal; when the frequency of the ideal signal is flo+ fbb, the first spurious signal is a signal with the frequency of flo-3fbb, and the second spurious signal is a signal with the frequency of flo-fbb; when the frequency of the ideal signal is flo-fbb, the first spurious signal is a signal with the frequency of flo+3fbb, and the second spurious signal is a signal with the frequency of flo+ fbb; the third spurious signal is a signal with the frequency size of flo; the flo is the size of local oscillation frequency, and the fbb is the size of intermediate frequency; the ideal signal is a theoretical value of the transmitting frequency of the power amplifier obtained by an up-conversion mode or a down-conversion mode; and the squaring circuit 702 is further configured to generate a converted signal corresponding to the detected spurious signal, the converted signal having a frequency equal to a difference in frequency between the ideal signal and the detected spurious signal; the analog-to-digital converter 703 is electrically connected to the square circuit 702 to obtain a converted signal generated by the square circuit 702 and output a digital signal corresponding to the converted signal generated by the square circuit 702; the judging module 704 is electrically connected to the power amplifier through the first suppressing unit 701, where the judging module 704 is configured to judge whether the digital signal output by the analog-to-digital converter 703 meets a preset condition, and if the digital signal does not meet the preset condition, control the first suppressing unit 701 to suppress a spurious signal corresponding to a digital signal that does not meet the preset condition until the digital signal corresponding to the spurious signal meets the preset condition.
All relevant contents of each step related to the above method embodiment may be cited to the functional description of the corresponding unit module, which is not described herein.
Because the intensity of the local oscillation frequency is relatively large, the spurious signals are inconvenient to directly analyze, the local oscillation frequency contained in the spurious signals is counteracted by acquiring the conversion signals corresponding to the spurious signals, a result convenient to analyze can be obtained, whether the spurious signals meet the requirements can be intuitively judged by converting the local oscillation frequency into the digital signals, and the magnitude of the spurious signals is adjusted according to the result of the analog-to-digital converter. The suppression effect of the prior art can be changed along with the process deviation and the environmental temperature, and the suppression circuit for the stray signals can adjust the suppression effect to achieve the required suppression effect, so that even if the influence of the process deviation and the environmental temperature exists, the influence of the process deviation and the environmental temperature can be corrected and compensated back through the suppression circuit, and the suppression circuit can obtain visual and convenient analysis results without being influenced by the process deviation and the environmental temperature.
In some embodiments, as shown in fig. 8, the first suppressing unit includes: the first branch circuit and the second branch circuit are provided with a first inductor L1 and a first adjustable capacitor C1 which are connected in parallel, and the second branch circuit is provided with a second inductor L2 and a second adjustable capacitor C2 which are connected in parallel; the mixer is electrically connected with the first input end of the power amplifier through the first branch circuit, and the mixer is electrically connected with the second input end of the power amplifier through the second branch circuit. The beneficial effects are that: the values of the inductance and the capacitance change due to the influence of process deviation and temperature, so that the resonance frequency changes, and the inhibition effect is further influenced. The first suppression unit designed by the invention has a simple structure, and the resonance of the first suppression unit can reach the frequency requirement of the spurious signals by adjusting the capacitance of the first adjustable capacitor or the second adjustable capacitor so as to achieve the purpose of suppressing the corresponding spurious signals.
In some embodiments, as shown in fig. 9, the squaring circuit includes: the first P-type transistor P1, the second P-type transistor P2, the first N-type transistor N1, the second N-type transistor N2, the third N-type transistor N3, the first resistor R1 and the second resistor R2; the source electrode of the first P-type transistor P1 is connected with a power supply; the drain electrode of the first P-type transistor P1 is connected to the first end of the first resistor R1, the drain electrode of the first N-type transistor N1, and the drain electrode of the second N-type transistor N2; the gate of the first P-type transistor P1 is connected to the gate of the second P-type transistor P2, the second end of the first resistor R1, and the first end of the second resistor R2; the source electrode of the second P-type transistor P2 is connected with a power supply; the drain electrode of the second P-type transistor P2 is connected to the second end of the second resistor R2 and the drain electrode of the third N-type transistor N3; the source electrode of the first N-type transistor N1 is grounded; the grid electrode of the first N-type transistor N1 is connected with the first output end of the power amplifier so as to acquire a first output signal Vip of the power amplifier; the source electrode of the second N-type transistor N2 is grounded; and the grid electrode of the second N-type transistor N2 is connected with the second output end of the power amplifier so as to acquire a second output signal Vin of the power amplifier. The squaring circuit is used for generating a conversion signal corresponding to the spurious signal according to the first output signal Vip and the second output signal Vin. The source electrode of the third N-type transistor N3 is grounded; the gate of the third N-type transistor N3 is configured to receive a bias voltage Vb; the first end of the first resistor R1 is also connected with the first input end of the analog-to-digital converter so as to output a first signal Voutp to the analog-to-digital converter; the second end of the second resistor R2 is further connected to the second input end of the analog-to-digital converter, so as to output a second signal Voutn to the analog-to-digital converter. The analog-to-digital converter is used for generating a digital signal corresponding to the conversion signal according to the first signal Voutp and the second signal Voutn. The beneficial effects are that: the squaring circuit can convert the spurious signals into corresponding converted signals so as to facilitate analysis of subsequent processes.
In some embodiments, the spurious signal suppression circuit further comprises a linearity adjustment circuit; the linearity adjusting circuit is electrically connected with the power amplifier, and the linearity adjusting circuit adjusts the linearity of the power amplifier by adjusting the magnitude of the bias voltage input to the power amplifier.
As shown in fig. 10, the power amplifier includes: a fourth N-type transistor N4, a fifth N-type transistor N5, a sixth N-type transistor N6, a seventh N-type transistor N7, a first capacitor C3, a second capacitor C4, a third resistor R3 and a fourth resistor R4; the drain electrode of the fourth N-type transistor N4 and the drain electrode of the sixth N-type transistor N6 are connected with the power amplifier; the gate of the fourth N-type transistor N4 and the gate of the sixth N-type transistor N6 are connected to the second bias current source S2; the source electrode of the fourth N-type transistor N4 is connected with the drain electrode of the fifth N-type transistor N5; a gate of the fifth N-type transistor N5 is connected to the first end of the first capacitor C3 and the first end of the third resistor R3, and a second end of the third resistor R3 is connected to the first bias current source; the source electrode of the fifth N-type transistor N5 is grounded; the source electrode of the sixth N-type transistor N6 is connected with the drain electrode of the seventh N-type transistor N7; a gate of the seventh N-type transistor N7 is connected to the first end of the second capacitor C4 and the first end of the fourth resistor R4, and a second end of the fourth resistor R4 is connected to the first bias current source; the source electrode of the seventh N-type transistor N7 is grounded.
In some embodiments, as shown in fig. 11, the first bias current source includes: a first current source S1 and an eighth N-type transistor N8; the second bias current source includes: a second current source S2, a ninth N-type transistor N9, a third capacitor C5, and a fifth resistor R5; the drain electrode of the eighth N-type transistor N8 is connected with the first current source S1 and the grid electrode of the eighth N-type transistor N8; the source electrode of the eighth N-type transistor N8 is grounded; a gate of the eighth N-type transistor N8 is connected to the second end of the third resistor R3 and the second end of the fourth resistor R4; the drain electrode of the ninth N-type transistor N9 is connected to the second current source S2 and the gate electrode of the ninth N-type transistor N9; the source electrode of the ninth N-type transistor N9 is connected with the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is grounded; a gate of the ninth N-type transistor N9 is connected to the first end of the third capacitor C5, the gate of the fourth N-type transistor N4, and the gate of the sixth N-type transistor N6; the second end of the third capacitor C5 is grounded.
In some embodiments, the spurious signal suppression circuit further includes a second suppression unit, where the power amplifier is electrically connected to the square circuit through the second suppression unit, and the second suppression unit is configured to perform suppression processing on the spurious signal carried by the output of the power amplifier; the second suppressing unit includes: the third branch is provided with a third inductor and a third adjustable capacitor which are connected in parallel, and the fourth branch is provided with a fourth inductor and a fourth adjustable capacitor which are connected in parallel. The first output end of the power amplifier is electrically connected with the grid electrode of the first N-type transistor in the square circuit through the third branch circuit, and the second output end of the power amplifier is electrically connected with the grid electrode of the third N-type transistor in the square circuit through the fourth branch circuit.
In some embodiments, the embodiments of the present application disclose a terminal, which may refer to the judging module in the above embodiments, as shown in fig. 12, the terminal may include: one or more processors 1201; a memory 1202; a display 1203; one or more applications (not shown); and one or more computer programs 1204, the devices described above may be connected by one or more communication buses 1205. Wherein the one or more computer programs 1204 are stored in the memory 1202 and configured to be executed by the one or more processors 1201, where the one or more computer programs 1204 include instructions that can be used to perform the related steps of determining whether the digital signal output by the analog-to-digital converter meets a preset condition as described above, and if the preset condition is not met, controlling the first suppressing unit to perform a suppressing process on a spurious signal corresponding to a digital signal that does not meet the preset condition until the digital signal corresponding to the spurious signal meets the preset condition.
From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.
The functional units in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic or optical disk, and the like.
All relevant contents of each step related to the above method embodiment may be cited to the functional description of the corresponding unit module, which is not described herein.
In order to highlight the invention, based on the spurious signal suppression circuit provided by the foregoing embodiment, the present application further provides a transmitter, which further includes the spurious signal suppression circuit based on the prior art, as shown in fig. 13, and the transmitter includes: a digital-to-analog converter (Digital to analog converter, DAC) 1301, a Low-pass filter (LPF) 1302, a Mixer (MX) 1303, a Power Amplifier (PA) 1304, a BALUN (BALUN) 1305, a data processing module 1306, and a phase-locked loop (phase locked loop, PLL) 1307, a power management unit (Power management unit, PMU) 1308, a temperature sensor (temperature sensor, tsensor) 1309 associated therewith; and a second suppressing unit 1312, a linearity adjusting circuit 1311, a first suppressing unit 1310, a squaring circuit 1313, an analog-to-digital converter 1314, and a judging module 1315. The specific structures and functions of the second suppressing unit 1312, the linearity adjusting circuit 1311, the first suppressing unit 1310, the squaring circuit 1313, the analog-to-digital converter 1314 and the determining module 1315 are described in the above embodiments, and are not described herein. The second suppression unit 1312 is not a necessary structure and may be absent in some embodiments.
The foregoing is merely a specific implementation of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered by the protection scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. A method of spurious signal suppression, for use in a transmitter, comprising:
detecting whether a signal sent by a power amplifier in the transmitter contains a first spurious signal, wherein the first spurious signal is a signal with the frequency of flo-3fbb when the frequency of an ideal signal is flo+ fbb; when the frequency of the ideal signal is flo-fbb, the first spurious signal is a signal with the frequency of flo+3 fbb; the flo is the size of local oscillation frequency, and the fbb is the size of intermediate frequency; the ideal signal is a theoretical value of the transmitting frequency of the power amplifier obtained by an up-conversion mode or a down-conversion mode;
acquiring a first conversion signal, wherein the frequency of the first conversion signal is equal to the difference value between the ideal signal and the frequency of the first spurious signal;
And acquiring a first digital signal corresponding to the first conversion signal, judging whether the first digital signal meets a first preset condition, and if not, performing inhibition processing on the first spurious signal until the first digital signal corresponding to the first spurious signal meets the first preset condition.
2. The method of spurious signal suppression according to claim 1, further comprising:
detecting whether a signal sent by the power amplifier contains a second spurious signal, wherein when the frequency of an ideal signal is flo+ fbb, the second spurious signal is a signal with the frequency of flo-fbb; when the frequency of the ideal signal is flo-fbb, the second spurious signal is a signal with the frequency of flo+ fbb;
acquiring a second conversion signal, wherein the frequency of the second conversion signal is equal to the difference value between the ideal signal and the frequency of the second spurious signal;
and acquiring a second digital signal corresponding to the second conversion signal, judging whether the second digital signal meets a second preset condition, and if not, performing inhibition processing on the second spurious signal until the second digital signal corresponding to the second spurious signal meets the second preset condition.
3. The method of spurious signal suppression according to claim 2, further comprising:
detecting whether a signal sent by the power amplifier contains a third spurious signal or not, wherein the third spurious signal is a signal with the frequency of flo;
acquiring a third conversion signal, wherein the frequency of the third conversion signal is equal to the difference value between the ideal signal and the frequency of the third spurious signal;
and acquiring a third digital signal corresponding to the third conversion signal, judging whether the third digital signal meets a third preset condition, and if not, performing inhibition processing on the third spurious signal until the third digital signal corresponding to the third spurious signal meets the third preset condition.
4. A spurious signal suppression circuit for performing the spurious signal suppression method according to any one of claims 1 to 3, comprising: the device comprises a first suppression unit, a square circuit, an analog-to-digital converter and a judgment module;
the squaring circuit is electrically connected with the power amplifier to detect whether the output of the power amplifier is doped with spurious signals, wherein the spurious signals comprise at least one of a first spurious signal, a second spurious signal and a third spurious signal; when the frequency of the ideal signal is flo+ fbb, the first spurious signal is a signal with the frequency of flo-3fbb, and the second spurious signal is a signal with the frequency of flo-fbb; when the frequency of the ideal signal is flo-fbb, the first spurious signal is a signal with the frequency of flo+3fbb, and the second spurious signal is a signal with the frequency of flo+ fbb; the third spurious signal is a signal with the frequency size of flo; the flo is the size of local oscillation frequency, and the fbb is the size of intermediate frequency; the ideal signal is a theoretical value of the transmitting frequency of the power amplifier obtained by an up-conversion mode or a down-conversion mode;
And the squaring circuit is further configured to generate a converted signal corresponding to the detected spurious signal, the converted signal having a frequency equal to a difference in frequency between the ideal signal and the detected spurious signal;
the analog-to-digital converter is electrically connected with the square circuit to acquire a conversion signal generated by the square circuit and output a digital signal corresponding to the conversion signal generated by the square circuit;
the judging module is electrically connected with the power amplifier through the first suppressing unit, and is used for judging whether the digital signal output by the analog-to-digital converter meets a preset condition or not, and if the digital signal does not meet the preset condition, the first suppressing unit is controlled to suppress spurious signals corresponding to the digital signal which does not meet the preset condition until the digital signal corresponding to the spurious signals meets the preset condition.
5. The spurious signal suppression circuit of claim 4, wherein the first suppression unit comprises: the first branch is provided with a first inductor and a first adjustable capacitor which are connected in parallel, and the second branch is provided with a second inductor and a second adjustable capacitor which are connected in parallel; the mixer is electrically connected with the first input end of the power amplifier through the first branch circuit, and the mixer is electrically connected with the second input end of the power amplifier through the second branch circuit.
6. The spurious signal suppression circuit of claim 5, wherein the squaring circuit comprises: the first P-type transistor, the second P-type transistor, the first N-type transistor, the second N-type transistor, the third N-type transistor, the first resistor and the second resistor;
the source electrode of the first P-type transistor is connected with a power supply; the drain electrode of the first P-type transistor is connected with the first end of the first resistor, the drain electrode of the first N-type transistor and the drain electrode of the second N-type transistor; the grid electrode of the first P-type transistor is connected with the grid electrode of the second P-type transistor, the second end of the first resistor and the first end of the second resistor;
the source electrode of the second P-type transistor is connected with a power supply; the drain electrode of the second P-type transistor is connected with the second end of the second resistor and the drain electrode of the third N-type transistor;
the source electrode of the first N-type transistor is grounded; the grid electrode of the first N-type transistor is connected with the first output end of the power amplifier;
the source electrode of the second N-type transistor is grounded; the grid electrode of the second N-type transistor is connected with the second output end of the power amplifier;
the source electrode of the third N-type transistor is grounded; the grid electrode of the third N-type transistor is used for receiving bias voltage;
The first end of the first resistor is also connected with the first input end of the analog-to-digital converter; the second end of the second resistor is also connected with the second input end of the analog-to-digital converter.
7. The spurious signal suppression circuit of claim 4, further comprising a linearity adjustment circuit; the linearity adjusting circuit is electrically connected with the power amplifier, and the linearity adjusting circuit adjusts the linearity of the power amplifier by adjusting the magnitude of the bias voltage input to the power amplifier.
8. The spurious signal suppression circuit of claim 7, wherein the linearity adjustment circuit comprises: a first bias current source and a second bias current source, the first bias current source comprising: a first current source and an eighth N-type transistor; the second bias current source includes: the second current source, the ninth N-type transistor, the third capacitor and the fifth resistor;
the drain electrode of the eighth N-type transistor is connected with the first current source and the grid electrode of the eighth N-type transistor; the source electrode of the eighth N-type transistor is grounded; the grid electrode of the eighth N-type transistor is connected with the second end of the third resistor and the second end of the fourth resistor;
The drain electrode of the ninth N-type transistor is connected with the second current source and the grid electrode of the ninth N-type transistor; the source electrode of the ninth N-type transistor is connected with the first end of the fifth resistor, and the second end of the fifth resistor is grounded; a grid electrode of the ninth N-type transistor is connected with the first end of the third capacitor; the second end of the third capacitor is grounded.
9. The spurious signal suppression circuit according to claim 4, further comprising a second suppression unit, the power amplifier being electrically connected to the squaring circuit through the second suppression unit, the second suppression unit being configured to suppress the spurious signal carried by the output of the power amplifier; the second suppressing unit includes: the third branch is provided with a third inductor and a third adjustable capacitor which are connected in parallel, and the fourth branch is provided with a fourth inductor and a fourth adjustable capacitor which are connected in parallel.
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