CN115983190B - Integrated circuit layout wiring method, device and storage medium for meeting multiple mask constraints - Google Patents

Abstract

The invention discloses an integrated circuit layout wiring method meeting multiple mask constraints, which comprises the following steps: initializing wiring resources of an integrated circuit layout; (2) Constructing a virtual grid point model of wiring grid nodes suitable for a multiple mask distribution scene, wherein attribute parameters of each virtual sub-grid point in the virtual grid point model comprise coordinates, colors and mask types; (3) Wiring is conducted according to a wiring cost minimum principle based on the constructed virtual grid point model, wherein the wiring cost minimum principle refers to selecting virtual sub grid point connection wiring with the same characteristic mask for adjacent wiring grid nodes; and (4) outputting the wiring and mask distribution result of the integrated circuit layout.

Description

Integrated circuit layout wiring method, device and storage medium for meeting multiple mask constraints

Technical Field

The invention relates to the technical field of wiring design of very large scale integrated circuits (VLSI), in particular to an integrated circuit layout wiring method meeting multiple mask constraints.

Background

Photolithography is one of the key processes in the fabrication of integrated circuits. With the continuous reduction of the feature size of the integrated circuit, the density of the layout pattern is continuously increased, but the wavelength of a light source used for photoetching is not obviously reduced, and the exposure resolution is not obviously improved, so that the number of pattern conflicts (conflict) is continuously increased on the same mask. The pattern conflict is defined as two layout patterns separated by less than a certain value, which is called the conflict distance. Multiple exposure lithography (MultiplePatterningLithography) is one of the effective ways to resolve pattern conflicts.

Semiconductor multiple patterning (Semiconductor multi-pattern manufacturing method) refers to a technique in the semiconductor manufacturing process that increases the feature density on a chip by assigning objects on a single layer to different manufacturing steps. The multiple exposure photoetching process is to decompose the layout pattern onto several different masks and form the complete silicon chip pattern finally through several exposure and etching steps. How to distribute design layout patterns to a plurality of different masks so as to minimize pattern conflicts on the same mask is the key of a multiple exposure layout distribution method.

In the 20/22 nm technology node, a double exposure lithography process Double Patterning Lithography (DPL) has been widely used, which can improve the manufacturing resolution of immersion lithography, and the idea of DPT is to divide a single layout into two masks to increase the pitch size and depth of focus, optimizing manufacturability. In a double exposure lithography process, the patterns dispensed onto two reticles are typically fabricated using an exposure-Etch-exposure-Etch process (LithoEtch-Litho-Etch, LELE) or an exposure-Freeze-exposure-Etch process (Litho-Freeze-Litho-Etch, LFLE). However, at the 14/16 nanometer process technology node, as the feature size of the integrated circuit is further reduced, the layout patterns are more dense, the technical limit of DPL is reached, the original layout patterns are difficult to decompose on two masks without pattern conflict, and a triple exposure lithography process TRIPLE PATTERNING Lithography (TPL) is introduced. The triple exposure lithography process TRIPLE PATTERNING Lithography (TPL) process can eliminate conflicts that cannot be resolved by DPL and reduce the number of stitching lines, further increase the focal length size, and increase the focal depth.

There are generally two ways to implement layout design of multiple mask scenarios, one is to consider mask allocation after detailed routing, and the other is to consider mask allocation simultaneously during detailed routing. The prior research work proposes a lattice model suitable for a multiple mask scene, and wiring is carried out through the lattice model, but the problem that the model expression is complex and difficult to realize when the model is applied to a wiring algorithm exists.

Disclosure of Invention

Technical problem to be solved by the invention

The present invention has been made in view of the above problems, and it is an object of the present invention to solve the problem of mask allocation in wiring an integrated circuit layout, and to minimize the occurrence of stitching, and to improve the wiring efficiency and manufacturability of the process. It is therefore an object of the present invention to provide a wiring method for an integrated circuit layout that satisfies multiple mask constraints.

In order to achieve the above object, the present invention provides an integrated circuit layout wiring method satisfying multiple mask constraints, comprising:

(1) Initializing wiring resources of an integrated circuit layout;

(2) Constructing a virtual grid point model of wiring grid nodes suitable for a multiple mask distribution scene, wherein attribute parameters of each virtual sub-grid point in the virtual grid point model comprise coordinates, colors and mask types;

(3) Wiring is conducted according to a wiring cost minimum principle based on the constructed virtual grid point model, wherein the wiring cost minimum principle refers to selecting virtual sub grid point connection wiring with the same characteristic mask for adjacent wiring grid nodes; and

(4) Outputting the layout of the integrated circuit and the distribution result of the mask,

Wherein, the step (3) specifically comprises: sequentially searching a plurality of grid nodes on the way of wiring according to a preset direction from a wiring source grid node; traversing the searched multiple virtual sub-grid points in the virtual grid point model corresponding to the wiring grid node; and comparing the wiring cost of the virtual sub-grid points one by one according to the principle of minimum wiring cost, and once the virtual sub-grid point with the minimum wiring cost corresponding to the searched wiring grid node is determined, terminating the traversing, and connecting and wiring the virtual sub-grid point with the minimum wiring cost.

Further, constructing a virtual lattice point model of a routing grid node suitable for a multiple mask distribution scenario includes: virtually expanding each wiring grid node into a plurality of virtual sub-grid points, wherein each virtual sub-grid point corresponds to one type of mask, and constructing the virtual grid point model on the basis.

Further, the virtual sub-grid points located in the mask conflict area are not available corresponding to the mask, and the virtual sub-grid points cannot pop up as alternatives during searching.

Further, for the searched wiring grid node, judging whether each virtual sub-grid point of the wiring grid node conflicts with the mask attribute of the obstacle in the wiring environment, and if the mask attribute of any virtual sub-grid point of the wiring grid node is consistent with the mask attribute of the obstacle, deleting the virtual sub-grid point in the mask conflict area.

Further, when the virtual grid point model is constructed, the defined mask number m of each wiring layer is read from the wiring resource, and the scale of the virtual sub-grid points after the virtual grid point model is constructed is m times of the initialized uniform wiring grid node number.

Further, a Dijkstra algorithm is used to perform a shortest path search on a routing grid containing routing nodes that construct the virtual lattice model.

In one implementation, the present invention further provides an integrated circuit layout wiring device satisfying multiple mask constraints, including:

An initialization module for initializing wiring resources of the integrated circuit layout;

The virtual grid point model construction module is used for constructing a virtual grid point model of wiring grid nodes suitable for a multiple mask distribution scene, wherein attribute parameters of each virtual sub-grid point in the virtual grid point model comprise coordinates, colors and mask types;

The automatic wiring and mask distribution module is used for wiring according to a wiring cost minimum principle based on the constructed virtual lattice point model, wherein the wiring cost minimum principle is that virtual sub lattice point connection wirings with the same characteristic mask are selected for adjacent wiring grid nodes; and

An output module for outputting the layout of the integrated circuit and the mask allocation result,

The automatic wiring and mask distribution module sequentially searches grid nodes in the way of a plurality of wirings according to a preset direction from a wiring source grid node; traversing the searched multiple virtual sub-grid points in the virtual grid point model corresponding to the wiring grid node; and comparing the wiring cost of the virtual sub-grid points one by one according to the principle of minimum wiring cost, and once the virtual sub-grid point with the minimum wiring cost corresponding to the searched wiring grid node is determined, terminating the traversing, and connecting and wiring the virtual sub-grid point with the minimum wiring cost.

In another implementation manner, the present invention further provides a computer readable storage medium, on which a computer program is stored, where the computer program executes the steps of the integrated circuit layout wiring method for satisfying multiple mask constraints.

Effects of the invention

The invention accelerates the node searching speed of the wiring, reduces the generation of the stitching, and improves the wiring efficiency and the manufacturability of the process.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a block diagram of an integrated circuit layout wiring device satisfying multiple mask constraints in accordance with an embodiment of the present invention.

FIG. 2 is a flow chart of an integrated circuit layout routing method that satisfies multiple mask constraints in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram of a virtual grid point model according to an embodiment of the invention.

Fig. 4 is a schematic diagram of attribute parameters of a virtual sub-grid point according to an embodiment of the present invention.

Fig. 5 is a schematic layout diagram suitable for use in a dual mask dispensing scenario in accordance with an embodiment of the present invention.

Fig. 6 is a schematic layout diagram suitable for a triple mask distribution scenario according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of the results of integrated circuit layout routing satisfying multiple mask constraints in accordance with an embodiment of the present invention.

Fig. 8 is a schematic diagram of a wiring environment including an obstacle according to an embodiment of the present invention.

Fig. 9 is a specific schematic diagram of virtual sub-grid point search, mask allocation and routing according to an embodiment of the present invention.

FIG. 10 is a functional block diagram of an integrated circuit layout wiring device with multiple mask constraints according to an embodiment of the present invention.

Detailed Description

The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

With the continuous expansion of very large scale integrated circuits (VLSI), the performance requirements for software algorithms are increasing. For example, a larger scale means a larger span of the layout, i.e., the distance between two connected points may be relatively large (the connection relationship between the two points is called a net), which places a higher demand on very large scale integrated circuit (VLSI) wiring efficiency.

The invention provides a virtual grid point model which is concise in expression and suitable for wiring of an integrated circuit layout, wherein different virtual sub-grid points correspond to different mask types respectively, when the integrated circuit layout is wired, a plurality of wiring grid nodes for connecting the wiring are searched along a preset searching direction from a wiring source grid node, wiring cost is compared with the plurality of virtual sub-grid points of the wiring grid nodes respectively, then the virtual sub-grid point with the minimum wiring cost is selected as a connection point of the wiring, and because the mask type allocated to the grid node is also determined simultaneously when the virtual sub-grid point with the minimum wiring cost is determined, the wiring and mask allocation efficiency is improved through the invention.

Regarding the wiring cost, the cost of a collision occurring at a certain node in the wiring path, i.e., the case of being contended by a plurality of nets, is generally expressed by a cost function. The lower cost indicates the more likely it is to reach the endpoint through the node. The lower cost node will be preferentially considered in the routing path search, i.e. the path expansion is preferentially started from the lower cost node, otherwise, the higher cost node will be considered last. In the invention, wiring is carried out based on the wiring cost minimum principle, wherein the wiring cost minimum principle means that in the path expansion of the current net, virtual sub-grid points with the same characteristic mask (the mask representing the same type and characteristic by using the same color representation) are preferably selected for adjacent grid nodes to carry out connection wiring, so that the effects of reducing conflict and optimizing the wiring result are achieved.

The terms related to the present invention are explained as follows:

1) Coloring (coloring): the process of assigning integrated circuit design patterns to different reticles, which are represented by different colors in the EDA tool.

2) Suture (stitch): the same integrated circuit design pattern needs to be allocated to two reticles because of some design rule conflicts, and the junction of different colors is called a stitch.

3) Conflict (conflict): and in the case that the layout and wiring result of the integrated circuit does not accord with the design rule, the design rule comprises minimum spacing between patterns, minimum line width and the like. If the integrated circuit layout is not reasonably designed, for example, the double exposure tool can color adjacent patterns into the same color (called conflict) in the two-color mask distribution stage, namely, adjacent patterns are distributed to the same mask, so that etching failure is caused.

Fig. 1 is a block diagram illustrating an integrated circuit layout wiring device 10 satisfying multiple mask constraints according to an embodiment of the present invention. The integrated circuit layout wiring device 10 satisfying multiple mask constraints provided by the invention can be realized by a general computer or a computer system.

The integrated circuit layout wiring device 10 satisfying multiple mask constraints of the present invention may be either a general purpose device or a special purpose device. The structure of the wiring device 10 of the integrated circuit layout satisfying the multiple mask constraint is not particularly limited, and may have a physical structure of the computer 20 as shown in fig. 1, for example. Specifically, the computer 20 may include a processor 20a, a memory 20b, an auxiliary storage device 20c, an input/output interface 20d, a medium drive device 20e, and a communication control device 20f, and may be connected to each other via a bus 20 g.

The processor 20a is, for example, an arbitrary processing circuit including a CPU (Central Processing Unit: central processing unit). The processor 20a may also execute programs stored in the memory 20b, the auxiliary storage device 20c, and the storage medium 20h to perform programmed processing, thereby implementing the routing process of the integrated circuit layout satisfying the multiple mask constraint according to the present invention. The processor 20a may be configured using a dedicated processor such as an ASIC or FPGA.

The memory 20b is a working memory of the processor 20a. The memory 20b is an arbitrary semiconductor memory such as a RAM (Random Access Memory: random access memory). The auxiliary storage device 20c is a nonvolatile memory such as EPROM (Erasable Programmable ROM: erasable programmable ROM) or hard disk drive (HARD DISC DRIVE).

The input-output interface 20d exchanges information with external devices (server, display device, input device).

The medium drive device 20e can output data stored in the memory 20b and the auxiliary storage device 20c to the storage medium 20h, and can read out programs, data, and the like from the storage medium 20 h. The storage medium 20h is an arbitrary recording medium that can be transported. The storage medium 20h includes, for example, an SD card, a USB (Universal Serial Bus: universal serial bus) flash memory, a CD (Compact Disc), a DVD (DIGITAL VERSATILE DISC: digital versatile Disc), and the like.

The communication control device 20f performs input and output of information to and from the network. As the communication control device 20f, for example, NIC (Network INTERFACE CARD: network interface card), wireless LAN (Local Area Network: local area Network) card, or the like is used. The bus 20g connects the processor 20a, the memory 20b, the auxiliary storage device 20c, and the like so as to be able to exchange data with each other.

The integrated circuit layout wiring device 10 configured as described above satisfies the multiple mask constraint, and executes the automatic wiring and mask allocation process shown in fig. 2.

Fig. 2 is a schematic block diagram showing a wiring method of an integrated circuit layout satisfying multiple mask constraints by the wiring device 10 according to an embodiment of the present invention.

The overall technical scheme of the wiring method of the integrated circuit layout meeting the multiple mask constraint according to the embodiment of the present invention is described in detail below with reference to fig. 2.

And step S1, initializing wiring resources of the integrated circuit layout.

In the embodiment of the invention, initializing wiring resources of an integrated circuit layout comprises the following steps: acquiring setting parameters of layout wiring of an integrated circuit, such as basic data of design rule (design rule), available wiring layers, via holes and the like; acquiring a required wiring netlist (net) and an original wiring graph; initialization of a wiring window, initialization of a wiring grid, and the like.

In addition, the initialization of the wiring resources of the integrated circuit layout further comprises setting the mask number (mask number) of the metal layer used for wiring of the integrated circuit layout, which is hereinafter referred to as M, and the virtual grid point model described later determines the scale of constructing virtual sub-grid points according to the mask number (mask number) of the defined metal layer, namely, each network node corresponds to M virtual sub-grid points.

And S2, constructing a virtual grid point model of the wiring grid node suitable for a multiple mask scene (the wiring grid node can realize multiple mask distribution) according to the wiring resources of the initialized integrated circuit layout.

In order to adapt to the multiple exposure lithography process, the wiring grid of the integrated circuit layout needs to be expanded, a virtual lattice point model suitable for multiple mask scenes is constructed, and the expanded grid of the wiring grid is obtained. By the expansion, the invention can realize different masks distributed to different wiring grid nodes at the same time of wiring, which is beneficial to improving wiring efficiency.

The invention carries out virtual modeling on the obtained wiring grid, namely abstracting (expanding) each wiring grid node into a plurality of virtual sub-grid points, wherein each virtual sub-grid point corresponds to one type of mask, a virtual grid point model is constructed on the basis, and the virtual grid point model forms an expanded grid of the wiring grid. The types of masks may be represented by different colors, shapes, identifiers, etc.

In the embodiment of the invention, the original wiring grid nodes of the integrated circuit layout are respectively and independently abstracted into M virtual sub-grid points, namely, each grid node is expanded into M virtual sub-grid points, and the total number of the expanded virtual sub-grid points is M times of the total number of the original grid nodes.

FIG. 3 (a) is a schematic diagram of a virtual lattice model constructed in accordance with the present invention. As shown in fig. 3 (a), each wiring grid node in the original very large scale integrated circuit (VLSI) layout is virtually expanded as shown in fig. 3 (a), the wiring grid node encircled by the dotted line in fig. 3 (a) is taken as an example, the encircled wiring grid node is abstracted (expanded) into 2 virtual sub-grid points, the 2 virtual sub-grid points respectively represent two different masks, the light gray is mask 1, the white is mask 2, that is, one common wiring grid node is expanded into 2 virtual sub-grid points, and fig. 3 (a) is an example of the double mask allocation for the network wiring node, which is not limited by this, and the multiple masks with more than three layers can be allocated.

In the invention, the virtual sub-grid points expanded to the wiring network nodes have both public attributes identical to those of the original wiring grid nodes and private attributes specific to the virtual sub-grid points. That is, the virtual child lattice point inherits the properties of part of the original wiring lattice node. The public attributes include, for example, a location attribute that represents the location (coordinates) of the current virtual sub-grid point in the constructed virtual grid point model, and the private attributes include, for example: color attribute: black, light gray, white, etc.; mask attributes, each virtual sub-lattice point belongs to that mask type, etc.

And step S3, wiring is carried out according to the minimum wiring cost principle based on the constructed virtual lattice point model.

The invention sequentially routes according to a routing netlist (net), comprising searching for a plurality of grid nodes in the route according to a preset direction from a routing source grid node of one net, sequentially comparing the routing cost of a plurality of virtual sub-grid points of the grid nodes under the condition of the searched grid nodes in the route, determining mask allocation based on the result of the comparison of the routing cost, and routing until the grid nodes are connected to a target grid node.

On the wiring grid, based on a constructed virtual lattice point model suitable for a multiple mask scene, a shortest path search is performed on an expanded grid of the initialized wiring grid by using, for example, dijkstra (Dijkstra) wiring algorithm, network nodes in a wiring netlist (net) are traversed, and mask allocation is realized based on calculated wiring cost of the network nodes in a conflict area until wiring is finished.

In the embodiment of the invention, when the integrated circuit layout is routed based on the constructed virtual grid point model suitable for the multiple mask scene, whether each virtual sub-grid point corresponding to the routing grid node is positioned in a conflict area in the routing environment or not needs to be considered, namely whether the virtual sub-grid point is identical with the mask attribute (or color) of the obstacle or not.

For the initial wiring grid node, virtual sub-grid points of the mask represented by any one color may be randomly selected, and for each wiring grid node in the searched wiring path, it is necessary to determine whether each virtual sub-grid point of the wiring grid node conflicts with a mask attribute (or color) of an obstacle in the wiring environment. If there is a mask conflict, that is, for the virtual sub-grid points in the wiring grid node, which are consistent with the mask attribute (or color) of the obstacle, for example, all correspond to the mask represented by light gray, in the light gray conflict area, the virtual sub-grid points represented by light gray in the virtual grid point model are deleted, and only the virtual sub-grid points for realizing the wiring connection can be selected from the virtual sub-grid points corresponding to other masks represented by the residual color (black or white) in the virtual grid point model during actual wiring.

The wiring cost minimization principle utilized by the invention is specifically exemplified as follows: as shown by arrow 1 in fig. 3 (b), if light gray virtual sub-lattice points in the virtual lattice point model of one wiring lattice node are connected to light gray virtual sub-lattice points of the virtual lattice point model of another wiring lattice node, since they are the same color, the wiring cost between them is 1; as shown by another arrow 2 in fig. 3 (b), if the virtual sub-grid points of the virtual grid point model of one wiring grid node are connected from the light gray virtual sub-grid points to the white virtual sub-grid points of the virtual grid point model of another wiring grid node, they are different colors (different colors represent different masks), and since the connection junction of different colors requires the introduction of a suture, there is a suture cost between them, and the suture cost is far greater than 1. Therefore, the virtual sub-lattice points of the mask with the same color (attribute) are preferentially selected for connection wiring in the wiring process.

In general, in an integrated circuit layout scenario that does not consider mask allocation, a layout grid node on a routable metal layer plane can be uniquely determined by x and y coordinates.

In the wiring scene considering the multiple mask allocation, after the virtual grid point model is constructed, one wiring grid node corresponds to a plurality of virtual sub-grid points in one metal layer, and only one point can not be obtained through x and y coordinates. After the virtual grid point model is constructed, the position pointed by the coordinates xy is changed into a plurality of virtual sub-grid points from one wiring grid node.

FIG. 4 is an indexed representation of attribute parameters of virtual sub-grid points of the present invention. Compared with the original wiring grid node, each virtual sub-grid point has one more mask attribute, namely each virtual sub-grid point at least comprises two attributes: (1) Coordinate attributes, denoted xy, (2) mask attributes, denoted mask. Taking a dual mask as an example, the position of one wiring grid node pointed by the coordinates xy contains two virtual sub-grid points, and the coordinates of the two virtual sub-grid points are the same but the mask attributes (mask values) are different, so that different color characterizations are respectively utilized.

Fig. 5 and 6 respectively enumerate examples of different mask properties corresponding to one wiring grid node. In the dual mask scenario of fig. 5, the mask number (mask number) of the metal layer corresponding to one wiring grid node is 2, which means that there are two masks for the current metal layer that can be selected, 2 virtual sub-grid points respectively correspond to two different types of masks, with light gray being mask 1 and white being mask 2.

In the triple mask scenario of fig. 6, the mask number (mask number) of the metal layer corresponding to one wiring grid node is 3, which means that there are two masks selectable for the current metal layer, and 3 virtual sub-grid points respectively correspond to three different types of masks, with light gray being mask 1, white being mask 2, and black being mask 3. The invention needs to determine the virtual sub-grid point which is most suitable for wiring connection in a plurality of virtual sub-grid points expanded by the wiring grid node and the mask of the virtual sub-grid point pair when the wiring is carried out, which is realized according to the wiring cost principle.

Taking fig. 6 as an example, the virtual grid point model is analyzed at any point a in the wiring grid, and the point a can be uniquely determined by coordinates (x, y) in a common wiring grid, but after the virtual grid point model is constructed in a wiring scene considering multiple mask allocation, coordinates (x, y) originally corresponding to a node of the wiring grid point to three virtual sub-grid points relative to the common wiring grid, and only if one-dimensional index mask is added, the three virtual grid points at the same coordinate position can be distinguished. Similarly, in fig. 5, the point a can be uniquely determined by coordinates (x, y) in a normal common wiring grid, but after a virtual grid point model is constructed, the coordinates of two virtual sub-grid points are xy, and the two virtual sub-grid points are distinguished by increasing a mask value.

In the wiring scene considering the distribution of multiple masks, after the wiring searching process based on the virtual lattice point model reaches the position of a preset wiring lattice node T1, three masks (masks) of a metal layer corresponding to each virtual sub-lattice point in the virtual lattice point model of the wiring lattice node T1 are sequentially traversed, and as described above, the comparison of wiring cost is performed, and finally, a virtual sub-lattice point with the minimum wiring cost is selected from the three virtual sub-lattice points at the current position of the wiring node T1, and the mask corresponding to the virtual sub-lattice point is used as the mask distributed to the current position (x, y) of the wiring node T1. Then, the wiring algorithm continues to search for the next wiring node T2 according to the predetermined direction, determines the mask allocated to the wiring node T2 and the corresponding virtual sub-grid point in the same manner as described above, and performs the pushing in this way, and allocates the mask to the wiring grid node while wiring until the wiring and mask allocation of the whole integrated circuit layout are completed.

4. The wiring result is output (step S4).

After completing the wiring and mask allocation of the entire integrated circuit layout through step S3, the present invention may graphically output the wiring results of one or more integrated circuit layouts.

Fig. 7 is an example of the routing and coloring results based on three routing netlists (net) implemented by the above method of the present invention. As shown in fig. 7, white, black, and gray represent different masks using triple mask wiring as an example.

In order to show in detail the mask search situation of the virtual sub-lattice points of the virtual lattice point model of the wiring lattice in the wiring path generation process of the present invention, taking the wiring netlist net2 as an example, the wiring environment is restored as shown in fig. 8 below.

Fig. 8 is a wiring environment of an integrated circuit layout wiring source grid node to a target grid node, the given wiring environment including an original pattern (solid line rectangular area of the obstacle blockage) on the integrated circuit layout before wiring, a color of the original pattern, a conflict area of the original pattern (broken line rectangular area of the obstacle blockage), and a color of the wiring source grid node, a color of the target grid node.

In fig. 8, S and T are the source mesh node and the target mesh node of the wiring net2, respectively, and light gray, white and dark gray on the right side of fig. 8 represent masks mask1, 2 and 3 corresponding to different virtual lattice points in the virtual lattice point model of the wiring mesh node, respectively. The source grid node S and the target grid node T of the wiring net list net2 are in the same metal layer, the original graph of the mask1 is determined to be arranged between the source grid node S and the target grid node T of the wiring, and the range of the broken line is the conflict area of the marked original graph.

Fig. 9 is a specific example of the present invention for wiring on the wiring environment shown in fig. 8.

An example of the present invention for performing shortest path search on an expanded mesh of an initialized routing mesh while achieving routing and mask allocation using Dijkstra (Dijkstra) routing algorithm on the routing environment shown in fig. 8 will be described in detail with reference to fig. 9.

S101, initializing wiring resources of an integrated circuit layout, wherein the wiring resources comprise: the area required for routing, the routing grid, the initial mask allocation for each grid node, the process rules followed by the routing, etc.

S102, constructing a virtual grid point model of wiring grid nodes suitable for multiple mask scenes according to the initialized wiring resources of the integrated circuit layout.

S103, starting from a source grid node of the wiring net list net2, searching for wiring grid nodes which can be expanded into current-stage path nodes; and determining mask allocation and virtual sub-grid points corresponding to the wiring grid nodes based on the searched virtual grid point model corresponding to the wiring grid nodes, and connecting wiring.

Fig. 9 is a schematic diagram of available virtual sub-lattice points of each routing lattice node in the path of the search process according to the present invention, and the source lattice node S of the routing net2 searches for the target lattice node T during routing.

When searching for position 1 from source mesh node S of netlist net2, it is first determined whether position 1 is within the conflict area of any mask. When it is determined that the position 1 is not in the conflict area of any mask, three virtual sub-grid points are selected at the position 1, and then, according to the principle of minimum wiring cost, the position 1 selects a mask of the same type (or color) as the source grid node S of the wiring net list net2, so that the position 1 selects a virtual sub-grid point corresponding to the mask 3; continuing the search from position 1 to position 2, it is still first determined whether position 1 is within the conflict area of any mask. When it is determined that the position 2 is located in the conflict area of the mask1, the virtual grid point of the mask1 having the type consistent with the mask1 is not available, so that only the virtual sub-grid points of the other two types of masks 2,3 are selectable in the position 2, and the virtual sub-grid point corresponding to the mask of the same type as the mask1 is selected in the position 2, namely, the virtual sub-grid point corresponding to the mask 3 is selected in the position 2 according to the minimum wiring principle. Similarly, for positions 3, 6 and 7, when it is determined that they are within the conflict area of mask1, virtual sub-grid points for masks of the type consistent with mask1 are not available, so that only the virtual sub-grid points for the remaining two masks 2,3 are selectable for positions 3, 6 and 7, and the virtual sub-grid points for three masks are selectable for positions 4, 5 which are not within the conflict area of any mask.

S104, traversing each wiring grid node between the wiring source grid node and the target grid node in turn, distributing masks to virtual sub-grid points of each wiring grid node determined according to the minimum wiring cost principle, connecting wiring, and outputting a final wiring result.

The final routing result of the present invention is shown in fig. 9, where fig. 9 shows the dashed lines connecting the dark gray virtual sub-grid points, and the mask for each grid node is uniquely determined.

According to the method of the present invention described above, the following effects can be achieved.

1) Each virtual sub-grid point in the virtual grid point model constructed by the invention is represented by a data form of [ mask, (x, y) ], and the expansion from one grid node to a plurality of virtual sub-grid points is realized. Wherein, mask represents the kind of mask corresponding to this virtual sub-lattice point, and each kind of mask is represented by different colors. The data form is simple and universal, the construction of the virtual grid point model is irrelevant to the direction, and each virtual sub-grid point in the virtual grid point model can be represented by the same data form without distinguishing the points except the pin point (the wiring starting point and the wiring ending point) or the pin point (the wiring starting point and the wiring ending point).

2) When the virtual grid point model is constructed, the defined mask number m of each wiring layer is read from the wiring resource, and the grid point scale after the virtual grid point model is constructed is m times of the number of the uniform grid points initialized when the wiring data are initialized. If two masks exist, namely m=2, the scale after constructing the virtual grid points is twice the grid point number of the original wiring grid; if there are three masks, i.e. m=3, the scale after constructing the virtual grid is three times the number of grid points of the original wiring grid, and so on.

3) The built virtual lattice point model has no edge, two types of edges are arranged between the models, one type is the same-color edge, namely, the virtual lattice points with the same mask value between two adjacent models are connected, and the cost of the edges is 1; the other type of edge is a heterochromatic edge, namely two virtual lattice point models are connected by virtual lattice points with different mask values, and the cost of the edge is the cost of a suture. In path searching, selecting corresponding virtual sub-lattice points according to the principle of minimum cost, and realizing connection between the constructed adjacent virtual lattice point models. Specifically, when the path is searched, after the path reaches a preset position, all optional virtual sub-grid points of the virtual grid point model are traversed in turn, cost comparison is carried out on each virtual sub-grid point, one mask is selected from the optional virtual sub-grid points according to the principle of minimum cost, and the mask representing the current position is allocated to the mask.

4) Virtual sub-grid points in a certain mask conflict area are not available, virtual sub-grid points corresponding to the mask are not popped up as alternatives during searching, so that the situation that the number of selectable virtual sub-grid points in a model is smaller than the total number of virtual grid points of the model occurs, the unavailable virtual sub-grid points are removed, the comparison times are reduced, and the searching time is saved.

5) The method can meet the constraint of multiple masks, the same-color spacing is kept between the same masks, different-color spacing is kept between different masks, and detailed wiring meeting the constraint of the spacing between the masks can be realized by combining different wiring algorithms.

6) Compared with the prior other models, the virtual lattice point model greatly reduces the total lattice point scale, saves the storage space, and can accelerate the searching speed by reducing the lattice point scale when applied to the searching algorithm.

In one embodiment, referring to fig. 10, the functional modules of the multi-mask constrained integrated circuit layout routing device 10 according to the present invention may specifically include:

an initialization module 101 for initializing wiring resources of the integrated circuit layout;

A virtual grid point model construction module 102, configured to construct a virtual grid point model of wiring grid nodes applicable to a multiple mask allocation scene, where attribute parameters of each virtual sub-grid point in the virtual grid point model include coordinates, colors, and mask types;

An automatic wiring and mask distribution module 103, which performs wiring according to a wiring cost minimum principle based on the constructed virtual lattice point model, wherein the wiring cost minimum principle refers to selecting virtual sub lattice point connection wirings with the mask with the same characteristic for adjacent wiring lattice nodes; and

An output module 104 for outputting the layout of the integrated circuit and the mask allocation result,

Wherein the automatic wiring and mask distribution module 103 searches for grid nodes in the course of a plurality of wirings in sequence from a wiring source grid node according to a predetermined direction; traversing the searched multiple virtual sub-grid points in the virtual grid point model corresponding to the wiring grid node; and comparing the wiring cost of the virtual sub-grid points one by one according to the principle of minimum wiring cost, and once the virtual sub-grid point with the minimum wiring cost corresponding to the searched wiring grid node is determined, terminating the traversing, and connecting and wiring the virtual sub-grid point with the minimum wiring cost.

The invention also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the wiring method of the integrated circuit layout, and can achieve the same technical effect, and in order to avoid repetition, the description is omitted here.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims (7)

1. An integrated circuit layout wiring method meeting multiple mask constraints, comprising:

(1) Initializing wiring resources of an integrated circuit layout;

(2) Constructing a virtual grid point model of wiring grid nodes suitable for a multiple mask distribution scene, wherein attribute parameters of each virtual sub-grid point in the virtual grid point model comprise coordinates, colors and mask types;

(3) Wiring is conducted according to a wiring cost minimum principle based on the constructed virtual grid point model, wherein the wiring cost minimum principle refers to selecting virtual sub grid point connection wiring with the same characteristic mask for adjacent wiring grid nodes; and

(4) Outputting the layout of the integrated circuit and the distribution result of the mask,

In the step (2), constructing a virtual lattice point model of the wiring grid node suitable for the multiple mask distribution scene includes: virtually expanding each wiring grid node into a plurality of virtual sub-grid points, wherein each virtual sub-grid point corresponds to one type of mask, and constructing a virtual grid point model on the basis;

The step (3) specifically comprises: sequentially searching a plurality of grid nodes on the way of wiring according to a preset direction from a wiring source grid node; traversing the searched multiple virtual sub-grid points in the virtual grid point model corresponding to the wiring grid node; and comparing the wiring cost of the virtual sub-grid points one by one according to the principle of minimum wiring cost, and once the virtual sub-grid point with the minimum wiring cost corresponding to the searched wiring grid node is determined, terminating the traversing, and connecting and wiring the virtual sub-grid point with the minimum wiring cost.

2. The method according to claim 1, wherein if there is a virtual sub-lattice point of the routing grid node located in the mask conflict area, the virtual sub-lattice point of the mask that causes the mask conflict is not available, and the virtual sub-lattice point is not popped up as an alternative when searching.

3. The wiring method of an integrated circuit layout satisfying multiple mask constraints according to claim 2, wherein for the searched wiring grid node, it is determined whether each virtual sub-grid point of the wiring grid node conflicts with a mask attribute of an obstacle in a wiring environment, and if the mask attribute of any virtual sub-grid point of the wiring grid node coincides with the mask attribute of the obstacle, the virtual sub-grid point in the area of the mask conflict is deleted.

4. The wiring method of integrated circuit layout meeting multiple mask constraints according to claim 1, wherein when the virtual grid point model is constructed, the defined mask number m of each wiring layer is read from wiring resources, and the scale of virtual sub-grid points after the virtual grid point model is constructed is m times of the initialized uniform wiring grid node number.

5. The integrated circuit layout routing method that satisfies the multiple mask constraint of claim 1, wherein a Dijkstra algorithm is used to perform a shortest path search on a routing grid that includes routing nodes that construct the virtual lattice point model.

6. An integrated circuit layout wiring device satisfying multiple mask constraints, comprising:

An initialization module for initializing wiring resources of the integrated circuit layout;

The virtual grid point model construction module is used for constructing a virtual grid point model of wiring grid nodes suitable for a multiple mask distribution scene, wherein attribute parameters of each virtual sub-grid point in the virtual grid point model comprise coordinates, colors and mask types;

The automatic wiring and mask distribution module is used for wiring according to a wiring cost minimum principle based on the constructed virtual lattice point model, wherein the wiring cost minimum principle is that virtual sub lattice point connection wirings with the same characteristic mask are selected for adjacent wiring grid nodes; and

An output module for outputting the layout of the integrated circuit and the mask allocation result,

Wherein, the constructing the virtual lattice point model of the wiring grid node suitable for the multiple mask distribution scene comprises: virtually expanding each wiring grid node into a plurality of virtual sub-grid points, wherein each virtual sub-grid point corresponds to one type of mask, and constructing a virtual grid point model on the basis;

The automatic wiring and mask distribution module sequentially searches grid nodes in the way of a plurality of wirings according to a preset direction from a wiring source grid node; traversing the searched multiple virtual sub-grid points in the virtual grid point model corresponding to the wiring grid node; and comparing the wiring cost of the virtual sub-grid points one by one according to the principle of minimum wiring cost, and once the virtual sub-grid point with the minimum wiring cost corresponding to the searched wiring grid node is determined, terminating the traversing, and connecting and wiring the virtual sub-grid point with the minimum wiring cost.

7. A computer readable storage medium having stored thereon a computer program, wherein the computer program when run performs the integrated circuit layout routing method steps satisfying the multiple mask constraint of any one of claims 1-5.