CN115983164B - Free component layering method, apparatus and medium for digital circuit schematic diagram - Google Patents
Free component layering method, apparatus and medium for digital circuit schematic diagram Download PDFInfo
- Publication number
- CN115983164B CN115983164B CN202310040540.1A CN202310040540A CN115983164B CN 115983164 B CN115983164 B CN 115983164B CN 202310040540 A CN202310040540 A CN 202310040540A CN 115983164 B CN115983164 B CN 115983164B
- Authority
- CN
- China
- Prior art keywords
- free
- component
- components
- free components
- layered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of integrated circuits, in particular to a free component layering method, equipment and medium for a digital circuit schematic diagram, wherein the method comprises the following steps of C1, acquiring a first free component set; step C2, initializing A m Weight W belonging to arbitrary hierarchy identification j m,j =0; step C3, generating a corresponding layered adjacent component set; step C4, generating A i Weight W belonging to arbitrary hierarchy identification j i,j The method comprises the steps of carrying out a first treatment on the surface of the Step C5, based on W i,j Determination of A i Is a hierarchical identification of (c). Step C6, A is carried out i And deleting from the I, and returning to the step C3 until the first free component set is empty. The invention can reasonably layer the free components and improves the readability of the digital circuit schematic diagram.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method, apparatus, and medium for layering free components for a digital circuit schematic.
Background
The circuit schematic diagram is a debugging means commonly used in daily work of digital circuit design, and the existing debugging tool is generally based on a component netlist, automatically generates the digital circuit schematic diagram through a certain layout and wiring algorithm and displays the digital circuit schematic diagram to a user. In the prior art, how to reasonably layer components is not fully considered when a digital circuit schematic diagram is generated, so that the subsequent components are more in pin alignment and bending and crossing conditions during wiring, the readability of the digital circuit schematic diagram is poor, and the debugging efficiency is low. Therefore, how to reasonably layer the components, reduce bending and crossing conditions during pin alignment and wiring between subsequent components, improve the readability of a digital circuit schematic diagram, enable a user to better understand the principle structure of the digital circuit, and improve the debugging analysis efficiency, and become a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a layering method, equipment and medium for free components of a digital circuit schematic diagram, which can reasonably layer the free components, reduce bending and crossing conditions during wiring and improve the readability of the digital circuit schematic diagram.
According to a first aspect of the present invention, a hierarchical method for free components in a schematic diagram of a digital circuit is provided, where the free components are components in a netlist to be processed corresponding to the schematic diagram of the digital circuit, which cannot be traversed according to a unidirectional relationship of component precursors, the components in the netlist to be processed, which can be traversed according to the unidirectional relationship of component precursors, are non-free components, the non-free components determine a hierarchical identifier in advance based on the unidirectional relationship of component precursors, and if the free components have directly connected non-free components, the directly connected non-free components must be the precursor components of the free components;
the method comprises the following steps:
step C1, obtaining a first free component set i= { a 1 ,A 2 ,...,A m ,...,A M }，A m For the M first free components, the value range of M is 1 to M, M is the total number of the first free components, and at least one A exists in the first free component set I m Directly connected with at least one non-free component, A 1 ,A 2 ,...,A m ,...,A M Has an interconnection relationship;
step C2, each A m No layering is performed at the initial time, and A is initialized m Weight W belonging to arbitrary hierarchy identification j m,j =0, initialize a m Corresponding layered contiguous component set K m Is an empty set;
step C3, traversing the first free component set I, and regarding the first free component A which is not layered i If A i Connected with any layered component, all A are obtained i Adjacent layered components, generating corresponding layered adjacent component set K i ＝{B 1 i ,B 2 i ,...,B x i ,...B f(i) i }，B x i Is A i The x-th adjacent layered component of (a), x has a value ranging from 1 to f (i), f (i) is A i Total number of layered components adjacent to each other, B x i Is a non-free component or a free component;
step C4, traversing A i Corresponding layered contiguous component set K i If B x i Is A i And (2) updating A i Belonging to [ g (xi) -1]Weights W of layers i,[g(xi)-1] ＝W i,[g(xi)-1] +1; if B x i Is A i Is to follow up on of (1)Component, update A i Belonging to [ g (xi) +1 ]]Weights W of layers i,[g(xi)+1] ＝W i,[g(xi)+1] +1, g (xi) is B x i Generates A i Weight W belonging to arbitrary hierarchy identification j i,j ；
Step C5, if there is only one maximum W i,j Will be the largest W i,j The corresponding hierarchical identifier j is determined to be A i Is a hierarchical identifier of (a); if there are a plurality of equal maximum W i,j And K is i The layered adjacent components in the circuit are all A i Will be a plurality of equal maximum W i,j The smallest hierarchical identifier in the corresponding hierarchical identifiers j is determined to be A i Or else, a plurality of equal maximum W i,j The largest hierarchical identifier in the corresponding hierarchical identifiers j is determined to be A i Is a hierarchical identification of (c).
Step C6, A is carried out i And deleting from the I, and returning to the step C3 until the first free component set I is empty.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium having computer instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the free component layering method, equipment and medium for the digital circuit schematic diagram can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects:
the invention adjusts the weight of the non-layered free components belonging to the corresponding level mark according to the contribution degree of the layered components to the non-layered free components based on the association relation among the components in the digital circuit, and reasonably divides the free components in the original digital circuit netlist into different levels according to the driving and load relation. The digital circuit schematic drawing drawn after the free component netlist layering can more clearly represent the signal flow direction in the digital circuit, reduce bending and crossing, enable the circuit schematic drawing to have better readability, and further improve the efficiency of debugging analysis by a terminal user through the schematic drawing.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for layering components for a schematic diagram of a digital circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of components driven by the same selection signal line according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of components forming a feedback structure according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a pre-processed netlist provided by an embodiment of the present invention;
fig. 5 is a schematic diagram of a hierarchical state obtained by starting traversal with an output out1 of a preprocessing network according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a hierarchical state obtained by starting traversal with an output out2 of a preprocessing network according to an embodiment of the present invention;
FIG. 7 is a flow chart of a method for layering free components for a schematic diagram of a digital circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a netlist of an example one provided by an embodiment of the present invention;
FIG. 9 is a schematic diagram of a netlist of an example two provided by an embodiment of the present invention;
FIG. 10 is a schematic diagram of a netlist of an example III provided by an embodiment of the invention;
FIG. 11 is a schematic diagram of a netlist of an example four provided by an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Embodiment 1,
An embodiment provides a component layering method for a digital circuit schematic, as shown in fig. 1, including:
s1, obtaining a netlist to be processed, wherein the netlist to be processed comprises a plurality of components and a plurality of signal lines.
The netlist to be processed is generated through synthesis by a synthesis tool based on the generated electronic design written in the hardware description language.
And S2, dividing the associated components in the netlist to be processed into the same associated component group, wherein the associated components are components driven by the same selection signal line or components forming a feedback structure mutually, and the components in the associated component group need to be divided into the same level.
It should be noted that, the components with association relationship described in step S2 are drawn at the same vertical position, that is, are divided into the same level, so that the readability of the digital circuit schematic diagram can be enhanced, and the user can better understand the circuit structure. FIG. 2 shows a set of associated components mux1, mux2 and mux3 driven by the same select signal line. Fig. 3 shows a set of components ins1 and ins2 which form a feedback structure with each other.
And S3, replacing the associated component group of the netlist to be processed with an associated component, and connecting signal lines originally connected to components in the associated component group to the associated component to generate a preprocessed netlist.
It can be understood that in the subsequent processing process, all components in the associated component group are replaced by the same associated component for layering processing, and the connection relationship among all components is unchanged.
And S4, layering the components in the pre-processed netlist based on the signal depth, determining the depth of the traversing path as the level of the components, and determining the deepest depth as the level of the components for the components with a plurality of traversing paths.
As an example, the step S2 includes:
and S21, acquiring a signal line which is not traversed currently from the netlist to be processed.
Step S22, if the currently acquired signal line is a selection signal line, the components connected with the output end of the currently acquired signal line are divided into the same associated component group.
It is understood that if the currently acquired signal line is the selection signal line, and not the selection signal line, the determination in step S23 is directly performed.
Step S23, checking all output devices of the currently acquired signal line, and if the output devices drive source devices of the currently acquired signal line, dividing the output devices and the source devices of the currently acquired signal line into the same associated component group.
And step S24, returning to the step S21 until all the signal lines in the netlist to be processed are traversed.
The finally generated associated component group is the result of union. For example, the components 1, 2, 3, and 4 are divided into the same associated component group in step S22, and the components 4 and 5 are divided into the same associated component group in step S23, so that the components 1, 2, 3, 4, and 5 are all divided into the same associated component group.
As an example, the step S4 includes:
and S41, identifying the devices connected with the output end in the preprocessing netlist as initial devices, and identifying the layer number of the initial devices as preset initial layer times.
Wherein, the preset starting layer times may be set to 1.
Step S42, selecting an initial device which is not traversed as a first component, and adding the selected first component into the first traversing path.
Step S43, selecting a second component corresponding to the first component according to the component driving relation, wherein the second component is a component which is not traversed by the first traversing path and is a precursor component of the first component.
And S44, if the second component is not layered, or the number of layered components of the second component is less than or equal to the number of layers of the first component, updating the number of layers of the second component to be 1 plus the number of layers of the first component, and adding the number of layers of the second component to the first traversal path.
When the number of layered identifiers of the second components is smaller than or equal to the number of layers identifier of the first component, the number of layers identifier of the second component is updated to be 1 added to the number of layers identifier of the first component, and finally the deepest depth can be determined as the level of the components, and bending and crossing of a digital circuit schematic diagram are reduced.
And step S45, taking the second component as the first component, returning to the step S43 until the first component has no precursor component, and executing the step S46.
And step S46, if the first traversing path has the bifurcation component, taking the bifurcation component as the first component, returning to the step S43 until all the bifurcation paths are traversed, and executing step S47.
And step S47, returning to the execution of the step S42 until all the initial devices are traversed, and determining the corresponding layers of all the components in the pre-processing netlist.
As an example, in the step S44, if the number of layered identifiers of the second component is less than or equal to the number of layer identifiers of the first component, when the number of layer identifiers of the second component is updated to be 1 added to the number of layer identifiers of the first component, the related traversed precursor components need to be updated synchronously, and the traversed precursor components continue to be updated in a traceback manner until no precursor component exists, and specifically, the step S44 further includes:
in step S441, if the number of layer identifiers of the components in the traversed path is updated, the component is used as a third component, and the number of layer identifiers of the precursor components which belong to the traversed path and are the third component are updated to be 1 plus the number of layer identifiers of the third component.
Step S442, the process returns to step S441 until the third component has no precursor component in the traversed path.
Step S41-step S47 are further described below by way of a specific example, such as the example shown in fig. 4, which is a schematic diagram of a pre-processed netlist, it being understood that the components in fig. 4 may have associated components replaced. In fig. 4 there are two outputs out1, out2. The output out1 is selected as the first component, and the steps D and C are sequentially traversed until the input in, so as to obtain the layered state shown in fig. 5, where D is located in the number of layers 1 and C is located in the number of layers 2. Then, starting traversing by the output end out2, traversing the component E, the component F, the component B and the component C in sequence to obtain the component E positioned in the layer number 1, the component F positioned in the layer number 2 and the component B positioned in the layer number 3, wherein the component C is positioned in the layer number 2 and smaller than the layer number 3, so that the component C is updated to be in the layer number 4. And B is a bifurcation component, after the component E, the component F, the component B and the component C are traversed, the component B is returned, the component B and the component A are traversed in sequence, and the component A is determined to be positioned at the layer number 4, so that the layered state shown in fig. 6 is obtained.
As an example, the step S4 further includes:
and S5, dividing the components into corresponding layers according to the layers of the components in the preprocessing netlist, recovering the associated components into corresponding components in the associated component group, and recovering and connecting signal wires on the associated components to the corresponding components in the associated component group to generate a digital circuit schematic diagram.
The first embodiment is based on the association relation among components in the digital circuit and a depth traversing method of a combined graph, the components in the original digital circuit netlist are reasonably divided into different layers according to the driving and loading relation, and the digital circuit schematic drawing drawn after the component netlist layering based on the invention can more clearly represent the signal flow direction in the digital circuit, reduce bending and crossing, so that the circuit schematic has better readability, and further improve the efficiency of debugging analysis of a terminal user through the schematic.
However, in some scenarios, some free components may exist in the netlist to be processed, for example, components of the test platform module which are not connected with the non-free components, or components which are connected with the non-free components but cannot be traversed according to the unidirectional relation of the component precursors, and the free components cannot be directly layered by the method of the first embodiment, so the invention further provides a second embodiment, and the layering of the free components is realized on the basis that the non-free components are already classified into layers. However, it should be noted that the method of dividing the non-free components into layers is not limited to the method described in the first embodiment, and may be implemented by other layering methods in the prior art.
Embodiment II,
The second embodiment provides a layering method for free components of a digital circuit schematic diagram, wherein the free components are components which cannot be traversed according to a unidirectional relation of component precursors in a netlist to be processed corresponding to the digital circuit schematic diagram, and the components which can be traversed according to the unidirectional relation of the component precursors in the netlist to be processed are non-free components. The non-free component determines the hierarchical identifier in advance based on the unidirectional relationship of the component precursors, specifically, the hierarchical identifier of the non-free component can be determined in the mode of the first embodiment, and can also be determined in the existing other hierarchical dividing modes, which are not limited herein, and all fall within the protection scope of the invention. If there is a directly connected non-free component, the directly connected non-free component must be the precursor component of the free component.
As shown in fig. 7, the method includes:
step C1, obtaining a first free component set i= { a 1 ,A 2 ,...,A m ,...,A M }，A m For the M first free components, the value range of M is 1 to M, M is the total number of the first free components, and at least one A exists in the first free component set I m Directly connected with at least one non-free component, A 1 ,A 2 ,...,A m ,...,A M The free components are connected with at least one non-free component indirectly through interconnection among the free components.
At least one A exists in the first free component set I m Directly connected to at least one non-free component means that one or more free components in the first set of free components I may be directly connected to at least one non-free component. Other free components that are not directly connected to the non-free components refer to the other free components in the first free component set I except for the free components that are directly connected to the non-free components.
Step C2, each A m No layering is performed at the initial time, and A is initialized m Weight W belonging to arbitrary hierarchy identification j m,j =0, initialize a m Corresponding layered contiguous component set K m Is an empty set.
Wherein the value range of J is 1 to J, and J is the total number of layers.
Step C3, traversing the first free component set I, and regarding the first free component A which is not layered i If A i Connected with any layered component, all A are obtained i Adjacent layered components, generating corresponding layered adjacent component set K i ＝{B 1 i ,B 2 i ,...,B x i ,...B f(i) i }，B x i Is A i The x-th adjacent layered component of (a), x has a value ranging from 1 to f (i), f (i) is A i Contiguous dividedTotal number of layer components, B x i Is a non-free component or a free component.
The adjacent component of one component refers to a precursor component or a subsequent component directly connected to the component. It will be appreciated that if A i If there is a non-free component directly connected thereto, then A i The adjacent component of (a) may be a non-free component or a free component, and the adjacent non-free component is necessarily A i Is a precursor component of (a). If A i If there is no non-free component directly connected to it, then A i All of the adjacent components of (a) are non-free components.
Step C4, traversing A i Corresponding layered contiguous component set K i If B x i Is A i And (2) updating A i Belonging to [ g (xi) -1]Weights W of layers i,[g(xi)-1] ＝W i,[g(xi)-1] +1; if B x i Is A i And (2) updating A i Belonging to [ g (xi) +1 ]]Weights W of layers i,[g(xi)+1] ＝W i,[g(xi)+1] +1, g (xi) is B x i Generates A i Weight W belonging to arbitrary hierarchy identification j i,j 。
Step C5, if there is only one maximum W i,j Will be the largest W i,j The corresponding hierarchical identifier j is determined to be A i Is a hierarchical identifier of (a); if there are a plurality of equal maximum W i,j And K is i The layered adjacent components in the circuit are all A i Will be a plurality of equal maximum W i,j The smallest hierarchical identifier in the corresponding hierarchical identifiers j is determined to be A i Or else, a plurality of equal maximum W i,j The largest hierarchical identifier in the corresponding hierarchical identifiers j is determined to be A i Is a hierarchical identification of (c).
The generation of A i Weight W belonging to arbitrary hierarchy identification j i,j Thereafter, there may be a plurality of equal maximum W i,j It is also possible to have only one maximum W i,j . When there is only oneMaximum W i,j When it is, the maximum W is directly i,j The corresponding hierarchical identifier j is determined to be A i Is required to be identified by the hierarchy of the (3). The non-free components determine the good hierarchy identification based on the unidirectional relation of the component precursors, and the precursor components are found through the subsequent components, so that the precursor components are usually newly found, and therefore the precursor components need to be divided into the previous hierarchy as much as possible. However, for free components, if the corresponding layered adjacent components are all precursor components, the subsequent components are found by the precursor, and should be divided into later layers as far as possible, so that when there are a plurality of equal maximum W i,j And K is i The layered adjacent components in the circuit are all A i In the precursor component of (2), a plurality of equal maximum W i,j The smallest hierarchical identifier in the corresponding hierarchical identifiers j is determined to be A i Is a hierarchical identification of (c).
Step C6, A is carried out i And deleting from the I, and returning to the step C3 until the first free component set I is empty.
In the first embodiment, the associated components are divided into an associated component group and replaced by an associated component for division, so that the efficiency and accuracy of hierarchical division of the non-free components can be improved, and as an example, the step C1 further includes:
step C11, obtaining a second free component set I1 = { A1 to be processed 1 ,A1 2 ,...,A1 h ,...,A H }，A1 h And H is the number of the second free components to be processed, wherein the value range of H is 1 to H, and H is the total number of the second free components.
And C12, if a plurality of second free components are components driven by the same selection signal line, dividing the plurality of second free components driven by the same selection signal line into the same associated component group, wherein the components in the same associated component group need to be divided into the same layer.
And step C13, if two second free components form a feedback structure, dividing the two second free components forming the feedback structure into the same associated component group.
Step C14, replacing all second free components belonging to the same associated component group with a first free component, replacing the second free components which are not divided into associated component groups with a first free component, and generating a first free component set I= { A 1 ,A 2 ,...,A m ,...,A M }。
It should be noted that the related component groups may be specifically divided in the manner of step S21 to step S24, which is not described herein.
As an example, the step C6 further includes determining the hierarchical identifier of the first free component corresponding to the associated component group as the hierarchical identifiers of all the second free components corresponding to the associated component group.
The free components connected with the non-free components and having interconnection relationship can be hierarchically divided through the steps C1-C6, and then the free components not directly connected with the free components are hierarchically divided, and as an example, the method further includes:
step C10, obtaining a third free component set R= { D 1 ,D 2 ,...,D n ,...,D N }，D n For the nth third free component, N is in the range of 1 to N, N is the total number of the third free components, and no third free component directly connected with the non-free component exists in the third free component set R, D 1 ,D 2 ,...,D n ,...,D N Has an interconnection relationship.
Step C20, selecting one D from the third free component set R n Will select D n The hierarchy identification of (2) is set to a preset number of starting layer times.
Wherein, the preset starting layer times may be set to 1.
And C30, layering the third free components of the third free component set R based on the signal depth, determining the depth of the traversing path as the level of the third free components, and determining the deepest depth as the level of the third free components for the third free components with a plurality of traversing paths.
As an example, step C30 may specifically implement layering the third free components of the third free component set R based on the signal depth by the method in the first embodiment, and may specifically include:
step C301, selecting an unremoved D n As a first component, the selected first component is added to the first traversal path.
Step C302, according to the device driving relationship, from { D 1 ,D 2 ,...,D n ,...,D N And selecting a second component corresponding to the first component, wherein the second component is a component which is not traversed by the first traversing path and is a precursor component of the first component.
And step C303, if the second component is not layered, or the number of layered identifiers of the second component is less than or equal to the number of layers identifier of the first component, updating the number of layers identifier of the second component to the number of layers identifier of the first component plus 1, and adding the number of layers identifier of the second component to the first traversal path.
When the number of layered identifiers of the second components is smaller than or equal to the number of layers identifier of the first component, the number of layers identifier of the second component is updated to be 1 added to the number of layers identifier of the first component, and finally the deepest depth can be determined as the level of the components, and bending and crossing of a digital circuit schematic diagram are reduced.
And step C304, taking the second component as the first component, returning to the step C302, and executing the step C305 until the first component has no precursor component.
And step C305, if the first traversing path has the bifurcation component, taking the bifurcation component as the first component, returning to execute the step C302 until all the bifurcation paths are traversed, and executing the step C306.
Step C306, returning to the execution of step C301 until all D n And after traversing, determining the corresponding layers of all the components in the third free component set.
As an example, in the step C303, if the number of layered identifiers of the second component is less than or equal to the number of layer identifiers of the first component, when the number of layer identifiers of the second component is updated to be 1 added to the number of layer identifiers of the first component, the related traversed precursor components need to be updated synchronously, and the traversed precursor components continue to be updated in a traceback manner until no precursor component exists, and specifically, the step C303 further includes:
and step C3031, if the layer number identification of the component in the traversed path is updated, taking the component as a third component, and updating the layer number identification of the precursor component which belongs to the traversed path and is the third component into the layer number identification of the third component plus 1.
Step C3032, the execution of step C3031 is returned until the third component does not have a precursor component in the traversed path.
In the first embodiment, the associated components are divided into an associated component group and replaced by an associated component for division, so that the efficiency and accuracy of hierarchical division of the non-free components can be improved, and as an example, the step C10 further includes:
step C101, obtaining a fourth free component set R1 = { D1 to be processed 1 ,D1 2 ,...,D1 v ,...,D1 V }，D1 v And for the fourth free components to be processed in the V, the value range of V is 1 to V, and V is the total number of the fourth free components.
And step C102, if a plurality of fourth free components are components driven by the same selection signal line, dividing the plurality of fourth free components driven by the same selection signal line into the same associated component group, wherein the components in the same associated component group need to be divided into the same layer.
And step C103, if two fourth free components form a feedback structure, dividing the two fourth free components forming the feedback structure into the same associated component group.
Step C104, replacing all fourth free components belonging to the same association component group with a third free component, which is not divided and associatedThe fourth free component of the component group is replaced by a third free component, and the third free component set R= { D is generated 1 ,D 2 ,...,D n ,...,D N }。
It should be noted that the related component groups may be specifically divided in the manner of step S21 to step S24, which is not described herein.
As an example, the step C6 further includes determining the level identifier of the third free component corresponding to the associated component group as the level identifiers of all the fourth free components corresponding to the associated component group.
The free device layering is further illustrated by several specific examples:
example one,
As shown in FIG. 8, component A, component B, and component C are non-free devices, and component A, component B, and component C have been divided over the y-1, y, and y+1 layers, respectively. Component D and component E are free devices.
For component D, it is possible to obtain by steps C1-C6: component D is a weight W of the y-1 th layer D,y-1 =0, component D belongs to weight W of the y-th layer D,y =1, component D belongs to weight W of layer y+1 D,y+1 =0, only one maximum weight W exists D,y The level of the component D is thus determined as y.
For component E, it is obtained by steps C1-C6: the component E belongs to the weight W of the y-1 layer E,y-1 =1, component E belongs to weight W of the y-th layer E,y =1, component E belongs to weight W of layer y+1 E,y+1 =0, there are two largest weights W E,y-1 And W is E,y And both the adjacent layered components B and C of the component E are precursor components of the component E, so the level of the component E is determined as y-1.
Example two,
As shown in fig. 9, example two adds component G and component F on the basis of example one.
On the basis of example one, for component F, the following steps are passedC1-step C6 can be obtained: the component F belongs to the weight W of the y-th layer F,y =1, component F belongs to weight W of layer y+1 F,y+1 =1, the other weights are 0, there are two largest weights W F,y And W is F,y+1 And both the adjacent layered components D and E of the component F are subsequent components of the component F, the level of the component F is determined as y+1.
After the component F is layered, it is obtained through steps C1 to C6: component G is of weight W of the (y+2) th G,y+2 =1, the other weights are 0, and there is one maximum weight, so the level of the component G is directly determined as y+2.
Example III,
As shown in fig. 10, example three adds component H and component I on the basis of example one.
On the basis of example one, for component H, it is possible to obtain by steps C1 to C6: the component H belongs to the weight W of the y-1 layer H,y-1 =1, component H belongs to weight W of the y-2 th layer H,y-2 =1, the other weights are 0, there are two largest weights W H,y-1 、W H,y-2 And the adjacent layered components D and E of the component H are both the component H precursor components, so the level of the component H is determined as y-2.
After the component H is layered, it can be obtained through steps C1 to C6: the weight of the component I belonging to the y-3 layer is W I,y-3 =1, the other weights are 0, there is one maximum weight, so the level of component I is directly determined as y-3.
Example four,
As shown in fig. 11, example four adds component P and component Q on the basis of example one.
On the basis of example one, for component P, it is possible to obtain by steps C1 to C6: the component P belongs to the weight W of the y-1 layer P,y-1 =1, component P belongs to weight W of the y-th layer P,y =1, the other weights are 0, there are two largest weights W P,y-1 And W is P,y-1 The adjacent layered component D of the component P is a precursor component of the component P, and the adjacent layered component D of the component P is an adjacent layered componentThe layered component E is a subsequent component to the component P, and thus the level of the component P is determined as y.
After the component P is layered, it is obtained through steps C1 to C6: the weight of the component Q belonging to the y+1 layer is W Q,y+1 =1, and the other weights are 0, so the level of the component Q is directly determined as y+1.
Based on the association relation among components in the digital circuit, the embodiment adjusts the weight of the non-layered free components belonging to the corresponding level mark according to the contribution degree of the layered components to the non-layered free components, and reasonably divides the free components in the original digital circuit netlist into different levels according to the driving and loading relation. The digital circuit schematic drawing drawn after the free component netlist layering can more clearly represent the signal flow direction in the digital circuit, reduce bending and crossing, enable the circuit schematic drawing to have better readability, and further improve the efficiency of debugging analysis by a terminal user through the schematic drawing.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (8)
1. A layering method for free components of a digital circuit schematic diagram is characterized in that,
the free components are components which cannot be traversed according to the unidirectional relation of the component precursors in the netlist to be processed corresponding to the digital circuit schematic diagram, the components which can be traversed according to the unidirectional relation of the component precursors in the netlist to be processed are non-free components, the non-free components are determined to be of a hierarchical mark in advance based on the unidirectional relation of the component precursors, and if the free components have directly connected non-free components, the directly connected non-free components are necessarily the precursor components of the free components;
the method comprises the following steps:
step C1, obtaining a first free component set i= { a 1 ,A 2 ,...,A m ,...,A M }，A m For the M first free components, the value range of M is 1 to M, M is the total number of the first free components, and at least one A exists in the first free component set I m Directly connected with at least one non-free component, A 1 ,A 2 ,...,A m ,...,A M The free components which are not directly connected with the non-free components are indirectly connected with at least one non-free component through interconnection among the free components;
step C2, each A m No layering is performed at the initial time, and A is initialized m Weight W belonging to arbitrary hierarchy identification j m,j =0, initialize a m Corresponding layered contiguous component set K m Is an empty set;
step C3, traversing the first free component set I, and regarding the first free component A which is not layered i If A i Connected with any layered component, all A are obtained i Adjacent layered components, generating corresponding layered adjacent component set K i ＝{B 1 i ,B 2 i ,...,B x i ,...B f(i) i }，B x i Is A i The x-th adjacent layered component of (a), x has a value ranging from 1 to f (i), f (i) is A i Total number of layered components adjacent to each other, B x i Is a non-free component or a free component;
step C4, traversing A i Corresponding layered contiguous component set K i If B x i Is A i And (2) updating A i Belonging to [ g (xi) -1]Weights W of layers i,[g(xi)-1] ＝W i,[g(xi)-1] +1; if B x i Is A i And (2) updating A i Belonging to [ g (xi) +1 ]]Weights W of layers i,[g(xi)+1] ＝W i,[g(xi)+1] +1, g (xi) is B x i Generates A i Weight W belonging to arbitrary hierarchy identification j i,j ；
Step C5, if there is only one maximum W i,j Will be the largest W i,j The corresponding hierarchical identifier j is determined to be A i Is a hierarchical identifier of (a); if there are a plurality of equal maximum W i,j And K is i The layered adjacent components in the circuit are all A i Will be a plurality of equal maximum W i,j The smallest hierarchical identifier in the corresponding hierarchical identifiers j is determined to be A i Or else, a plurality of equal maximum W i,j The largest hierarchical identifier in the corresponding hierarchical identifiers j is determined to be A i Is a hierarchical identifier of (a);
step C6, A is carried out i And deleting from the I, and returning to the step C3 until the first free component set I is empty.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step C1 further includes:
step C11, obtaining a second free component set I1 = { A1 to be processed 1 ,A1 2 ,...,A1 h ,...,A1 H }，A1 h For the H second free components to be processed, the value range of H is 1 to H, and H is the total number of the second free components;
step C12, if a plurality of second free components are components driven by the same selection signal line, dividing the plurality of second free components driven by the same selection signal line into the same associated component group, wherein components in the same associated component group need to be divided into the same level;
step C13, if two second free components form a feedback structure, dividing the two second free components forming the feedback structure into the same associated component group;
step C14, replacing all second free components belonging to the same associated component group with a first free component, replacing the second free components which are not divided into associated component groups with a first free component, and generating a first free component set I= { A 1 ,A 2 ,...,A m ,...,A M }。
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
and step C6 is followed by determining the hierarchical identifications of the first free components corresponding to the associated component group as the hierarchical identifications of all the second free components corresponding to the associated component group.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the method further comprises the steps of:
step C10, obtaining a third free component set R= { D 1 ,D 2 ,...,D n ,...,D N }，D n For the nth third free component, N is in the range of 1 to N, N is the total number of the third free components, and no third free component directly connected with the non-free component exists in the third free component set R, D 1 ,D 2 ,...,D n ,...,D N Has an interconnection relationship;
step C20, selecting one D from the third free component set R n Will select D n Setting the hierarchy mark as the preset initial layer times;
and C30, layering the third free components of the third free component set R based on the signal depth, determining the depth of the traversing path as the level of the third free components, and determining the deepest depth as the level of the third free components for the third free components with a plurality of traversing paths.
5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
the step C10 further includes:
step C101, obtaining a fourth free component set R1 = { D1 to be processed 1 ,D1 2 ,...,D1 v ,...,D1 V }，D1 v The value range of V is 1 to V, and V is the total number of the fourth free components;
step C102, if a plurality of fourth free components are components driven by the same selection signal line, dividing the plurality of fourth free components driven by the same selection signal line into the same associated component group, wherein components in the same associated component group need to be divided into the same level;
step C103, if two fourth free components form a feedback structure, dividing the two fourth free components forming the feedback structure into the same associated component group;
step C104, replacing all fourth free components belonging to the same associated component group with a third free component, and replacing the fourth free components which are not divided into associated component groups with a third free componentInstead, the third free component set r= { D is generated 1 ,D 2 ,...,D n ,...,D N }。
6. The method of claim 5, wherein the step of determining the position of the probe is performed,
and step C6 is followed by determining the level identification of the third free component corresponding to the associated component group as the level identification of all fourth free components corresponding to the associated component group.
7. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-6.
8. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310040540.1A CN115983164B (en) | 2023-01-12 | 2023-01-12 | Free component layering method, apparatus and medium for digital circuit schematic diagram |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310040540.1A CN115983164B (en) | 2023-01-12 | 2023-01-12 | Free component layering method, apparatus and medium for digital circuit schematic diagram |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115983164A CN115983164A (en) | 2023-04-18 |
| CN115983164B true CN115983164B (en) | 2023-08-15 |
Family
ID=85959578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310040540.1A Active CN115983164B (en) | 2023-01-12 | 2023-01-12 | Free component layering method, apparatus and medium for digital circuit schematic diagram |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115983164B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6567958B1 (en) * | 2000-02-28 | 2003-05-20 | International Business Machines Corporation | Invention to allow hierarchical logical-to-physical checking on chips |
| CN106411682A (en) * | 2015-07-30 | 2017-02-15 | 周祥宇 | Social system and method thereof based on ad-hoc networking technology |
| CN109800534A (en) * | 2019-02-14 | 2019-05-24 | 广东高云半导体科技股份有限公司 | FPGA design circuit drawing generating method, device, computer equipment and storage medium |
| WO2021057465A1 (en) * | 2019-09-26 | 2021-04-01 | 中兴通讯股份有限公司 | Method and apparatus for performing parallel processing on deep learning model |
| CN113919252A (en) * | 2021-12-16 | 2022-01-11 | 北京云枢创新软件技术有限公司 | Component connectivity detection system based on different design data |
-
2023
- 2023-01-12 CN CN202310040540.1A patent/CN115983164B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6567958B1 (en) * | 2000-02-28 | 2003-05-20 | International Business Machines Corporation | Invention to allow hierarchical logical-to-physical checking on chips |
| CN106411682A (en) * | 2015-07-30 | 2017-02-15 | 周祥宇 | Social system and method thereof based on ad-hoc networking technology |
| CN109800534A (en) * | 2019-02-14 | 2019-05-24 | 广东高云半导体科技股份有限公司 | FPGA design circuit drawing generating method, device, computer equipment and storage medium |
| WO2021057465A1 (en) * | 2019-09-26 | 2021-04-01 | 中兴通讯股份有限公司 | Method and apparatus for performing parallel processing on deep learning model |
| CN113919252A (en) * | 2021-12-16 | 2022-01-11 | 北京云枢创新软件技术有限公司 | Component connectivity detection system based on different design data |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115983164A (en) | 2023-04-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0726538A2 (en) | Topology-based computer-aided design system for digital circuits and method thereof | |
| CN110502447B (en) | Regression test case priority ordering method based on graph | |
| US20070094204A1 (en) | Rule processing method and apparatus providing automatic user input selections | |
| US6477689B1 (en) | Architectural structure of a process netlist design tool | |
| US8280836B2 (en) | Converting unordered graphs to oblivious read once ordered graph representation | |
| JP2010128583A (en) | Test-facilitating design apparatus, its method and program | |
| CN115983164B (en) | Free component layering method, apparatus and medium for digital circuit schematic diagram | |
| CN116108778B (en) | Component layering method, device and medium for digital circuit schematic diagram | |
| JP2002311111A (en) | Test vector compressing method | |
| US7693694B2 (en) | Shape simulation method, program and apparatus | |
| EP2820547B1 (en) | Debugging method and computer program product | |
| US7496876B1 (en) | Method for generating integrated functional testcases for multiple boolean algorithms from a single generic testcase template | |
| Cheng | Single clock partial scan | |
| JP4891807B2 (en) | High level synthesis apparatus and high level synthesis method | |
| CN116011395B (en) | Module-exchange-based circuit schematic diagram module column ordering method, equipment and medium | |
| US7761835B2 (en) | Semiconductor device design method, semiconductor device design system, and computer program for extracting parasitic parameters | |
| US6886144B2 (en) | Logic verification method for semiconductor device | |
| US11048971B1 (en) | Method for training image generation model and computer device | |
| JP2011053764A (en) | Behavioral synthesis verification auxiliary device, behavioral synthesis verification auxiliary method, program and recording medium | |
| CN103164565A (en) | Method for automatically forming antenna regular test vectors | |
| JP4268694B2 (en) | Wiring processing method, wiring processing apparatus, and recording medium for wiring processing program | |
| JP3805298B2 (en) | Integrated circuit testability design method and apparatus | |
| JP2008186230A (en) | Integrated circuit design device, integrated circuit design method and integrated circuit design program | |
| JP5136257B2 (en) | Route management method | |
| JP2002149725A (en) | Device and method for generating three-dimensional expansion data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |