CN115966507A

CN115966507A - Semiconductor element with plug structure and preparation method thereof

Info

Publication number: CN115966507A
Application number: CN202210498934.7A
Authority: CN
Inventors: 黄则尧
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2021-10-08
Filing date: 2022-05-09
Publication date: 2023-04-14
Also published as: TW202316611A; TWI803140B

Abstract

The present disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a plug structure including a bottom conductive layer disposed on the substrate, a middle conductive layer disposed on the bottom conductive layer, a top conductive layer disposed on the middle conductive layer, and an insulating cap layer covering a sidewall of the middle conductive layer and disposed between the bottom conductive layer and the top conductive layer; and a first dielectric layer disposed on the substrate and surrounding the plug structure. A width of the bottom conductive layer is greater than a width of the middle conductive layer. A width of the top conductive layer is greater than the width of the middle conductive layer.

Description

Semiconductor element with plug structure and preparation method thereof

Cross-referencing

The present application claims priority and benefit from U.S. patent application Nos. 17/497,775 and 17/500,456 (priority date "8/10/2021" and "13/10/2021"), the contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to semiconductor devices and, particularly, to a semiconductor device with a plug structure and a method for fabricating the same.

Background

Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are continually being scaled to meet the ever increasing demand for computing power. However, various problems occur in the process of downsizing, and such problems are increasing. Thus, challenges remain in achieving improved quality, yield, performance, and reliability, as well as reduced complexity.

The above description of "prior art" merely provides background and does not constitute an admission that the above description of "prior art" discloses the subject matter of the present disclosure, and does not constitute prior art to the present disclosure, nor should any of the above description of "prior art" be taken as an admission that the present disclosure is prior art.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor device, including: a substrate; a plug structure including a bottom conductive layer disposed on the substrate, a middle conductive layer disposed on the bottom conductive layer, a top conductive layer disposed on the middle conductive layer, and an insulating cover layer covering a sidewall of the middle conductive layer and disposed between the bottom conductive layer and the top conductive layer; and a first dielectric layer disposed on the substrate and surrounding the plug structure. A width of the bottom conductive layer is greater than a width of the middle conductive layer. A width of the top conductive layer is greater than the width of the middle conductive layer.

In some embodiments, the width of the bottom conductive layer is substantially the same as an overall width consisting of the width of the middle conductive layer and a thickness of the insulating capping layer.

In some embodiments, a sidewall of the top conductive layer, a sidewall of the insulating cap layer, and a sidewall of the bottom conductive layer are substantially coplanar.

In some embodiments, a top surface of the first dielectric layer is located at about a vertical level between a top surface of the top conductive layer and a bottom surface of the top conductive layer.

In some embodiments, the semiconductor device includes a bottom dielectric layer disposed between the first dielectric layer and the substrate.

In some embodiments, the semiconductor device includes a second dielectric layer disposed on the first dielectric layer. A top surface of the second dielectric layer is at a vertical level greater than the top surface of the top conductive layer.

In some embodiments, the semiconductor component includes a contact disposed on and electrically connected to the top conductive layer.

In some embodiments, the contact includes a lower portion disposed on the top conductive layer and an upper portion disposed on the lower portion, and a width of the upper portion is greater than a width of the lower portion.

In some embodiments, the semiconductor device includes a third dielectric layer disposed on the second dielectric layer and surrounding the contact.

In some embodiments, a thickness of the bottom conductive layer is substantially the same as a thickness of the top conductive layer.

In some embodiments, a thickness of the bottom conductive layer is greater than a thickness of the top conductive layer.

In some embodiments, the first dielectric layer comprises a porous dielectric material, the middle conductive layer comprises aluminum and copper, the bottom conductive layer and the top conductive layer comprise titanium and titanium nitride, and the insulating capping layer comprises aluminum oxide.

In some embodiments, a ratio of a thickness of the insulating capping layer to a width of the intermediate conductive layer is between about 1:20 to about 1:2000, in the range of the said catalyst.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate; sequentially forming a layer of a first conductive material, a layer of a second conductive material, a layer of a third conductive material and an anti-reflection coating on the substrate; performing a plug etch process to convert the layer of the first conductive material into a bottom conductive layer on the substrate, the layer of the second conductive material into a middle conductive layer on the bottom conductive layer, and the layer of the third conductive material into a top conductive layer on the middle conductive layer; selectively forming an insulating cover layer on a sidewall of the intermediate conductive layer; and forming a first dielectric layer on the substrate and surrounding a plug structure. The bottom conductive layer, the middle conductive layer, the top conductive layer and the insulating cover layer collectively configure the plug structure. A width of the bottom conductive layer is greater than a width of the middle conductive layer, and a width of the top conductive layer is greater than the width of the middle conductive layer.

In some embodiments, the method of fabricating a semiconductor device includes forming a bottom dielectric layer between the first dielectric layer and the substrate.

In some embodiments, the method further includes performing an etch back process to lower a top surface of the first dielectric layer to a vertical level between a top surface of the top conductive layer and a bottom surface of the top conductive layer.

In some embodiments, the method of manufacturing a semiconductor device includes: forming a second dielectric layer on the first dielectric layer and surrounding the top conductive layer and the anti-reflective coating; forming a third dielectric layer on the second dielectric layer and the anti-reflection coating; forming a contact hole by removing a portion of the anti-reflective coating and the third dielectric layer; and forming a contact in the contact hole to electrically connect with the top conductive layer. The top conductive layer is exposed through the contact hole.

In some embodiments, a hardness of the second dielectric layer may be greater than a hardness of the first dielectric layer.

In some embodiments, the bottom dielectric layer comprises silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-on low dielectric constant (low-k) dielectric layers, chemical vapor deposited low-k dielectric layers, or combinations thereof.

Due to the design of the semiconductor device of the present disclosure, the insulating capping layer may prevent metal ions in the intermediate conductive layer from diffusing out to contaminate adjacent devices (e.g., the first dielectric layer), and thus may reduce short circuits between adjacent conductive features. Therefore, the reliability and electrical characteristic performance of the semiconductor element can be improved.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages, which configure the disclosed claims of the present disclosure, will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.

Fig. 1 is a flow chart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 to 11 are cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 12 to 15 are cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

Description of reference numerals:

1A: semiconductor device with a plurality of semiconductor chips

10: preparation method

101: substrate

103: contact hole

103L: lower part

103U: upper part

105: contact point

105L: lower part

105U: upper part

201: plug structure

203: bottom conductive layer

203S: side wall

205: intermediate conductive layer

205S: side wall

207: top conductive layer

207S: side wall

207TS: top surface of the container

209: insulating cover layer

209S: side wall

301: bottom dielectric layer

303: first dielectric layer

303TS: top surface of the container

305: a second dielectric layer

307: a third dielectric layer

401: a first conductive material

403: a second conductive material

405: a third conductive material

407: anti-reflective coating

407TS: top surface of the container

409: first mask layer

411: energy removable material

S11: step (ii) of

S13: step (ii) of

S15: step (ii) of

S17: step (ii) of

T1: thickness of

T2: thickness of

T3: thickness of

VL1: vertical horizontal plane

VL2: vertical horizontal plane

W1: width of

W2: width of

W3: width of

W4: total width

W5: width of

W6: width of

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and/or desired properties of the elements. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for brevity and clarity. In the drawings, some layers/features may be omitted for simplicity.

Furthermore, for ease of description, spatially relative terms such as "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The elements may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

It will be understood that, although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, the terms are only used to distinguish one element from another. Thus, for example, a first element, first component, or first section discussed below could be termed a second element, second component, or second section without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, when a term such as "same", "equal", "planar", or "coplanar" is used herein in reference to a direction, a layout, a position, a shape, a size, a number, or other measure, it does not necessarily mean exactly the same direction, layout, position, shape, size, number, or other measure, but rather means that the direction, layout, position, shape, size, number, or other measure is nearly the same within an acceptable range of variations that may occur, for example, as a result of a manufacturing process. The term "substantially" may be used to reflect this meaning. For example, items described as "substantially identical," "substantially equal," or "substantially planar" may be identical, equal, or planar, or may be identical, equal, or planar within acceptable variations, such as may occur due to manufacturing processes.

In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and an electro-optical element, a light-emitting display element, a semiconductor circuit, and an electronic element are included in the scope of the semiconductor element.

It should be understood that in the description of the present disclosure, the upper (or upper) corresponds to the direction of the arrow of the direction Z, and the lower (or lower) corresponds to the opposite direction of the arrow of the direction Z.

It should be understood that in the description of the present disclosure, the terms "forming", "formed" and "forming" may refer to and include any method of creating, building, patterning, implanting or depositing elements, dopants or materials. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

It should be understood that in the description of the present disclosure, the functions or steps indicated may occur out of the order indicated in the figures. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or the figures may sometimes be executed in the reverse order, depending upon the functionality or steps involved.

Fig. 1 is a flow chart illustrating a method 10 of fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Fig. 2 to 11 are cross-sectional views illustrating a manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

Referring to fig. 1 to 5, in step S11, a substrate 101 may be provided, a bottom dielectric layer 301 may be formed on the substrate 101, and a plurality of plug structures 201 may be formed on the bottom dielectric layer 301.

Referring to fig. 2, in some embodiments, the substrate 101 may be a bulk (bulk) semiconductor substrate entirely composed of at least one semiconductor material; the bulk semiconductor substrate does not contain any dielectric, insulating layer, or conductive features. The bulk semiconductor substrate may be fabricated, for example, from an intrinsic semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductor, or group II-VI compound semiconductor; or a combination thereof.

In some embodiments, the substrate 101 may include a semiconductor-on-insulator (SOI) structure including, from bottom to top, a handle substrate, an insulator layer, and an uppermost semiconductor material layer. The fabrication technique for the handle substrate and the uppermost semiconductor material layer may be through the same materials as the bulk semiconductor substrate described above. The insulator layer may be a crystalline or amorphous dielectric material such as an oxide and/or nitride. For example, the insulating layer may be a dielectric oxide such as silicon oxide (silicon oxide). For another example, the insulator layer may be a dielectric nitride, such as silicon nitride (silicon nitride) or boron nitride (boron nitride). Also for example, the insulator layer may comprise a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulator layer may have a thickness in a range of 10 nanometers (nm) to 200 nm.

It should be understood that in describing the present disclosure, the term "about" modifies the amount of an ingredient, composition, or reactant of the present disclosure by indicating that a change in the numerical amount may occur, for example, through typical measurement and liquid handling procedures used to make concentrates or solutions. Furthermore, inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used to make a composition or perform a method, and the like may all produce variations. In one embodiment, the term "about" refers to within 10% of the disclosed value. In another embodiment, the term "about" refers to within 5% of the disclosed value. In yet another embodiment, the term "about" refers to within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the disclosed value.

In some embodiments, the substrate 101 may include a plurality of device elements (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive features (not shown for clarity).

In some embodiments, a plurality of element units may be formed on the bulk semiconductor substrate or the uppermost semiconductor material layer. Some portions of the plurality of element units may be formed in the bulk semiconductor substrate or the uppermost semiconductor material layer. The plurality of element units may be transistors, such as Complementary Metal Oxide Semiconductor (CMOS) transistors, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), fin field effect transistors (finfets), etc., or combinations thereof.

In some embodiments, a plurality of dielectric layers may be formed on the bulk semiconductor substrate or the uppermost semiconductor material layer and cover the plurality of element units. In some embodiments, the plurality of dielectric layers may be formed by, for example, silicon oxide (silicon oxide), borophosphate glass (borophosphate glass), undoped silicate glass (undoped silicate glass), fluorinated silicate glass (fluorinated silicate glass), low dielectric constant (low-k) materials, or the like, or combinations thereof. The term "(low-k)" as used in this disclosure refers to a dielectric material having a dielectric constant less than that of silicon dioxide. The dielectric constant of the low-k material may be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k material may be less than 2.0. The plurality of dielectric layers may be formed by a deposition process, such as a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the like. The deposition process may be followed by a planarization process to remove excess material and provide a substantially planar surface for subsequent process steps.

In some embodiments, the plurality of conductive features may include an interconnect layer, a conductive via (via), and a conductive pad (pad). The interconnect layers may be separated from each other and may be horizontally disposed in the plurality of dielectric layers in the Z-direction. In this embodiment, the topmost interconnect layer may be designated as a conductive pad. The conductive vias may connect adjacent interconnect layers, adjacent element units and interconnect layers, and adjacent conductive pads and interconnect layers in the Z-direction. In some embodiments, the conductive vias may improve heat dissipation and may provide structural support. In some embodiments, the fabrication technique of the plurality of conductive features may be, for example, tungsten (W), cobalt (Co), zirconium (Zr), tantalum (Ta), titanium (Ti), aluminum (Al), ruthenium (Ru), copper (Cu), metal carbides (such as tantalum carbide (TaC), titanium carbide (TiC), tantalum magnesium carbide (TaMgC)), metal nitrides (such as titanium nitride (TiN)), transition metal aluminides, or combinations thereof. The plurality of conductive features may be formed during the process of forming the plurality of dielectric layers.

In some embodiments, the plurality of element units and the plurality of conductive features may collectively configure a functional unit of the semiconductor element 1A. In the description of the present disclosure, a functional unit generally refers to a circuit related to a function, which has been divided into an independent unit. In some embodiments, the functional units may be typically highly complex circuits, such as processor cores, memory controllers, or accelerator units. In other embodiments, the complexity and functionality of the functional units may be more or less complex.

Referring to fig. 2, a bottom dielectric layer 301 may be formed on a substrate 101. The bottom dielectric layer 301 may comprise, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-on (spin-on) low-k dielectric layers, chemical vapor deposited low-k dielectric layers, or combinations thereof. In some embodiments, the bottom dielectric layer 301 may comprise a self-planarizing material, such as spin-on glass or spin-on low-k dielectric materials, such as SilKTM. The use of a self-planarizing dielectric material may avoid performing subsequent planarization steps. In some embodiments, the bottom dielectric layer 301 may be formed by a deposition process including, for example, a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, an evaporation process, or a spin-on coating process.

Referring to fig. 2, a first conductive material layer 401 may be formed on the bottom dielectric layer 301. In some embodiments, the first conductive material 401 may include, for example, titanium nitride, titanium silicon nitride, tantalum nitride, tantalum silicon nitride, or a combination thereof. In some embodiments, the first conductive material layer 401 may be fabricated by, for example, an Atomic Layer Deposition (ALD) process, a chemical vapor deposition (cvd) process, and/or a sputtering (sputtering) process. In some embodiments, the first layer of conductive material 401 may be selectively subjected to oxidation, nitridation or other processes to form oxides, nitrides and/or other metal compounds in the first layer of conductive material 401.

Referring to fig. 2, a second conductive material 403 layer may be formed on the first conductive material 401 layer. In some embodiments, the second conductive material 403 may include, for example, aluminum, copper, and combinations thereof.

In some embodiments, the second conductive material 403 is an alloy of aluminum and copper, and the content of aluminum is greater than the content of copper. It has been found that the addition of small amounts of copper to aluminum improves electromigration resistance, while such addition may reduce the occurrence of hillocks (hillocks), which are small protrusions on the surface of the aluminum layer. In some embodiments, the second conductive material 403 layer may be formed by a chemical vapor deposition process and/or a sputtering process. In some embodiments, the process temperature of the fabrication technique of the second conductive material 403 layer may be in the range of about 100 ℃ to about 400 ℃. In some embodiments, the process pressure of the fabrication technique of the layer of second conductive material 403 may be in a range of about 1 millitorr (mTorr) to about 100 mTorr. In some embodiments, the thickness of the layer of second conductive material 403 may be in the range of about 4000 angstroms (angstrom) to about 11000 angstroms.

Referring to fig. 2, a third layer of conductive material 405 may be formed on the second layer of conductive material 403. In some embodiments, the third conductive material 405 may include, for example, titanium nitride, titanium silicon nitride, tantalum nitride, tantalum silicon nitride, or a combination thereof. In some embodiments, the third conductive material 405 layer may be formed by an atomic layer deposition process, a chemical vapor deposition process, and/or a sputtering process. In some embodiments, the third layer of conductive material 405 may be selectively subjected to oxidation, nitridation or other processes to form oxides, nitrides and/or other metal compounds in the third layer of conductive material 405.

Referring to fig. 2, an anti-reflective coating 407 may be formed on the third conductive material 405 layer. The anti-reflective coating 407 may suppress the reflection of the underlying layer (as shown in fig. 3 and 4) during the underlying patterning process to provide accurate pattern replication. In some embodiments, the anti-reflective coating 407 may include silicon nitride and titanium nitride.

In some embodiments, the fabrication technique of the anti-reflective coating 407 can be by reaction of a process gas comprising a silane compound and an oxygen and carbon containing compound (such as carbon dioxide or an organosilicon compound). The anti-reflective coating 407 may include at least silicon and oxygen, and may further include carbon. The fabrication technique of the anti-reflective coating 407 may be by a plasma enhanced chemical vapor deposition process. The anti-reflective coating 407 may exhibit a dielectric constant of about 11 or less, such as about 4 or less.

In some embodiments, silane-based compounds suitable for use in plasma enhanced chemical vapor deposition processes can include oxygen-free silane-based compounds. The oxygen-free silyl compound may have the formula Si _x H _2x+2 、Si _x H _y C _lz 、(CH3) _z Si _x H _y Or a combination thereof. X may be equal to 1 to 4, Y may be equal to 2X +1, and Z may be equal to 1 to 2X +2. Examples of such compounds include silane, disilane, chlorosilane (chlorosilane), dichlorodisilane (dichlorosilane), hexachlorosilane (hexachlorosilane), methylsilane (methylsilane), dimethylsilane (dimethylsilane), and the likeSilane (dimethylsilane), trimethylsilane (trimethylsilane), tetramethylsilane (tetramethylsilane), and combinations thereof. One or more oxygen-free silane-based compounds may be used in a plasma enhanced chemical vapor deposition process. A silane based compound, such as silane, can be provided to the plasma processing chamber at a flow rate in a range of about 100sccm (standard milliliters per minute) to about 700 sccm.

In some embodiments, suitable oxygen-containing and carbon-containing compounds may include carbon dioxide, carbon monoxide, and oxygen-containing organosilicon compounds. Suitable oxygen-containing organosilicon compounds include tetraethoxysilane, triethoxyfluorosilane, 1,3,5, 7-tetramethylcyclotetrasiloxane, dimethyldiethoxysilane, dimethyldimethoxysilane, 1, 3-dimethyldisiloxane, 1, 3-tetramethyldisiloxane, hexamethyldisiloxane, 1, 3-bis (silylene) disiloxane. Bis (1-methyldisiloxane) methane, 2-bis (1-methyldisiloxane) propane, hexamethoxydisiloxane, 1,3, 5-trisiloxane-2, 4, 6-trimethyl, octamethylcyclotetrasiloxane. 1,3,5,7, 9-pentamethylcyclopentasiloxane, 1,3,5, 7-tetrasiloxane-2, 6-dioxo-4, 8-dimethyl, hexamethylcyclotrisiloxane, and combinations thereof.

Referring to fig. 3, a first mask layer 409 may be formed on the anti-reflective coating 407. The first mask layer 409 may be a photoresist layer. The first mask layer 409 may have a pattern of a plurality of plug structures 201.

Referring to fig. 4, a plug etch process may be performed using the first mask layer 409 as a pattern guide (guide) to remove a portion of the anti-reflective coating layer 407, a portion of the third conductive material 405, a portion of the second conductive material 403, and a portion of the first conductive material 401. After the plug etch process, the anti-reflective coating 407 may be divided into a plurality of portions. The first layer of conductive material 401 may be transformed into a plurality of bottom conductive layers 203. The second layer of conductive material 403 may be transformed into a plurality of intermediate conductive layers 205. The third layer of conductive material 405 may be transformed into a plurality of top conductive layers 207.

In some embodiments, the plug etch process may be a multi-step etch process. For example, the plug etch process may include four etch stages that etch the anti-reflective coating 407, the third conductive material 405, the second conductive material 403, and the first conductive material 401, respectively. In some embodiments, the plug etch process may be an anisotropic (anistropic) etch process. In some embodiments, the plug etch process may include an anisotropic etch process and an isotropic (isotropic) etch process. For example, the plug etch process may be anisotropic when etching the anti-reflective coating 407 and isotropic when etching the second conductive material 403.

In some embodiments, during the second conductive material etch phase of the plug etch process, the ratio of the etch rate of the second conductive material 403 to the anti-reflective coating 407 may be in the range of about 100:1 to about 1.05:1, about 15:1 to about 2:1, or about 10:1 to about 2:1, or a salt thereof. In some embodiments, during the second conductive material etch phase of the plug etch process, the ratio of the etch rates of the second conductive material 403 to the third conductive material 405 may be between about 100:1 to about 1.05:1, about 15:1 to about 2:1, or about 10:1 to about 2:1, in the above range. In some embodiments, during the second conductive material etch phase of the plug etch process, the ratio of the etch rate of the second conductive material 403 to the first conductive material 401 may be between about 100:1 to about 1.05:1, about 15:1 to about 2:1, or about 10:1 to about 2:1, or a salt thereof. In some embodiments, the ratio of the etching rate of the second conductive material 403 to the bottom dielectric layer 301 in the second conductive material etching phase of the plug etch process may be in the range of about 100:1 to about 1.05:1, about 15:1 to about 2:1, or about 10:1 to about 2:1, or a salt thereof.

In some embodiments, the etchant for the second conductive material etch stage of the plug etch process may be, for example, chlorine and argon. The flow rate of the etchant may be approximately 200sccm for chlorine and 1000sccm for argon. The process temperature of the second conductive material etch stage of the plug etch process may be in a range of about 50 ℃ (degrees celsius) to about 200 ℃. The process pressure of the second conductive material etch stage of the plug etch process may be in a range of about 50 millitorr (Torr) to about 10 Torr (Torr). The process duration of the second conductive material etch phase of the plug etch process may be in a range of about 30 seconds to about 200 seconds. In some embodiments, the bottom dielectric layer 301 may serve as an etch stop layer for the plug etch process.

For simplicity, clarity and ease of description, only one bottom conductive layer 203, one middle conductive layer 205 and one top conductive layer 207 are depicted.

Referring to fig. 4, a width W1 of the bottom conductive layer 203 may be greater than a width W2 of the middle conductive layer 205. The width W2 of the middle conductive layer 205 may be less than the width W3 of the top conductive layer 207. The width W1 of bottom conductive layer 203 and the width W3 of top conductive layer 207 may be substantially the same. In other words, the bottom conductive layer 203, the middle conductive layer 205, and the top conductive layer 207 may collectively define an I-shaped cross-sectional profile.

In some embodiments, thickness T1 of bottom conductive layer 203 and thickness T2 of top conductive layer 207 may be substantially the same. In some embodiments, thickness T1 of bottom conductive layer 203 and thickness T2 of top conductive layer 207 may be different. For example, thickness T1 of bottom conductive layer 203 may be greater than thickness T2 of top conductive layer 207.

Referring to fig. 5, a plurality of insulating capping layers 209 may be selectively and respectively formed on sidewalls 205S of the plurality of intermediate conductive layers 205 and completely cover the sidewalls 205S. For simplicity, clarity and ease of description, only one insulating cap layer 209 is depicted. A thermal oxidation process may be performed on the intermediate semiconductor element shown in fig. 4, and an oxide layer (e.g., aluminum oxide) may be formed on the sidewalls 205S of the intermediate conductive layer 205 including aluminum. This oxide layer may be referred to as an insulating cap layer 209. The insulating cap layer 209 may prevent the intermediate conductive layer 205 from being contaminated or damaged in a subsequent semiconductor process. In addition, the insulating cap layer 209 may prevent metal ions in the intermediate conductive layer 205 from diffusing out to contaminate adjacent components, thus reducing shorting between adjacent conductive features.

In some embodiments, the width W1 and the total width W4 of the bottom conductive layer 203 (consisting of the width W2 of the middle conductive layer 205 and the thickness T3 of the insulating capping layer 209) may be substantially the same. The width W3 and the total width W4 of the top conductive layer 207 may be substantially the same. In other words, the surface consisting of the sidewall 203S of the bottom conductive layer 203, the sidewall 209S of the insulating capping layer 209, and the sidewall 207S of the top conductive layer 207 may be substantially vertical. It should be understood that in the description of the present disclosure, a surface is "substantially flat" if there is a horizontal plane from which the surface deviates by no more than three times the root mean square roughness of the surface.

In some embodiments, the ratio of the thickness T3 of the insulating cap layer 209 to the width W2 of the intermediate conductive layer 205 may be in the range of about 1:20 to about 1:2000, about 1: 50 to about 1: 1800, or about 1:200 to about 1: 1600.

Referring to fig. 1, 6 and 7, in step S13, a first dielectric layer 303 may be formed on the bottom dielectric layer 301.

Referring to fig. 6, the first dielectric layer 303 may be formed on the bottom dielectric layer 301 and completely cover the plurality of plug structures 201 and the anti-reflective coating 407. In other words, the first dielectric layer 303 may completely surround the plurality of plug structures 201. It will be appreciated that the intermediate conductive layer 205 is separated from the first dielectric layer 303 by an insulating capping layer 209. A planarization process, such as a Chemical Mechanical Polishing (CMP) process, may be performed until the top surface of the anti-reflective coating 407 is exposed to remove excess material and provide a substantially planar surface for subsequent process steps. In some embodiments, the first dielectric layer 303 can be formed by, for example, a porous dielectric material. In some embodiments, the first dielectric layer 303 can be formed by, for example, a porous low-k dielectric material, a porous polymeric material, an organic spin-on glass, or a combination thereof, but is not limited thereto. In some embodiments, the average diameter of the pores (not shown for clarity) of first dielectric layer 303 ranges from about 10 angstroms to about 200 angstroms, depending on the type of material of first dielectric layer 303.

Referring to fig. 7, an etch back process may be performed to lower the top surface 303TS of the first dielectric layer 303 to a vertical level VL1 between the top surface 207TS of the top conductive layer 207 and the bottom surface 207BS of the top conductive layer 207. The anti-reflective coating 407 may serve as a protection layer during the etch back process to prevent the underlying top conductive layer 207 from being damaged. In some embodiments, the etch-back process may be an anisotropic dry etch process. In some embodiments, the ratio of the etching rate of the first dielectric layer 303 to the anti-reflective coating 407 in the etch back process may be in a range of about 100:1 to about 1.05:1, about 15:1 to about 2:1, or about 10:1 to about 2:1, in the above range. In some embodiments, the ratio of the etch rate of the first dielectric layer 303 to the top conductive layer 207 in the etch back process may be in the range of about 100:1 to about 1.05:1, about 15:1 to about 2:1, or about 10:1 to about 2:1, in the above range.

Referring to fig. 1, 8 and 9, in step S15, a second dielectric layer 305 may be formed on the first dielectric layer 303, and a third dielectric layer 307 may be formed on the second dielectric layer 305.

Referring to fig. 8, the second dielectric layer 305 may be formed on the first dielectric layer 303 and completely cover the plurality of plug structures 201 and the anti-reflective coating 407. In some embodiments, the second dielectric layer 305 and the first dielectric layer 303 may be made of different materials. For example, the second dielectric layer 305 may be made of a material having a hardness greater than that of the first dielectric layer 303. In some embodiments, the second dielectric layer 305 may be formed by, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, or the like, or combinations thereof. The second dielectric layer 305 may be formed by a deposition process, such as a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or the like. A planarization process, such as a chemical mechanical polishing process, may be performed until the top surface 407TS of the anti-reflective coating 407 is exposed to remove excess material and provide a substantially planar surface for subsequent process steps. After the planarization process, the top surface 305TS of the second dielectric layer 305 is located on the vertical plane VL2, which is larger than the top surface 207TS of the top conductive layer 207.

Referring to fig. 9, a third dielectric layer 307 may be formed on the second dielectric layer 305 and cover the anti-reflective coating 407. The third dielectric layer 307 may be formed by, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-on low-k dielectric layer, chemical vapor deposition low-k dielectric layer, or combinations thereof. In some embodiments, the third dielectric layer 307 may comprise a self-planarizing material, such as spin-on glass or a spin-on low-k dielectric material, such as SiLK ^TM . The use of a self-planarizing dielectric material may avoid performing a subsequent planarization step. In some embodiments, the third dielectric layer 307 may be formed by a deposition process, for example, including a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an evaporation process, or a spin-on process.

Referring to fig. 1, 10 and 11, in step S17, a plurality of contacts 105 may be formed in the third dielectric layer 307 and electrically connected to the plurality of plug structures 201.

Referring to fig. 10, an opening etch process may be performed to remove a portion of the third dielectric layer 307 and completely remove the anti-reflective coating 407. After the opening etching process, a plurality of contact holes 103 may be formed, and the plurality of top conductive layers 207 may be exposed through the plurality of contact holes 103. In the opening etching process, the ratio of the etching rates of the third dielectric layer 307 and the top conductive layer 207 may be in a range of about 100:1 to about 1.05:1, about 15:1 to about 2:1, or about 10:1 to about 2:1, in the above range. In the opening etch process, the ratio of the etch rate of the anti-reflective coating 407 to the top conductive layer 207 may be in the range of about 100:1 to about 1.05:1, about 15:1 to about 2:1, or about 10:1 to about 2:1, in the above range.

For simplicity, clarity and ease of description, only one contact hole 103 is depicted.

Referring to fig. 10, the contact hole 103 may include a lower portion 103L and an upper portion 103U. The lower portion 103L of the contact hole 103 may be located where the anti-reflective coating 407 is occupied. The upper portion 103U may be disposed along the third dielectric layer 307 and communicate with the lower portion 103L. The width W5 of the lower portion 103L may be substantially the same as the width W3 of the top conductive layer 207. The width W6 of the upper portion 103U may be greater than the width W5 of the lower portion 103L.

Referring to fig. 11, a plurality of contacts 105 may be respectively and correspondingly formed in the plurality of contact holes 103. A plurality of contacts 105 may be electrically connected with a plurality of plug structures 201. The plurality of contacts 105 may be fabricated using techniques such as, for example, polysilicon, poly-germanium, poly-silicon-germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. The plurality of contacts 105 may be formed by, for example, a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, or the like. A planarization process, such as a chemical mechanical polishing process, may be performed until the top surface of the third dielectric layer 307 is exposed to remove excess material and provide a substantially planar surface for subsequent process steps.

For simplicity, clarity and ease of description, only one contact 105 is depicted. The contacts 105 may include a lower portion 105L and an upper portion 105U. A lower portion 105L of contact 105 may be formed on top conductive layer 207 and surrounded by a second dielectric layer 305. An upper portion 105U of contact 105 may be formed on a lower portion 105L of contact 105 and surrounded by a third dielectric layer 307. Since the profile of the contact 105 is determined by the contact hole 103, a lower portion 105L of the contact 105 may have the same width W5 as the lower portion 103L of the contact hole 103, and an upper portion 105U of the contact 105 may have the same width W6 as the upper portion 103U of the contact hole 103. In some embodiments, the width W5 of the lower portion 105L may be substantially the same as the width W3 of the top conductive layer 207. The width W6 of the upper portion 105U may be greater than the width W5 of the lower portion 105L.

Fig. 12 to 15 are cross-sectional views illustrating a manufacturing flow of a semiconductor element 1B according to another embodiment of the present disclosure.

Referring to fig. 12, an intermediate semiconductor device may be fabricated by a procedure similar to that illustrated in fig. 2 through 5, and a description thereof will not be repeated. A layer of energy-removable material 411 may be formed on the bottom dielectric layer 301 and around the plurality of plug structures 201. The energy-removable material 411 may include, for example, a material that thermally decomposes, a photon decomposing material, an electron beam decomposing material, or a combination thereof. For example, the energy-removable material 411 may include a base material and a decomposable porogen material and may be sacrificed when exposed to an energy source. The base material may include a silyl-based material. The decomposable porogen material may comprise a porogen organic compound that provides porosity to the base material of the energy removable material 411.

Referring to fig. 13, the layer of energy-removable material 411 may be recessed in a similar procedure as shown in fig. 7, the description of which is not repeated here. The second dielectric layer 305 may be formed on the energy-removable material layer 411 by a process similar to that shown in fig. 8, and the description thereof will not be repeated here. The second dielectric layer 305 may serve as a capping layer for the energy removable material layer 411.

Referring to fig. 14, the intermediate semiconductor element in fig. 13 may be subjected to energy treatment by applying an energy source thereto. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, the temperature of the energy treatment may be in the range of about 800 ℃ to about 900 ℃. When light is used as the energy source, ultraviolet rays may be used. The energy treatment can remove the decomposable porogen material from the energy removable material to create voids (pores) while the base material remains in place. After the energy treatment, the layer 411 of energy-removable material may be transformed into the first dielectric layer 303.

In some embodiments, the first dielectric layer 303 may include a framework and a plurality of voids disposed between the framework. The plurality of voids may be interconnected and may be filled with air. The backbone may include, for example, silica, low-k materials, or silyl ethers. The first dielectric layer 303 may have a porosity of 25% to 100%. It should be understood that when the porosity is 100%, meaning that the first porous layer 415 includes only an empty space, the first dielectric layer 303 may be regarded as an air gap. In some embodiments, the porosity of the first dielectric layer 303 may be in the range of 45% and 95%. The plurality of voids of the first dielectric layer 303 may be filled with air. Thus, the dielectric constant of the first dielectric layer 303 may be significantly lower than that of a layer of, for example, silicon oxide, which is a fabrication technique. Therefore, the first dielectric layer 303 can significantly reduce the parasitic capacitance between the plurality of plug structures 201. That is, the first dielectric layer 303 may significantly mitigate the effect of interference between electrical signals induced or applied to the plurality of plug structures 201.

Referring to fig. 15, the third dielectric layer 307 and the plurality of contacts 105 may be formed using a procedure similar to that shown in fig. 9 to 11, and a description thereof will not be repeated.

Due to the design of the semiconductor device of the present disclosure, the insulating capping layer 209 may prevent metal ions in the intermediate conductive layer 205 from diffusing out to contaminate adjacent devices (e.g., the first dielectric layer 303), and thus may reduce short circuits between adjacent conductive features. Therefore, the reliability and the electrical characteristic performance of the semiconductor element 1A can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the disclosure of the present disclosure.

Claims

1. A semiconductor component, comprising:

a substrate;

a plug structure comprising:

a bottom conductive layer disposed on the substrate;

an intermediate conductive layer disposed on the bottom conductive layer;

a top conductive layer disposed on the middle conductive layer; and

an insulating cover layer covering a sidewall of the middle conductive layer and disposed between the bottom conductive layer and the top conductive layer; and

a first dielectric layer disposed on the substrate and surrounding the plug structure;

wherein a width of the bottom conductive layer is greater than a width of the middle conductive layer;

wherein a width of the top conductive layer is greater than the width of the middle conductive layer.

2. The semiconductor device as defined in claim 1, wherein the width of the bottom conductive layer is substantially the same as a total width consisting of the width of the middle conductive layer and a thickness of the insulating cover layer.

3. The semiconductor device of claim 1, wherein a sidewall of the top conductive layer, a sidewall of the insulating cap layer, and a sidewall of the bottom conductive layer are substantially coplanar.

4. The semiconductor device of claim 3, wherein a top surface of the first dielectric layer is located at about a vertical level between a top surface of the top conductive layer and a bottom surface of the top conductive layer.

5. The semiconductor device as defined in claim 4, further comprising a bottom dielectric layer disposed between the first dielectric layer and the substrate.

6. The semiconductor device of claim 5, further comprising a second dielectric layer disposed on said first dielectric layer, wherein a top surface of said second dielectric layer is at a vertical level greater than said top surface of said top conductive layer.

7. The semiconductor device of claim 6, further comprising a contact disposed on and electrically connected to the top conductive layer.

8. The semiconductor device of claim 7, wherein the contact comprises a lower portion disposed on the top conductive layer and an upper portion disposed on the lower portion, and a width of the upper portion is greater than a width of the lower portion.

9. The semiconductor device as defined in claim 8, further comprising a third dielectric layer disposed on the second dielectric layer and surrounding the contact.

10. The semiconductor device as defined in claim 9, wherein a thickness of the bottom conductive layer is substantially the same as a thickness of the top conductive layer.

11. The semiconductor device as defined in claim 9, wherein a thickness of the bottom conductive layer is greater than a thickness of the top conductive layer.

12. The semiconductor device of claim 9, wherein the first dielectric layer comprises a porous dielectric material, the middle conductive layer comprises aluminum and copper, the bottom conductive layer and the top conductive layer comprise titanium and titanium nitride, and the insulating cap layer comprises aluminum oxide.

13. The semiconductor device of claim 1, wherein a ratio of a thickness of the insulating capping layer to a width of the intermediate conductive layer is between about 1:20 to about 1:2000, in the range of the said catalyst.

14. A method for manufacturing a semiconductor device includes:

providing a substrate;

sequentially forming a layer of a first conductive material, a layer of a second conductive material, a layer of a third conductive material and an anti-reflection coating on the substrate;

performing a plug etch process to convert the layer of the first conductive material into a bottom conductive layer on the substrate, the layer of the second conductive material into a middle conductive layer on the bottom conductive layer, and the layer of the third conductive material into a top conductive layer on the middle conductive layer;

selectively forming an insulating cover layer on a sidewall of the middle conductive layer, wherein the bottom conductive layer, the middle conductive layer, the top conductive layer and the insulating cover layer together configure a plug structure; and

forming a first dielectric layer on the substrate and surrounding the plug structure;

wherein a width of the bottom conductive layer is greater than a width of the middle conductive layer, and a width of the top conductive layer is greater than the width of the middle conductive layer.

15. The method according to claim 14, wherein the first dielectric layer comprises a porous dielectric material, the middle conductive layer comprises aluminum and copper, the bottom conductive layer and the top conductive layer comprise titanium and titanium nitride, and the insulating cap layer comprises aluminum oxide.

16. The method of claim 15, further comprising forming a bottom dielectric layer between the first dielectric layer and the substrate.

17. The method according to claim 16, further comprising performing an etch back process to lower a top surface of the first dielectric layer to a vertical level between a top surface of the top conductive layer and a bottom surface of the top conductive layer.

18. The manufacturing method of a semiconductor element according to claim 17, further comprising:

forming a second dielectric layer on the first dielectric layer and surrounding the top conductive layer and the anti-reflective coating;

forming a third dielectric layer on the second dielectric layer and the anti-reflective coating;

forming a contact hole by removing a portion of the anti-reflective coating layer and the third dielectric layer, wherein the top conductive layer is exposed through the contact hole; and

a contact is formed in the contact hole to electrically connect with the top conductive layer.

19. The method according to claim 18, wherein a hardness of the second dielectric layer is greater than a hardness of the first dielectric layer.

20. The method according to claim 19, wherein the bottom dielectric layer comprises silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-on low dielectric constant (low-k) dielectric layers, chemical vapor deposited low dielectric constant dielectric layers, or combinations thereof.