CN115955837A - Preparation method of semiconductor structure and semiconductor structure - Google Patents

Abstract

The embodiment of the disclosure provides a preparation method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a substrate, wherein the substrate comprises an array area and a peripheral area surrounding the array area, and the array area comprises an active area; forming a mask layer on a substrate; forming a contact hole pattern on the part of the mask layer positioned in the array area; etching the substrate based on the contact hole pattern, and forming a contact hole in the array region of the substrate, wherein the contact hole exposes at least part of the active region; forming a first conductive layer in the contact hole to connect the first conductive layer with the active region; forming a second conductive layer on both the peripheral region and the array region where the first conductive layer is formed in the contact hole; and removing the second conductive layer in the array area to expose the first conductive layer. The method of the embodiment of the disclosure can simplify the preparation process, reduce the defects of the preparation process on the semiconductor structure, improve the yield of the semiconductor structure and reduce the cost.

Description

Preparation method of semiconductor structure and semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells and has a Memory function. With the continuous improvement of the performance requirements of the DRAM, the process is more complicated in the process of preparing the DRAM, the DRAM is easy to generate defects in the preparation process, the yield of the DRAM is reduced, and the cost is increased.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure, and thus it may include information that does not constitute related art known to those of ordinary skill in the art.

Disclosure of Invention

The embodiment of the disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, which can simplify a preparation process, reduce defects of the semiconductor structure caused by the preparation process, improve the yield of the semiconductor structure and reduce the cost.

The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises an array region and a peripheral region surrounding the array region, and the array region comprises an active region; forming a mask layer on the substrate; forming a contact hole pattern on the part of the mask layer, which is positioned in the array area, etching the substrate based on the contact hole pattern, and forming a contact hole in the array area of the substrate, wherein at least part of the active area is exposed through the contact hole; forming a first conductive layer in the contact hole, so that the first conductive layer is connected with the active region; forming a second conductive layer on both the peripheral region and the array region in which the first conductive layer is formed in the contact hole; and removing the second conductive layer in the array area to expose the first conductive layer.

According to some exemplary embodiments of the present disclosure, forming a contact hole pattern at a portion of the mask layer located at the array region includes: forming a mask layer on the mask layer; forming the contact hole pattern at a portion of the mask layer located at the array region; and transferring the contact hole pattern into the mask layer.

According to some exemplary embodiments of the present disclosure, forming a first conductive layer in the contact hole to connect the first conductive layer with the active region includes: forming a first conductive layer in the array region and the peripheral region, and filling the contact holes with the first conductive layer; and removing the first conducting layer on the surfaces of the peripheral area and the array area, and reserving the first conducting layer in the contact hole.

According to some exemplary embodiments of the present disclosure, after forming the first conductive layer in the array region and the peripheral region, the method further includes: and carrying out ion doping on the first conducting layer by adopting an ion implantation process.

According to some exemplary embodiments of the present disclosure, the element doping the first conductive layer is at least one of boron, phosphorus, arsenic, and antimony.

According to some exemplary embodiments of the present disclosure, the material of the first conductive layer is doped polysilicon.

According to some exemplary embodiments of the present disclosure, removing the second conductive layer located in the array region to expose the first conductive layer includes: forming an etch barrier layer on the second conductive layer located in the peripheral region; removing the second conductive layer in the array region; and removing the etching barrier layer to expose the second conductive layer in the peripheral area.

According to some exemplary embodiments of the present disclosure, before forming a mask layer on the substrate, the method further includes: an etch stop layer is formed in the array region.

According to some exemplary embodiments of the present disclosure, before forming the mask layer on the substrate, further comprising: forming a gate oxide layer on the etch stop layer and the peripheral region; and forming a mask layer on the substrate, wherein the forming of the mask layer on the gate oxide layer is included.

According to some exemplary embodiments of the present disclosure, forming a second conductive layer on each of the peripheral region and the array region having the first conductive layer formed in the contact hole includes: forming a second conductive layer on the gate oxide layer; removing the second conductive layer in the array region to expose the first conductive layer, including: and removing the second conducting layer and the gate oxide layer in the array area by adopting an etching process to expose the etching stop layer and the first conducting layer in the contact hole.

According to some example embodiments of the present disclosure, the gate oxide layer is at least one of silicon oxide and silicon oxynitride.

According to some exemplary embodiments of the present disclosure, the material of the second conductive layer is at least one of doped polysilicon, metal and conductive metal oxide.

According to some exemplary embodiments of the present disclosure, the material of the mask layer is at least one of polysilicon and carbon.

According to some exemplary embodiments of the present disclosure, the first conductive layer in the contact hole is a bit line contact or a capacitor contact; the second conductive layer located in the peripheral region is a gate.

The embodiment of the present disclosure further provides a semiconductor structure, which is prepared by the method described in any one of the above embodiments.

According to the technical scheme, the preparation method of the semiconductor structure and the semiconductor structure have at least one of the following advantages and positive effects:

in the embodiment of the disclosure, the contact hole is formed first, the first conductive layer is formed in the contact hole, and then the second conductive layer is formed in the peripheral region.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor structure in accordance with some embodiments of the present disclosure;

fig. 2 is a schematic diagram of a semiconductor structure showing the formation of a gate oxide layer on a substrate according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram illustrating the formation of a mask layer on a substrate according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram illustrating the formation of a mask layer over a mask layer in accordance with some embodiments of the present disclosure;

FIG. 5 is a schematic diagram illustrating the formation of contact holes in an array region according to some embodiments of the present disclosure;

fig. 6 is a schematic diagram illustrating the formation of a first conductive layer according to some embodiments of the present disclosure;

FIG. 7 is a schematic diagram illustrating the removal of a first conductive layer on a surface of a substrate according to some embodiments of the present disclosure;

fig. 8 is a schematic diagram illustrating the formation of a second conductive layer in accordance with some embodiments of the present disclosure;

fig. 9 is a schematic diagram illustrating the formation of an etch stop layer on the second conductive layer in the peripheral region according to some embodiments of the present disclosure;

fig. 10 is a schematic diagram illustrating the removal of the second conductive layer, the gate oxide layer and the etch stop layer in the array region and in the peripheral region according to some embodiments of the disclosure.

Description of reference numerals:

1. a substrate; 2. an etch stop layer; 3. a gate oxide layer; 4. a mask layer; 5. a mask layer; 6. a first conductive layer; 7. a second conductive layer; 8. etching the barrier layer; 9. a word line structure; 10. shallow trench isolation; A. an array region; a. an active region; B. a peripheral region; s, contact hole patterns; H. and (6) contacting the holes.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not numerical limitations of their objects.

The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

In addition, in the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a capacitor. The voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage.

With the development of technology, the performance requirements of the dynamic random access memory are higher and higher, and meanwhile, the cost is required to be reduced as much as possible to improve the market competitiveness. In a conventional manufacturing process, especially in a front-end manufacturing process of a DRAM, a conductive layer is usually formed in a peripheral region after bit line contacts are formed in an array region, and since semiconductor structures of the array region and the peripheral region are different, it is necessary to make a certain layer structure of one region as little as possible influence a layer already formed in the other region, which makes the conventional process cumbersome, for example, forming a conductive layer on the array region and the peripheral region of a substrate of a semiconductor structure, forming an oxidation protection layer on the conductive layer, then removing the conductive layer and the oxidation protection layer located in the array region, forming contact holes on the substrate of the array region, forming bit line contacts in the contact holes, then removing the oxidation protection layer located on the conductive layer located in the peripheral region, exposing the conductive layer, and connecting the conductive layer to a peripheral circuit. In the process, an oxidation protection layer needs to be formed and then the oxidation protection layer located in the peripheral region needs to be removed separately, the process is complex, and due to excessive steps, defects are easily generated due to the influence on the formed layer structure.

Based on this, the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. As shown in fig. 1, a flow chart of a method of making an embodiment of the present disclosure is shown. Fig. 2 to 10 respectively show schematic views of a semiconductor structure during fabrication. As shown in fig. 1, the preparation method of the embodiment of the present disclosure includes the steps of: s110 to S170.

S110: a substrate 1 is provided, the substrate 1 including an array region a and a peripheral region B surrounding the array region a, the array region a including an active region a.

As shown in fig. 2, the base 1 includes a semiconductor substrate, shallow trench isolations (Shallow trench isolations) are formed on the semiconductor substrate, and active regions a are disposed between the Shallow trench isolations 10. The shallow trench isolation 10 is used for isolation and may be made of silicon nitride or silicon dioxide. The substrate 1 includes an array region a and a peripheral region B surrounding the array region a. The array region a is used for forming main devices of the semiconductor structure, such as transistors, capacitors, bit lines, word lines, etc., and the peripheral region B is used for forming peripheral circuits.

In the embodiment of the present disclosure, a buried word line structure 9 is disposed in the semiconductor substrate, and the word line structure 9 is connected to the active region a. The word line structure 9 may include a high-k dielectric layer, a polysilicon layer, a work function layer, a word line metal layer, and the like.

In some embodiments, the material of the semiconductor substrate may be silicon, silicon carbide, silicon-on-insulator-germanium, or germanium-on-insulator, etc. The semiconductor substrate can also be implanted with certain doping particles according to design requirements to change electrical parameters.

S120: a mask layer 4 is formed on a substrate 1.

In some embodiments, as shown in fig. 3, a mask layer 4 may be formed on the substrate 1 using a deposition process. The mask layer 4 may be a hard mask layer, and the material of the mask layer 4 may be at least one of polysilicon and carbon.

In some embodiments, before forming the mask layer 4, as shown in fig. 1, the method further comprises: an etch stop layer 2 is formed in the array region a. In the embodiment of the present disclosure, after the embedded word line structure 9 is formed, the etching stop layer 2 is formed in the word line trench located above the embedded word line structure 9 and on the surface of the substrate 1 by using a deposition process, so as to insulate and isolate the embedded word line structure 9, and play a role of stopping etching in a subsequent etching process, thereby preventing the surface of the substrate 1 from being damaged by over-etching. The etch stop layer 2 located at the peripheral region B is removed using an etching process such that the etch stop layer 2 is formed only at the array region a.

In some embodiments, the material of the etch stop layer 2 may be silicon nitride or silicon oxynitride, which is not limited herein.

In some embodiments, as shown in fig. 1, before forming the mask layer 4 on the substrate 1, the method further comprises: forming a gate oxide layer 3 on the etch stop layer 2 and the peripheral region B; forming the mask layer 4 on the substrate 1 includes: a mask layer 4 is formed on the gate oxide layer 3. Specifically, after the etch stop layer 2 is formed at the array region a, a gate oxide layer 3 may be formed at the array region a and the peripheral region B of the substrate 1 using a deposition process, and then a mask layer 4 may be formed on the gate oxide layer 3. The gate oxide layer 3 is mainly used as an oxide layer of a gate electrode to be subsequently formed in the peripheral region B.

In some embodiments, the material of the gate oxide layer 3 is at least one of silicon oxide and silicon oxynitride. In some embodiments, the gate oxide layer 3 and the etch stop layer 2 are made of different materials, and in the subsequent process, the gate oxide layer 3 in the array region a may be removed by using an etching process, and the two have different etching selection ratios, and on the premise of satisfying the respective performances, the difference between the etching selection ratios of the two is preferably larger, and thus the two materials may be different. For example, the gate oxide layer 3 is made of silicon dioxide, and the etch stop layer 2 is made of silicon nitride.

S130: a contact hole pattern S is formed in a portion of the mask layer 4 located in the array region a.

As shown in fig. 4, forming the contact hole pattern S on the mask layer 4 at the array region a may include the following: a1 to A3.

A1: a mask layer 5 is formed on the mask layer 4.

Specifically, the mask layer 5 may be formed on the mask layer 4 of the array region a and the peripheral region B using a deposition process. In some embodiments, the mask layer 5 may be a photoresist.

A2: a contact hole pattern S is formed in a portion of the mask layer 5 located in the array region a.

In some embodiments, a contact hole pattern may be formed on the mask layer 5 above the array region a, and then the contact hole pattern S may be transferred into the mask layer 5 through exposure and development.

In some embodiments, the contact hole pattern S may be a bit line contact hole pattern or a capacitor contact hole pattern, and a person skilled in the art may set the position, number, and shape of the contact hole pattern S according to the formation position of the bit line contact or the capacitor contact.

A3: the contact hole pattern S is transferred into the mask layer 4.

Specifically, the mask layer 4 may be etched using an etching process based on the contact hole pattern S of the mask layer 5 to transfer the contact hole pattern S into the mask layer 4 so as to form the contact hole H.

After forming the contact hole pattern S in the mask layer 4, the mask layer 5 may be removed by an etching process or a Chemical Mechanical Polishing (CMP) process.

The etching process may be a dry etching process or a wet etching process. The dry etching process can be a plasma etching process, the etching gas adopted by the plasma etching process can be chlorine, and the etching degree can be controlled by controlling the consumption of the etching gas; the wet etching process can use concentrated sulfuric acid and hydrogen peroxide as an etchant, and the etching degree is controlled by adjusting the concentration of the etchant or the etching time.

S140: the substrate 1 is etched based on the contact hole pattern S to form contact holes H in the array region a of the substrate 1, the contact holes H exposing at least a portion of the active region a.

As shown in fig. 4, based on the contact hole pattern S of the mask layer 4, the array region a of the substrate 1 may be etched using an etching process to form contact holes H in the array region a of the substrate 1. The contact hole H exposes at least a portion of the active region a.

After the contact hole H is formed in the substrate 1, the mask layer 4 may be removed by an etching process or a chemical mechanical polishing process to expose the gate oxide layer 3.

The etching process may be a wet etching process, and when the mask layer 4 is a hard mask layer, especially when the material is polysilicon, the etchant used in the wet etching process may be hydrofluoric acid (HF) and ammonium fluoride (NH) ₄ F) The mixed liquid completely removes the mask layer 4 by regulating and controlling the concentration, the dosage and the etching time of the etching agent, and does not damage the gate oxide layer 3 positioned below the mask layer 4. Of course, the adjustment can be performed by those skilled in the art according to the actual situation, and is not limited specifically here.

S150: a first conductive layer 6 is formed in the contact hole H such that the first conductive layer 6 is connected to the active region a.

In some embodiments, S150 may include the following: b1 to B2.

B1: a first conductive layer 6 is formed in the array region a and the peripheral region B, and the first conductive layer 6 fills the contact hole H.

A first conductive layer 6 may be deposited in the contact hole H and on the surface of the exposed gate oxide layer 3 using a deposition process. The first conductive layer 6 located at the contact hole H may be formed as a bit line contact or a capacitive contact, and the first conductive layer 6 has a good conductive property to enable electrical connection of the active region a with a bit line or a capacitor.

In some embodiments, the material of the first conductive layer 6 may be doped polysilicon to improve the conductivity of the first conductive layer 6.

In some embodiments, after forming the first conductive layer 6 in the array region a and the peripheral region B, the method may further include: the first conductive layer 6 is ion-doped using an ion implantation process.

An ion implantation process is understood to be a process in which doped ions are introduced into a solid, which is a material modification. In the ion implantation, in a vacuum system, dopant ions accelerated are implanted into a solid material, thereby forming the material of the implanted region into a dopant material. In the embodiment of the present disclosure, when the first conductive layer 6 is not doped, the material of the first conductive layer 6 may be undoped polysilicon. The first conductive layer 6 is ion implanted by an ion implantation process, so that undoped polysilicon is formed into doped polysilicon, and the conductivity of the first conductive layer 6 is improved.

In some embodiments, the element doping the first conductive layer 6 is at least one of boron, phosphorus, arsenic, and antimony.

The first conductive layer 6 is doped with the above elements, so that the conductivity of the first conductive layer 6 is improved, a bit line contact or a capacitor contact formed by the first conductive layer 6 has better conductivity, and the electrical performance of the semiconductor structure is improved.

B2: the first conductive layer 6 on the surfaces of the peripheral area B and the array area a is removed, and the first conductive layer 6 remains in the contact hole H.

As shown in fig. 7, the first conductive layer 6 on the surface of the gate oxide layer 3 may be removed by an etching process or a chemical mechanical polishing process to expose the gate oxide layer 3 and the first conductive layer 6 in the contact hole H, so as to form a bit line contact or a capacitor contact in the contact hole H.

S160: a second conductive layer 7 is formed on the peripheral region B and the array region a having the first conductive layer 6 formed in the contact hole H.

As shown in fig. 8, S160 may include: a second conductive layer 7 is formed on the gate oxide layer 3. That is, after forming the first conductive layer 6 in the contact hole H, the second conductive layer 7 may be formed on the surface of the gate oxide layer 3 using a deposition process. The second conductive layer 7 is used to form a gate electrode of the peripheral region B, so that the second conductive layer 7 of the peripheral region B is finally required to be remained, and the second conductive layer 7 located in the array region a is removed.

In some embodiments, the material of the second conductive layer 7 is at least one of doped polysilicon, metal and conductive metal oxide. The second conductive layer 7 is made of the above materials, so that the second conductive layer 7 has good conductivity as a gate of the peripheral region B.

S170: the second conductive layer 7 in the array region a is removed to expose the first conductive layer 6.

In some embodiments, S170 may include the following: c1 to C3.

C1: an etch stopper layer 8 is formed on the second conductive layer 7 located at the peripheral region B.

Specifically, as shown in fig. 9, an etch barrier layer 8 may be formed on the second conductive layer 7 located in the array region a and the peripheral region B using a deposition process, and then the etch barrier layer 8 located in the array region a is removed, leaving the etch barrier layer 8 located in the peripheral region B to cover the second conductive layer 7 located in the peripheral region B.

C2: the second conductive layer 7 at the array region a is removed.

In some embodiments, as shown in fig. 10, specifically, an etching process is used to remove the second conductive layer 7 and the gate oxide layer 3 located in the array region a, exposing the etch stop layer 2 and the first conductive layer 6 located in the contact hole H. In some embodiments, the first etching process may be used to remove the second conductive layer 7, the etchant in the first etching process can only etch the second conductive layer 7, and then the second etching process is used to etch the gate oxide layer 3 in the array region a to the etching stop layer 2, and the etchant in the second etching process can only etch the gate oxide layer 3, so that the second conductive layer 7 and the gate oxide layer 3 in the array region a can be more completely removed through two etching processes, thereby ensuring the uniformity of the surface of the etching stop layer 2, so as to form other layer structures in the subsequent processes, and reduce the formation of defects. In other embodiments, the second conductive layer 7 and the gate oxide layer 3 may be directly removed to the etching stop layer 2 by using a single etching process to expose the first conductive layer 6 in the contact hole H, and the etchant of the single etching process can etch both the second conductive layer 7 and the gate oxide layer 3, so that the process can be simplified and the cost can be reduced.

In any of the above etching methods, the etching stop layer 2 and the gate oxide layer 3 are made of different materials, for example, the etching stop layer 2 is made of silicon nitride, the gate oxide layer 3 is made of silicon dioxide, and the etching selectivity of the selected etchant to the etching stop layer and the etching selectivity to the gate oxide layer are different. In addition, the amount of etching can be controlled by controlling the amount of etchant and the etching time to avoid over-etching the first conductive layer 6 in the contact hole H.

Because the second conductive layer 7 and the gate oxide 3 in the array area a are removed by using an etching process, and the etching barrier layer 8 is not etched in the etching process, the material of the etching barrier layer 8 is different from the material of the second conductive layer 7 and the material of the gate oxide 3, that is, the etching selection ratio of the etching barrier layer to the second conductive layer 7 and the gate oxide 3 is different, and in each etching, the etching selection ratio of the etchant to the second conductive layer 7 and the gate oxide 3 is larger. In one embodiment, the second conductive layer 7 is made of polysilicon (undoped), the gate oxide layer 3 is made of silicon dioxide, and the etch stop layer 8 is made of photoresist.

C3: the etch stop layer 8 is removed to expose the second conductive layer 7 in the peripheral region B.

In some embodiments, as shown in fig. 10, the etch barrier layer 8 may be removed using an etching process to expose the second conductive layer 7 located in the peripheral region B. The exposed second conductive layer 7 may serve as a gate of the peripheral region B to be connected to a peripheral circuit.

The etching process may be a dry etching process, such as a plasma etching process, which enables a directional removal of the etch stop layer 8 located on the second conductive layer 7 without damaging the other layer structures.

In other embodiments, the specific implementation methods of S150 and S160 are different from those of S150 and S160 in the above embodiments.

S150: a first conductive layer 6 is formed in the contact hole H such that the first conductive layer 6 is connected to the active region a. Specifically, S150 may include the following: d1 to D4.

D1: a first conductive layer 6 is formed in the array region a and the peripheral region B, and the first conductive layer 6 fills the contact hole H.

The material of the first conductive layer 6 may be polysilicon, that is, undoped polysilicon. As shown in fig. 6, a first conductive layer 6 may be deposited in the contact hole H and on the surface of the exposed gate oxide layer 3 using a deposition process.

D2: and forming a hard mask layer on the first conductive layer 6 positioned in the peripheral area B, etching the first conductive layer 6 and the gate oxide layer 3 positioned in the array area A, and reserving and exposing the first conductive layer 6 positioned in the contact hole H. Specifically, a hard mask layer may be formed on the first conductive layer 6 in the peripheral area B by using a deposition process, and the hard mask layer is used to cover the first conductive layer 6 in the peripheral area B when etching the first conductive layer 6 and the gate oxide 3 in the array area a, so as to prevent the first conductive layer 6 from being etched.

D3: the first conductive layer 6 in the contact hole H is ion-doped.

Specifically, the first conductive layer 6 in the contact hole H may be doped by an ion implantation process, wherein the doped element may be at least one of boron, phosphorus, arsenic, and antimony. The first conductive layer 6 in the contact hole H is doped, so that the conductivity of the first conductive layer 6 can be improved, bit line contact or capacitor contact formed by the first conductive layer 6 has better conductivity, and the electrical performance of the semiconductor structure is improved.

S160: a second conductive layer 7 is formed in the peripheral region B.

When the first conductive layer 6 in the contact hole H is ion-doped, the first conductive layer 6 in the peripheral region B is not doped because the first conductive layer 6 in the peripheral region B is covered by the hard mask layer, and the material of the first conductive layer 6 is still undoped polysilicon.

The hard mask layer on the first conductive layer 6 in the peripheral region B is removed to expose the first conductive layer 6, and the exposed first conductive layer 6 is formed as a second conductive layer 7 in the embodiment of the present disclosure.

Specifically, the hard mask layer on the first conductive layer 6 in the peripheral region B may be removed using an etching process. Since the first conductive layer 6 is undoped polysilicon for connection with peripheral circuits, as shown in fig. 10, the first conductive layer 6 can be referred to as a second conductive layer 7 for convenience of distinction.

In the above embodiment, the second conductive layer 7 is not formed by a deposition process alone, thereby saving processes.

In some embodiments, the first conductive layer 6 in the contact hole H is a bit line contact, and the method of the embodiment of the disclosure further includes: forming a bit line structure (not shown in the figure), wherein the bit line structure includes a bit line metal layer and a bit line insulating layer, the bit line metal layer may be made of at least one of tungsten, titanium, nickel, aluminum, and platinum, and the bit line metal layer is in contact connection with the bit line to achieve conduction of the circuit. The bit line insulating layer may be made of silicon nitride and is disposed on the surface of the bit line metal layer.

In some embodiments, the first conductive layer 6 located in the contact hole H is a capacitor contact, and the method of the embodiment of the present disclosure further includes: forming a capacitor (not shown). Specifically, a stacked structure, which may be a silicon oxide layer and a silicon nitride layer alternately formed on the substrate 1, is formed on the substrate 1. And forming a capacitor hole in the laminated structure, wherein the silicon oxide layer can be used as a sacrificial layer and the silicon nitride layer can be used as a supporting layer in the process of forming the capacitor hole. A lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially deposited in the capacitor hole. A capacitor includes the lower electrode layer, the dielectric layer, and the upper electrode layer. The lower electrode layer is in contact connection with the capacitor to realize the conduction of the circuit. The lower electrode layer may be a columnar electrode or a cylindrical electrode. The material of the lower electrode layer and the upper electrode layer may include at least one of metal nitride and metal silicide species, such as titanium nitride, titanium silicide, nickel silicide, etc. The dielectric layer may be a high-K dielectric layer to improve capacitance per unit area of the capacitor, and the dielectric layer may be made of: zrOx, hfOx, zrTiOx, ruOx, sbOx, alOx, and the dielectric layer may also include a plurality of layers stacked by different materials, which is not particularly limited herein.

The deposition process used in the embodiments of the present disclosure may be chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and is not limited herein.

In a conventional process for manufacturing a semiconductor structure, a second conductive layer 7 is formed first, and an oxidation protection layer is formed on the second conductive layer 7, wherein the oxidation protection layer is located on the second conductive layer 7 in the whole process until the oxidation protection layer is removed independently in the end of the process. In the preparation method of the embodiment of the disclosure, the contact hole H is formed in the substrate 1, the first conductive layer 6 is formed in the contact hole H, and then the second conductive layer 7 is formed in the peripheral region B, and an oxidation protection layer in the conventional process is not formed to protect the second conductive layer 7 in the whole process, so that the process of removing the oxidation protection layer is not required to be added independently.

Embodiments of the present disclosure further provide a semiconductor structure, where the semiconductor structure is prepared by the preparation method in any of the above embodiments, and a specific preparation process of the semiconductor structure is not described herein again.

In some embodiments, the semiconductor structure includes a substrate 1, the substrate 1 including an array region a and a peripheral region B surrounding the array region a. The semiconductor structure further comprises a buried word line structure 9, a bit line contact and a bit line. The bit line contact is a first conductive layer 6 in the embodiment of the manufacturing method, and is located in the substrate 1, and the bit line is located on the substrate 1 and connected to the bit line contact.

In some embodiments, the semiconductor structure further comprises a capacitor, a capacitive contact. The capacitor contact is positioned in the substrate 1, the capacitor contact is the first conductive layer 6 in the preparation method embodiment, the capacitor is positioned on the substrate 1, and the capacitor comprises a lower electrode layer, a dielectric layer and an upper electrode layer, wherein the lower electrode layer is connected with the capacitor contact.

The semiconductor structure of the embodiment of the disclosure is prepared by the preparation method, so that the manufacturing cost is reduced, and the yield of the semiconductor structure is improved.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the present specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims (15)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate comprising an array region and a peripheral region surrounding the array region, the array region comprising an active region;

forming a mask layer on the substrate;

forming a contact hole pattern on the part of the mask layer, which is positioned in the array area;

etching the substrate based on the contact hole pattern, and forming a contact hole in the array region of the substrate, wherein the contact hole exposes at least part of the active region;

forming a first conductive layer in the contact hole, so that the first conductive layer is connected with the active region;

forming a second conductive layer on both the peripheral region and the array region in which the first conductive layer is formed in the contact hole;

and removing the second conductive layer in the array area to expose the first conductive layer.

2. The method of claim 1, wherein forming a contact hole pattern in a portion of the mask layer located in the array region comprises:

forming a mask layer on the mask layer;

forming the contact hole pattern at a portion of the mask layer located at the array region;

and transferring the contact hole pattern into the mask layer.

3. The method of claim 1, wherein forming a first conductive layer in the contact hole, connecting the first conductive layer with the active region, comprises:

forming a first conductive layer in the array region and the peripheral region, and filling the contact holes with the first conductive layer;

and removing the first conducting layer on the surfaces of the peripheral area and the array area, and reserving the first conducting layer in the contact hole.

4. The method of claim 3, further comprising, after forming the first conductive layer in the array region and the peripheral region:

and carrying out ion doping on the first conductive layer by adopting an ion implantation process.

5. The method of claim 4, wherein the element doping the first conductive layer is at least one of boron, phosphorus, arsenic, and antimony.

6. The method of claim 1, wherein the first conductive layer is doped polysilicon.

7. The method of claim 1, wherein removing the second conductive layer at the array region to expose the first conductive layer comprises:

forming an etch barrier layer on the second conductive layer located in the peripheral region;

removing the second conductive layer in the array region;

and removing the etching barrier layer to expose the second conductive layer in the peripheral area.

8. The method of claim 1, further comprising, prior to forming a mask layer on the substrate: an etch stop layer is formed in the array region.

9. The method of claim 8, further comprising, prior to forming a masking layer on the substrate: forming a gate oxide layer on the etch stop layer and the peripheral region;

and forming a mask layer on the substrate, wherein the forming of the mask layer on the gate oxide layer is included.

10. The method of claim 9, wherein forming a second conductive layer on both the peripheral region and the array region having the first conductive layer formed in the contact hole comprises: forming a second conductive layer on the gate oxide layer;

removing the second conductive layer in the array region to expose the first conductive layer, including: and removing the second conducting layer and the gate oxide layer in the array area by adopting an etching process to expose the etching stop layer and the first conducting layer in the contact hole.

11. The method of claim 10, wherein the gate oxide layer is at least one of silicon oxide and silicon oxynitride.

12. The method of claim 1, wherein the second conductive layer is at least one of doped polysilicon, metal and conductive metal oxide.

13. The method of claim 1, wherein the mask layer is made of at least one of polysilicon and carbon.

14. The method according to any one of claims 1 to 13,

the first conducting layer positioned in the contact hole is a bit line contact or a capacitor contact;

the second conductive layer located in the peripheral region is a gate.

15. A semiconductor structure, characterized in that it is produced by a method according to any one of claims 1 to 14.

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