CN115954358B - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
- Publication number
- CN115954358B CN115954358B CN202310239019.0A CN202310239019A CN115954358B CN 115954358 B CN115954358 B CN 115954358B CN 202310239019 A CN202310239019 A CN 202310239019A CN 115954358 B CN115954358 B CN 115954358B
- Authority
- CN
- China
- Prior art keywords
- region
- semiconductor
- forming
- schottky diode
- implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a manufacturing method of a semiconductor device and the semiconductor device, and belongs to the technical field of semiconductor manufacturing. The manufacturing method comprises the following steps: implanting a first type impurity into the semiconductor substrate to form a first region; implanting second-type impurities into the Schottky diode forming region to form a second region, wherein the second region is positioned at two sides of the central region; implanting first type impurities into a first region in the first semiconductor forming region and the second semiconductor forming region to form a third region degree; implanting first type impurities into the Schottky diode forming region and the second semiconductor forming region to form an implantation region and a high-concentration trench region; and forming silicide in the anode forming region of the Schottky diode forming region, wherein the work function of the material used in forming the silicide is higher than that of cobalt. The semiconductor device and the manufacturing method thereof can improve the performance of the semiconductor device.
Description
Technical Field
The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
In manufacturing a semiconductor device including a schottky diode (Schottky Barrier Diode, SBD), and forming a contact material for a gate, a source, or a drain of the semiconductor device, a nickel (Ni) silicide is used to form a schottky junction. Relative to cobalt disilicide (CoSi) 2 ) Or titanium disilicide (TiSi) 2 ) The nickel silicide can form a metal silicide film having the same film thickness using a small amount of silicon atoms, and the silicide film can be reduced in resistance without deteriorating the contact leakage current characteristics. In addition, schottky diodes are used in devices mounted with various power supplies, such as Display Driver ICs (DDICs) for small panels and touch and Display Driver integration (Touch and Display Driver Integration, TDDI), to prevent latch-up.
However, when a schottky diode is used in a semiconductor device and a material having a high work function such as nickel (Ni) is used as a material for silicide, the forward current of the schottky diode is reduced to 1/10 or less of that of cobalt. Also, when nickel (Ni) is used, in order to obtain the same forward current as when cobalt is used, the size of the semiconductor device needs to be increased, resulting in an increase in cost. In addition, schottky diodes are required to ensure a high breakdown voltage of, for example, 25V or more when they are used for latch-up prevention in devices mounted with various power supplies such as display driver chips of small panels and touch and display driver integration.
Disclosure of Invention
The present invention provides a semiconductor structure and a method for manufacturing the same, by which the semiconductor device and the method for manufacturing the same can suppress the increase in size and manufacturing cost of the semiconductor device and the decrease in performance of the semiconductor device.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a method of manufacturing a semiconductor device including a first semiconductor region, a second semiconductor region, and a schottky diode region provided on a semiconductor substrate, the method of manufacturing the semiconductor device including the steps of:
implanting a first type impurity into the semiconductor substrate to form a first region;
a second type impurity is injected into the upper surface of a central region in the first region, which is in the Schottky diode forming region and is positioned in the width direction orthogonal to the thickness direction of the semiconductor substrate, so as to form a second region, and the second region is positioned at two sides of the central region;
implanting first type impurities into a first region in the first semiconductor forming region and the second semiconductor forming region to form a third region, wherein the impurity concentration in the third region is greater than that in the first region;
Forming a photoresist layer which shields an upper surface of the first semiconductor forming region in which at least a trench region is formed, and a region other than a middle region of the central region, which is narrower than the central region in width and is provided inside edge portions on both sides of the central region, of the schottky diode forming region;
injecting first-type impurities into the Schottky diode forming region and the second semiconductor forming region by taking the photoresist layer as a mask, forming an injection region in the Schottky diode forming region, forming a high-concentration groove region in the second semiconductor forming region, and positioning the high-concentration groove region in a region covered by a grid electrode in the second semiconductor forming region; and
silicide is formed in the anode forming region of the schottky diode forming region to form a schottky junction, and a work function of a material used in forming the silicide is higher than that of cobalt.
In one embodiment of the present invention, the first type impurity is implanted at an impurity concentration of 1e when the first region is formed ＋16 /cm 3 ～4e ＋16 /cm 3 ；
The second type impurity is implanted to have an impurity concentration of 1e when the second region is formed ＋16 /cm 3 ～6e ＋16 /cm 3 ；
The impurity concentration of the first type impurity implanted in the formation of the third region is higher than 1e +17 /cm 3 ；
The dose of the first type impurity implanted in the formation of the high concentration trench region and the implantation region is 2e +12 ions/cm 2 ～1.5e +13 ions/cm 2 ；
The impurity concentration of the implantation region is 1e ＋18 /cm 3 ～1e ＋19 /cm 3 。
In one embodiment of the invention, the depth of the implanted region is within 100nm of the depth of the semiconductor substrate surface.
In one embodiment of the present invention, the photoresist layer in the schottky diode formation region has an opening portion thereon, and a distance from the opening portion to both side edge portions of the central region in a width direction is 0.1 μm to 0.3 μm when the implantation region is formed.
In one embodiment of the present invention, the first type of impurity implanted in forming the implant region and the high concentration trench region comprises arsenic.
In one embodiment of the present invention, the ion implantation energy is less than 50KeV when forming the implant region and the high concentration trench region.
In one embodiment of the present invention, the first region is formed at a depth ranging from 3 μm to 63 μm from the surface of the semiconductor substrate.
In one embodiment of the present invention, the second region is formed in a depth range of 1 μm to 3 μm from the surface of the semiconductor substrate.
The present invention also provides a semiconductor device including at least:
a schottky diode region formed on the semiconductor substrate;
a first semiconductor region formed on the semiconductor substrate, the first semiconductor region having a trench region into which a first type impurity is implanted, the trench region in the first semiconductor region being located in a region covered by a gate in the first semiconductor region; and
a second semiconductor region formed on the semiconductor substrate, the second semiconductor region having a trench region into which a first type impurity is implanted, the trench region in the second semiconductor region being located in a region covered by a gate in the second semiconductor region;
wherein the schottky diode region includes:
a silicide region using a material having a higher work function than cobalt;
an implantation region provided in the semiconductor substrate covered with the silicide region, the implantation region being located in a middle region of a central region in a width direction orthogonal to a thickness direction of the semiconductor substrate, the middle region being narrower in width than the central region and provided inside edge portions on both sides of the central region, the implantation region being implanted with a first type impurity, and the implantation region and the trench region in the second semiconductor region being formed simultaneously;
Wherein an impurity concentration of the implantation region is within ±10% of a difference between an impurity concentration of the trench region in the second semiconductor region and an impurity concentration of the trench region in the first semiconductor region.
In an embodiment of the invention, the second semiconductor region is disposed in a static random access memory.
In summary, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device, which can suppress the increase in size of the semiconductor device and suppress the decrease in performance of the semiconductor device without increasing the manufacturing cost.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a block diagram of the schottky diode region in fig. 1 according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view of a schottky diode region in a semiconductor device according to an embodiment of the present invention.
Fig. 4 is a diagram showing a process of forming a first N-type well region in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a diagram showing a process of forming a second N-type well region and a first P-type well region in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 6 is a diagram showing a process of forming an insulating portion and a gate oxide film in the method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 7 is a diagram showing a process of forming a third N-type well region in the method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 8 is a diagram showing a process of forming an implantation region and a high-concentration trench region in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 9 is a diagram showing a process of forming a gate electrode in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 10 is a diagram showing a process of forming a gate electrode and a source/drain portion in the method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 11 is a diagram showing a process of forming a silicide block in the method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 12 is a graph showing the relationship between the depth of the first semiconductor region and the second semiconductor region with respect to the surface of the semiconductor substrate and the impurity concentration of each region in the semiconductor device according to the embodiment of the present invention.
Fig. 13 is a graph showing a relationship between a depth of a schottky diode region of the semiconductor device according to an embodiment of the present invention with respect to a surface of a semiconductor substrate and an impurity concentration of each region.
Fig. 14 is a graph showing performance evaluation of a schottky diode region manufactured by the manufacturing method according to the embodiment of the present invention.
Description of the reference numerals
1. A schottky diode (SBD) region; 1b, schottky diode (SBD) forming region; 2. a first semiconductor region; 2b, a first semiconductor forming region; 3. a second semiconductor region; 3b, a second semiconductor forming region; 4. a third semiconductor region; 4b, a third semiconductor forming region; 10. a semiconductor substrate; 20. a silicide region; 22. an insulating part; 4. a silicide block; 100. a semiconductor device; an, anode; C. a central region; ch. A high concentration trench region; DL, DV, depletion layer region; HVGOX, LVGOX, gate oxide film; IF. Forward current; IR, leakage current; im, injection region; K. a cathode; LVG1, LVG2, HVG3, gate; NW1, first N-type well region; NW2, second N-type well region; NW3, third N-type well region; PR and photoresist layer; PW1, a first P-type well region; r, region; SD, source/drain portions; SJ, schottky junction; LVPex, LVP, diffusion region; n1, n2, n3, impurity concentration; x, distance.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a cross-sectional view of a semiconductor device 100. In the present embodiment, as shown in fig. 1, a direction orthogonal to the thickness (depth) direction H1 of the silicon substrate is defined as a width direction H2. The cross section shown in fig. 1 is continuously formed within a predetermined range in a direction orthogonal to the thickness direction H1 and the width direction H2.
As shown in fig. 1, a semiconductor apparatus 100 includes a plurality of semiconductor devices formed on a semiconductor substrate 10 that is a base material of a silicon substrate. In the present application, the semiconductor device 100 includes a schottky diode region 1 as a schottky diode, a first semiconductor region 2 and a second semiconductor region 3 as Low Voltage PMOS (LVPMOS), and a third semiconductor region 4 as High Voltage PMOS (HVPMOS).
Fig. 2 is a block diagram of the schottky diode region of fig. 1. As shown in fig. 2, when the schottky diode region 1 is provided in a display driving chip or a display driving integration for a small panel for latch-up prevention, it is required to have a breakdown voltage of, for example, 25V or more. In order to increase the breakdown voltage of the schottky diode to 25V or more, when a reverse voltage is applied to the schottky diode region 1, it is necessary to expand the lateral depletion layer region DL and the vertical depletion layer region DV generated in the first N-type well region NW1, which are regions where carriers move, respectively. Further, in order to expand the depletion layers in the depletion layer region DL and the depletion layer region DV, the impurity concentration in the region R including the depletion layer region DL and the depletion layer region DV needs to be sufficiently low relative to the impurity concentration in the vicinity of the anode An. That is, the breakdown voltage can be increased by decreasing the impurity concentration of the region R.
Fig. 3 is a cross-sectional view of a schottky diode region in the semiconductor device of the present embodiment. As shown in fig. 3, the schottky diode region 1 of the semiconductor device 100 includes a semiconductor substrate 10, a first N-type well region NW1, a second N-type well region NW2, a first P-type well region PW1, a central region C, an implantation region Im, a silicide region 20 as An anode An, a cathode K, an insulating portion 22, and a silicide block 24. In this application, for convenience of description, an edge of the first P-type well region PW1 near the central region C is assumed to be an edge portion PW1e.
As shown in fig. 3, the first N-type well region NW1 is a region where carriers move when the semiconductor device 100 operates. The first N-type well region NW1 is formed at a depth of 3 μm to 63 μm from the surface of the semiconductor substrate 10, and the impurity concentration in the first N-type well region NW1 is 1e ＋16 /cm 3 ～4e ＋16 /cm 3 . A schottky junction SJ is formed on the surface of the first N-type well region NW 1. The cathode K is a cathode electrode in the schottky diode region 1.
As shown in fig. 3, the second N-type well region NW2 may reduce the resistance of the anode-cathode current path, and the cathode K is disposed on the second N-type well region NW 2. The impurity concentration of the second N-type well region NW2 is higher than that of the first N-type well region NW1, and the impurity concentration of the second N-type well region NW2 is, for example, 1e +16 /cm 3 ～6e ＋16 /cm 3 . The second N-type well region NW2 is suppressed to be not lower than a desired breakdown voltage with respect to the junction withstand voltage of the first P-type well region PW 1. In addition, as shown in FIG. 3,the second N-type well region NW2 is symmetrically disposed on both sides of the implantation region Im (high concentration region) in the width direction H2 in the cross-sectional view of the schottky diode region 1.
As shown in fig. 3, the first P-type well region PW1 covers a lower surface of a portion of the silicide region 20 (schottky junction region). The first P-type well region PW1 is located on both sides of the central region C in the width direction H2. The first P-type well region PW1 is formed in a depth of 1 μm to 3 μm from the surface of the semiconductor substrate 10, and the impurity concentration of the first P-type well region PW1 is 1e ＋16 /cm 3 ～6e ＋16 /cm 3 . In addition, the P-type heavily doped region p+ may form a good ohmic contact between the silicide region 20 and the first P-type well region PW 1.
As shown in fig. 3, the central region C is provided in the schottky diode region 1. In the width direction H2, the central region C is located at the central position of the silicide region 20 (anode An). That is, the central region C is a region sandwiched by edge portions PW1e of the first P-type well region PW1, and is a region for forming an implantation region Im described later.
As shown in fig. 3, the implantation region Im is disposed in the central region C of the first N-type well region NW 1. The implantation region Im having a high concentration can be formed by doping the local central region C with an N-type impurity so that the impurity concentration in the local central region C becomes high. Among them, the N-type impurity is, for example, arsenic (As). The implantation region Im is provided in a range of about 100nm in depth on the surface of the semiconductor substrate 10, and the impurity concentration of the implantation region Im is 1e ＋18 /cm 3 ～1e ＋19 /cm 3 . In addition, in some embodiments, the implantation region Im has a predetermined distance X from the edge portions PW1e on the central region C side in the first P-type well region PW1, that is, the implantation region Im has a predetermined distance X from the edge portions PW1e on both sides of the central region C in the width direction H2, and the predetermined distance X ranges from, for example, 0.1 μm to 0.3 μm.
As shown in fig. 3, the silicide region 20 (anode An) is a region where the semiconductor substrate 10 and the metal material are heated to form silicide, and corresponds to the schottky junction SJ. In some embodiments, a higher melting point metal such as nickel (Ni) may be deposited on the semiconductor substrate 10 by sputtering and annealed to form the silicide regions 20. Further, within the silicide region 20, an anode An is formed by generating silicide at the interface of the implantation region Im surface and nickel (Ni).
As shown in fig. 3, the insulating portion 22 is an insulator region, and can mitigate an electric field between the second N-type well region NW2 and the first P-type well region PW 1. In one embodiment of the present application, the insulating portion 22 is, for example, shallow trench isolation (Shallow Trench Isolation, STI). When the insulating portion 22 is a shallow trench isolation, the insulating portion 22 may be formed by etching a predetermined position of the semiconductor substrate 10 to form a patterned shallow trench and filling the shallow trench with an insulating material. In addition, when the material of the semiconductor substrate 10 is silicon (Si), the insulating material is, for example, a silicon oxide film (SiO 2 ) Or a silicon nitride film (SiN), etc.
As shown in fig. 3, the silicide block 24 is An insulating film that separates nickel (Ni) deposited on the anode An from the end of the insulating portion 22 by a desired distance. In addition, silicide blocks 24 are located on both sides of the region where nickel (Ni) is deposited on the anode An to define a region where a silicide film is formed. The silicide blocks 24 may separate areas where silicide is provided from areas where silicide is not provided on the surface of the semiconductor substrate 10.
As shown in fig. 1, the first semiconductor region 2 and the second semiconductor region 3 are low-voltage PMOS, and the third N-type well region NW3 covered with the gate LVG1 has an impurity concentration different from that of the first N-type well region NW 1. Specifically, the low-voltage PMOS structure in the first semiconductor region 2 includes a gate LVG1, a source/drain portion SD, a first N-type well region NW1, a third N-type well region NW3, and an insulating portion 22. Wherein the gate LVG1 is formed on the gate oxide film LVG on the surface of the semiconductor substrate 10 OX And (3) upper part.
As shown in fig. 1, the second semiconductor region 3 also has a high concentration trench region Ch with respect to the first semiconductor region 2, and other portions of the second semiconductor region 3 have the same configuration as the first semiconductor region 2 except for this. The high concentration trench region Ch is formed by implanting an N-type impurity such As arsenic (As) into the third N-type well region NW3 covered with the gate electrode LVG2 in the second semiconductor region 3. The high-concentration trench region Ch is a region of high impurity concentration with respect to the third N-type well region NW 3.
As shown in fig. 1, since the second semiconductor region 3 has the high concentration trench region Ch therein, the semiconductor device 100 has a plurality of low voltage PMOS having different threshold voltages. I.e. the low voltage PMOS threshold voltages in the first semiconductor region 2 and the second semiconductor region 3 are different.
As shown in fig. 1, since the second semiconductor region 3 has the high concentration trench region Ch, the low voltage PMOS threshold voltage in the second semiconductor region 3 is higher than the low voltage PMOS threshold voltage in the first semiconductor region 2. In addition, the threshold value of the low-voltage PMOS in the first semiconductor region 2 and the second semiconductor region 3 also varies according to the formation condition of the third N-type well region NW 3. In the present embodiment, the impurity concentration of the third N-type well region NW3 is, for example, 1e +17 /cm 3 ～1e +18 /cm 3 . In order to raise the threshold voltage, the third N-type well region NW3 in the second semiconductor region 3 is re-implanted with N-type impurities to form a high concentration trench region Ch. The implantation of the high-concentration trench region Ch type N-type impurity is the same as the process of forming the implantation region Im in the schottky diode region 1.
In addition, in some embodiments, as shown in fig. 1, the third N-type well region NW3 of the first semiconductor region 2 and the second semiconductor region 3 is located in a static random access memory (Static Random Access Memory, SRAM). When the third N-type well region NW3 is used to form the sram, the impurity concentration ratio of the third N-type well region NW3 to other regions of the sram may be appropriately adjusted according to the requirements for forming the sram, so that the first semiconductor region 2 and the second semiconductor region 3 can ensure desired performance.
Further, in the present embodiment, the third semiconductor region 4 is the same as a conventional high-voltage PMOS structure. And in the third semiconductor region 4, the same reference numerals as the first semiconductor region 2, the second semiconductor region 3, and the schottky diode region 1 are doped with the same impurity and impurity concentration.
As shown in fig. 4 to 11, the present invention also provides a method of manufacturing a semiconductor device. Hereinafter, a method for manufacturing the semiconductor device 100 including the diode will be described. Fig. 4 to 11 are block diagrams during respective manufacturing steps of the semiconductor device 100.
In each step of forming the semiconductor device 100, for convenience of description, the region for forming the schottky diode region 1 is defined as a schottky diode formation region 1b, the region for forming the first semiconductor region 2 is defined as a first semiconductor formation region 2b, the region for forming the second semiconductor region 3 is defined as a second semiconductor formation region 3b, and the region for forming the third semiconductor region 4 is defined as a third semiconductor formation region 4b.
As shown in fig. 4, in step S10, a region on the semiconductor substrate 10 (silicon substrate) is oxidized, and an oxide film Ox is formed on the surface of the semiconductor substrate 10. In this application, the oxide film Ox is formed by, for example, wet oxidation. The semiconductor substrate 10 in the schottky diode formation region 1b, the first semiconductor formation region 2b, the second semiconductor formation region 3b, and the third semiconductor formation region 4b is ion-implanted and annealed by using an N-type impurity (first-type impurity), a first N-type well region NW1 (first region) is formed in a depth of 3 μm to 6 μm with respect to the surface of the semiconductor substrate 10, and the impurity concentration of the first N-type well region NW1 (first region) is 1e ＋16 /cm 3 ～4e ＋16 /cm 3 . Wherein the N-type impurity is, for example, phosphorus (P) or arsenic (As).
As shown in fig. 5, in step S12, a second N-type well region NW2 is formed in the schottky diode formation region 1b and the third semiconductor formation region 4b of the semiconductor device 100. First, a photoresist layer is formed on the surface of the semiconductor substrate 10, and an opening (mask opening) is provided on the photoresist layer, the opening exposing the position of the second N-type well region NW2. The photoresist layer may be a patterned photoresist layer formed by patterning using a photolithography technique. Then, ion implantation is performed on the surface of the semiconductor substrate 10 using the N-type impurity with the photoresist layer as a mask. After the ion implantation process, the photoresist layer is removed and an annealing process is performed.
As shown in fig. 5, after forming the second N-type well region NW2, the first P-type well region PW1 (second region) is formed using the same manufacturing method as that of the second N-type well region NW2. Specifically, for example, the schottky diode formation region 1b and the third semiconductor formation region 4b of the semiconductor device 100 are subjected to ion implantation treatment and annealing treatment using P-type impurities (second-type impurities) to form a first P-type well region PW1 (second region). The first P-type well region PW1 (second region) is located within the range of 1 μm to 3 μm in depth of the surface of the semiconductor substrate 10, and the impurity concentration in the first P-type well region PW1 (second region) is 1e ＋16 /cm 3 ～6e ＋16 /cm 3 . When the first P-type well region PW1 (second region) is formed, the central region C is located in a region where the anode of the schottky diode region 1 needs to be formed in the width direction H2 of the schottky diode formation region 1 b. Therefore, the central region C is masked by the photoresist material when the P-type impurity is implanted. The P-type impurity implanted into the surface of the semiconductor substrate 10 is, for example, boron (B).
As shown in fig. 6, in step S14, shallow trench isolation STI is formed as the insulating portion 22 in the first semiconductor formation region 2b, the second semiconductor formation region 3b, and the third semiconductor formation region 4b, at positions on both sides of the gate LVG1, the gate LVG2, and the gate HVG3, and at positions that are boundaries of the respective regions of the semiconductor device 100.
Specifically, as shown in fig. 6, first, a silicon nitride film (SiN) is deposited on the surface of the semiconductor substrate 10, and a photoresist layer having an opening portion exposing the STI position of the shallow trench isolation is formed as a mask on the silicon nitride film. Then, the surface of the semiconductor substrate 10 is etched using the photoresist layer as a mask. After etching, the photoresist layer is removed, and the shallow trench formed by etching is oxidized, for example, by about 10 nm. Then, the shallow trench is filled with silicon dioxide (SiO 2 ) And (5) performing annealing treatment on the insulators to form shallow trench isolation STI. Then, chemical mechanical polishing (Chemical Mechanical Polishing, CMP) the shallow trench isolation STI surface to isolate the shallow trench isolation STI surfaceThe insulating portion 22 is formed by planarization. The silicon nitride film (SiN) is then removed.
As shown in fig. 6, after the insulating portion 22 is formed, a gate oxide film HVG is formed in the third semiconductor formation region 4b OX . Specifically, tetraethoxysilane (Tetra ethoxy silane, TEOS) is used as a raw material, and a gas phase reaction (Chemical Vapor Deposition, CVD) at a high temperature is used to form a gate oxide film HVG OX . Gate oxide film HVG OX May be used to define the location of the gate HVG3 of the high voltage PMOS.
As shown in fig. 7, in step S16, a third N-type well region NW3 (third region) is formed in the first semiconductor formation region 2b and the second semiconductor formation region 3b of the semiconductor device 100. Specifically, first, a photoresist layer having openings corresponding to the positions of the third N-type well region NW3 (third region) is formed on the first semiconductor formation region 2b and the second semiconductor formation region 3b of the semiconductor device 100 on the surface of the semiconductor substrate 10. Ion implantation is performed on the surface of the semiconductor substrate 10 using the N-type impurity with the photoresist layer as a mask. After the ion implantation, the photoresist layer is removed. Then, an annealing treatment is performed. Thus, the third N-type well region NW3 can be formed in the first semiconductor formation region 2b and the second semiconductor formation region 3b of the semiconductor device 100, and the impurity concentration of the third N-type well region NW3 is 1e +17 /cm 3 ～1e +18 /cm 3 。
As shown in fig. 8, in step S18, a gate oxide film LVG is formed in the first semiconductor formation region 2b and the second semiconductor formation region 3b OX . Specifically, first, a photoresist layer is formed on the surface of the semiconductor substrate 10, the photoresist layer having openings on the third N-type well region NW3 of the first semiconductor formation region 2b and the second semiconductor formation region 3b, the openings exposing the gate oxide film LVG to be formed OX Is a region of (a) in the above-mentioned region(s). Then, the oxide film Ox in the opening is removed by wet etching, and the photoresist layer is removed. Next, a gate oxide film LVG is formed at a position where the oxide film Ox is removed OX And gate oxide film LVG OX Is less than 3nm thick.
As shown in FIG. 8, inForming gate oxide film LVG OX Thereafter, an implantation region Im is formed in the schottky diode formation region 1b, and a high-concentration trench region Ch is formed in the second semiconductor formation region 3 b. Specifically, first, a photoresist layer PR (mask) is formed over the entire region of the schottky diode formation region 1b, the third N-type well region NW3 of the first semiconductor formation region 2b, and the third semiconductor formation region 4b, except for the implantation region Im. The width of the implantation region Im is narrower than the central region C, and the implantation region Im is located inside the edge portions PW1e of the two first P-type well regions PW1 in the width direction in the central region C. That is, the opening of the photoresist layer PR is located on the implantation region Im in the schottky diode formation region 1b and on the third N-type well region NW3 of the second semiconductor formation region 3 b. At this time, the fixed distance X between each end of the implantation region Im and the edge PW1e of the first P-type well region PW1 is in the range of 0.1 μm to 0.3 μm.
As shown in fig. 8, after forming the photoresist layer PR, N-type impurities, for example, arsenic (As), are implanted into the schottky diode formation region 1b and the second semiconductor formation region 3 b. Wherein the dosage of the implanted N-type impurity is 2e +12 ions/cm 2 ～1.5e + 13 ions/cm 2 . The implant region Im is formed at a maximum depth of 100nm from the surface of the first N-type well region NW1, and has an impurity concentration of at least 1e +18 /cm 3 ～1e +19 /cm 3 Is a region of (a) in the above-mentioned region(s). Similarly, the impurity concentration of the region in which arsenic (As) is implanted in the second semiconductor formation region 3b is also higher than that of the other third N-type well region NW3, and a high-concentration trench region Ch can be formed. After arsenic (As) is implanted into the schottky diode formation region 1b and the second semiconductor formation region 3b, the photoresist layer PR is removed.
As shown in fig. 8, since the diffusion coefficient of arsenic (As) implanted into the schottky diode formation region 1b and the second semiconductor formation region 3b is smaller than that of phosphorus (P), impurity diffusion due to heat treatment in the process is small. The implantation region Im is formed in a shallower region of the surface of the semiconductor substrate 10. Further, in order to form the implantation region Im in a shallow region of the semiconductor substrate 10, the maximum implantation energy of arsenic (As) is, for example, 50keV.
As shown in fig. 9, in step S20, a gate oxide film LVG is formed on the first semiconductor formation region 2b and the second semiconductor formation region 3b OX And forming a gate oxide film LVG on the first semiconductor formation region 2b and the second semiconductor formation region 3b OX And a gate oxide film HVG of the third semiconductor formation region 4b OX Polysilicon is deposited thereon, patterned and etched to form polysilicon of a specific shape for use as a gate.
As shown in fig. 9, a gate oxide film LVG is formed OX And a gate electrode, and a photoresist layer having openings formed thereon in the first semiconductor formation region 2b and the second semiconductor formation region 3 b. The first semiconductor formation region 2b and the second semiconductor formation region 3b are ion-implanted with P-type impurities. Then, the photoresist layer is removed and annealed to form a low voltage PMOS diffusion region LVPex. The diffusion region LVPex is located on the surface of the third N-type well region NW3 of the first semiconductor formation region 2b and the second semiconductor formation region 3b, and is located on both sides of the gate LVG1 and the gate LVG 2.
As shown in fig. 10, in step S22, the sidewalls of the gate LVG1, the gate LVG2, and the gate HVG3 are formed in the first semiconductor formation region 2b, the second semiconductor formation region 3b, and the third semiconductor formation region 4b, and then the source/drain portion SD is formed. In addition, a cathode K is formed in the schottky diode formation region 1 b. Specifically, first, tetraethoxysilane (Tetra ethoxy silane, TEOS) is used as a raw material, an oxide film is formed on the gate electrodes LVG1, LVG2, and HVG3 by a gas phase reaction (Chemical Vapor Deposition, CVD) at a high temperature, and anisotropic etching is performed to leave only the oxide films on both sides of the gate electrodes LVG1, LVG2, and HVG 3. The oxide films on both sides of the gate LVG1, the gate LVG2, and the gate HVG3 form sidewalls. In other embodiments, a stacked silicon nitride (SiN) film may also be deposited as sidewalls using a gas phase reaction (Chemical Vapor Deposition, CVD) at high temperature.
As shown in fig. 10, the gate LVG1, the gate LVG2, and the gate are formedAfter the side wall of the electrode HVG3, a predetermined region is implanted with a dose of at least 1e, for example, in each of the schottky diode formation region 1b, the first semiconductor formation region 2b, the second semiconductor formation region 3b, and the third semiconductor formation region 4b +15 ions/cm 2 And performing annealing treatment. Thereby, the source/drain portion SD or the cathode K is formed in the predetermined region. In addition, P-type impurities may be implanted into the gate LVG1, the gate LVG2, and the gate HVG3 to form P-type gates.
As shown in fig. 11, in step S24, silicide blocks 24 are formed in the schottky diode formation region 1b, and silicide is formed on the surfaces of the gate LVG1, the gate LVG2, the gate HVG3, the source/drain portion SD, the anode An, and the cathode K. In particular. First, tetraethoxysilane (Tetra ethoxy silane, TEOS) is used as a raw material, silicide is formed by a gas phase reaction (Chemical Vapor Deposition, CVD) at a high temperature, and the formed silicide is etched to form silicide blocks 24 at predetermined positions on the surface of the semiconductor substrate 100 in the schottky diode formation region 1 b. The silicide may space the anode An from the end of the insulating portion 22 by a predetermined distance.
As shown in fig. 11, after the silicide block 24 is formed, nickel (Ni) is sputtered on the surfaces of the gate LVG1, the gate LVG2, the gate HVG3, the source/drain portion SD, the anode An, and the cathode K. Particles of nickel (Ni) are deposited on the surfaces of the gate electrode LVG1, the gate electrode LVG2, the gate electrode HVG3, the source/drain portion SD, the anode An and the cathode K. After the sputtering is completed, annealing treatment is performed, and the interfaces between the deposited nickel (Ni) particles and the surfaces of the respective gates LVG1, LVG2, HVG3, SD, an and K are heated, thereby generating silicide at the interfaces.
Fig. 12 is a graph showing the relationship between the impurity concentration in each of the first semiconductor region 2 and the second semiconductor region 3 and the depth from the surface of the semiconductor substrate 10. Wherein the horizontal axis is the depth relative to the surface of the semiconductor substrate 10 and the vertical axis is the impurity concentration. In fig. 12, the dashed line indicates the N-type impurity concentration in the third N-type well region NW3 and the first N-type well region NW1 of the first semiconductor region 2, the solid line indicates the N-type impurity concentration in the high-concentration trench region Ch, the third N-type well region NW3, and the first N-type well region NW1 of the second semiconductor region 3, and the dashed-dotted line indicates the P-type impurity concentration in the semiconductor substrate 10. Further, the impurity concentration in the first semiconductor region 2 at a depth of 10nm from the surface of the semiconductor substrate 10 is set to n1, and the impurity concentration in the second semiconductor region 3 at a depth of 10nm from the surface of the semiconductor substrate 10 is set to n2.
Similarly, fig. 13 is a graph showing the relationship between the impurity concentration of each of the implantation region Im and the first N-type well region NW1 of the schottky diode region 1 and the depth from the surface of the semiconductor substrate 10. The horizontal axis represents the depth relative to the surface of the semiconductor substrate 10, and the vertical axis represents the impurity concentration. In fig. 13, the solid line indicates the N-type impurity concentration in the implantation region Im of the schottky diode region 1 and the first N-type well region NW1, and the dash-dot line indicates the P-type impurity concentration in the semiconductor substrate 10. Further, the impurity concentration in the schottky diode region 1 at a depth of 10nm from the surface of the semiconductor substrate 10 is set to n3.
As shown in fig. 12 and 13, the impurity concentrations in the first semiconductor region 2, the second semiconductor region 3, and the schottky diode region 1 each decrease with increasing depth from the surface of the semiconductor substrate 10. In addition, in step S18 of the above-described manufacturing method, arsenic (As) is implanted into the third N-type well region NW3, and when the depth is 0.1 μm, the impurity concentration of the second semiconductor region 3 is higher than that of the first semiconductor region 2, and this region corresponds to the high-concentration trench region Ch shown in fig. 1. Further, the impurity concentrations n1, n2, and n3 at the respective positions having a depth of 10nm from the surface of the semiconductor substrate 10 have the following relational expression:
（n2-n1）＝n3；
In the semiconductor device 100 shown in fig. 1, the formation process of the high-concentration trench region Ch and the implantation region Im can be shared by forming a manufacturing method satisfying the above relation.
Fig. 14 is a graph showing performance evaluation of the schottky diode manufactured by the manufacturing method according to the present embodiment.
As shown in fig. 14, "+" "indicates a schottky diode formed using cobalt disilicide. In addition, "#" indicates a schottky diode formed using nickel silicide in the original method. "■" indicates a schottky diode manufactured by the manufacturing method provided in this embodiment. In the graph of fig. 14, the horizontal axis represents the forward current IF of each schottky diode when the forward bias voltage of 0.3V is applied. The vertical axis indicates the leakage current IR of each schottky diode when a reverse bias of-15V was applied.
As shown in fig. 14, in the schottky diode formed using cobalt disilicide and the schottky diode formed using nickel silicide in the original method ("+.and" +.j "in fig. 14), the forward current IF performance is greatly deteriorated due to the change of silicide from cobalt disilicide to nickel silicide, i.e., the change of the metal material used for the schottky junction. According to the semiconductor device having the schottky diode manufactured by the manufacturing method according to the present embodiment, the forward current IF performance similar to that of the schottky diode of Co silicide is provided, and the deterioration of the forward current IF performance is significantly improved as compared with the conventional schottky diode using nickel silicide. When reverse bias is applied, the diode has a breakdown voltage of 30V equivalent to that of a conventional schottky diode. Thus, even when nickel silicide is used, a high breakdown voltage and a high forward current can be ensured, and thus an SBD suitable for a semiconductor product handling a high voltage such as DDIC or TDDI can be manufactured.
As described above, according to the method for manufacturing the schottky diode region 1 according to the present embodiment, the SBD performance can be improved without newly adding a manufacturing process or a mask, that is, without increasing the manufacturing cost.
As described above, according to the semiconductor device and the method of manufacturing the same according to the present embodiment, the semiconductor device 100 includes the first semiconductor region 2, the second semiconductor region 3, and the schottky diode SBD region 1 formed on the silicon substrate 10, and the method of manufacturing the semiconductor device 100 includes: the first region forming step S10 is to implant a first type impurity into the silicon substrate to form a first region (first N-type well region NW 1). A second region forming step S12 of forming second regions (first P-type well regions PW 1) on both sides of the central region by implanting second-type impurities having a polarity opposite to that of the first-type impurities in a state where the upper surface of the central region C in the width direction H2 orthogonal to the thickness direction H1 of the silicon substrate is masked in the anode forming region of the schottky diode forming region 1b in the first region; a third region forming step S16 of implanting first type impurities into the first region of the first semiconductor forming region and the first region of the second semiconductor forming region to form a third region (third N-type well region NW 3) having an impurity concentration higher than that of the first region; a high concentration region forming step S18 of implanting a first type impurity into the mask opening in the Schottky diode forming region and the second semiconductor forming region in a state where the upper surface of the region in which at least the trench region is formed in the first semiconductor forming region and the region other than the upper surface of the region in which the implantation region Im is required to be formed are shielded by the Schottky diode forming region; and a Schottky junction step S24 of silicide an anode formation region of the Schottky diode formation region by using a material having a higher work function than cobalt to form a Schottky junction. Thus, without adding a mask or a manufacturing process, a semiconductor device can be manufactured in which a high breakdown voltage is ensured and the forward current IF is improved by increasing the impurity concentration in the region corresponding to the schottky junction in the schottky diode region.
In this application, according to the semiconductor device and the method for manufacturing the same according to the present embodiment, the type and the dose of the impurity implanted in each step are specified so that the impurity concentration in each region becomes a desired value. Thus, a semiconductor that achieves desired performance such as high breakdown voltage can be manufactured.
In the present application, according to the semiconductor device and the method for manufacturing the same according to the present embodiment, in the high concentration region forming step, the depth of the implanted region is set to be within a range of 100nm with respect to the surface of the silicon substrate. Thus, the concentration is increased only in a narrow range in the first region, and the forward current IF performance can be improved while suppressing the breakdown voltage from decreasing.
In this application, according to the semiconductor device and the method of manufacturing the same of the present embodiment, the distance from each edge portion of the central region to the photoresist opening at the time of forming the implantation region is set to be 0.1 μm to 0.3 μm in the width direction. Thus, the implantation region is made small, and the electric field strength of the SBD region can be suppressed from increasing, thereby reducing the leakage current.
In the present application, according to the semiconductor device and the method for manufacturing the same according to the present embodiment, in the high concentration region forming step, the impurity implanted is arsenic (As). This can suppress diffusion of impurities due to heat treatment such as an annealing step, as compared with phosphorus (P).
In the present application, according to the semiconductor device and the method for manufacturing the same according to the present embodiment, in the high concentration region forming step, the ion implantation energy of arsenic (As) is 50keV or less. Since the ion implantation energy is low, impurities after ion implantation can be distributed in a range of less than 50nm from the surface of the semiconductor substrate, and the distribution range of ions after heat treatment such as an annealing process can be suppressed to about 100 nm. Here, the thickness of the oxide film is defined so that the implantation energy is such that ions can pass through the surface of the semiconductor substrate.
In the present application, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, the semiconductor device includes the schottky diode region 1 formed on the silicon substrate 10; a first semiconductor region 2 formed in a silicon substrate, having a trench region implanted with a first type impurity; and a second semiconductor region 3 formed on the silicon substrate and having a high concentration trench region Ch into which the first type impurity is implanted, the schottky diode region 1 including: a silicide region 20 that silicides the anode-forming region using a material having a higher work function than cobalt; and an implantation region Im provided below the silicide region 20 and located near a central region in a width direction orthogonal to a thickness direction of the silicon substrate, and being implanted with a first type impurity, the impurity concentration of the implantation region being within ±10% of a difference between the impurity concentration of the trench region of the second semiconductor region and the impurity concentration of the trench region of the first semiconductor region.
In addition, according to the semiconductor device and the method of manufacturing the same according to the present embodiment, the second semiconductor region is used for the SRAM. Thus, the ratio of the impurity concentration to other regions formed in each manufacturing process of the SRAM can be optimized, and the 2 nd MOS transistor can ensure desired performance.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A method of manufacturing a semiconductor device including a first semiconductor region, a second semiconductor region, and a schottky diode region provided over a semiconductor substrate, comprising the steps of:
implanting a first type impurity into the semiconductor substrate to form a first region;
A second type impurity is injected into the upper surface of a central region in the first region, which is in the Schottky diode forming region and is positioned in the width direction orthogonal to the thickness direction of the semiconductor substrate, so as to form a second region, and the second region is positioned at two sides of the central region;
implanting first type impurities into a first region in the first semiconductor forming region and the second semiconductor forming region to form a third region, wherein the impurity concentration in the third region is greater than that in the first region;
forming a photoresist layer which shields an upper surface of the first semiconductor forming region in which at least a trench region is formed, and a region other than a middle region of the central region, which is narrower than the central region in width and is provided inside edge portions on both sides of the central region, of the schottky diode forming region;
injecting first-type impurities into the Schottky diode forming region and the second semiconductor forming region by taking the photoresist layer as a mask, forming an injection region in the Schottky diode forming region, forming a high-concentration groove region in the second semiconductor forming region, and positioning the high-concentration groove region in a region covered by a grid electrode in the second semiconductor forming region; and
Silicide is formed in the anode forming region of the schottky diode forming region to form a schottky junction, and a work function of a material used in forming the silicide is higher than that of cobalt.
2. The method for manufacturing a semiconductor device according to claim 1, wherein:
the first type impurity is implanted to have an impurity concentration of 1e when the first region is formed ＋16 /cm 3 ～4e ＋16 /cm 3 ；
The second type impurity is implanted to have an impurity concentration of 1e when the second region is formed ＋16 /cm 3 ～6e ＋16 /cm 3 ；
The impurity concentration of the first type impurity implanted in the formation of the third region is higher than 1e +17 /cm 3 ；
The dose of the first type impurity implanted in the formation of the high concentration trench region and the implantation region is 2e + 12 ions/cm 2 ～1.5e +13 ions/cm 2 ；
The impurity concentration of the implantation region is 1e ＋18 /cm 3 ～1e ＋19 /cm 3 。
3. The method for manufacturing a semiconductor device according to claim 1, wherein a depth of the implantation region is within a range of 100nm from a surface of the semiconductor substrate.
4. The method according to claim 1, wherein the photoresist layer in the schottky diode formation region has an opening portion formed thereon, and a distance from the opening portion to both side edge portions of the central region in a width direction is 0.1 μm to 0.3 μm when the implantation region is formed.
5. The method according to claim 1, wherein the first type impurity implanted when the implantation region and the high concentration trench region are formed comprises arsenic.
6. The method according to claim 5, wherein an ion implantation energy is less than 50KeV when forming the implantation region and the high concentration trench region.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the first region is formed at a depth of 3 μm to 63 μm from a surface of the semiconductor substrate.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the second region is formed at a depth from the surface of the semiconductor substrate in a range of 1 μm to 3 μm.
9. A semiconductor device, comprising at least:
a schottky diode region formed on the semiconductor substrate;
a first semiconductor region formed on the semiconductor substrate, the first semiconductor region having a trench region into which a first type impurity is implanted, the trench region in the first semiconductor region being located in a region covered by a gate in the first semiconductor region; and
A second semiconductor region formed on the semiconductor substrate, the second semiconductor region having a trench region into which a first type impurity is implanted, the trench region in the second semiconductor region being located in a region covered by a gate in the second semiconductor region;
wherein the schottky diode region includes:
a silicide region using a material having a higher work function than cobalt;
an implantation region provided in the semiconductor substrate covered with the silicide region, the implantation region being located in a middle region of a central region in a width direction orthogonal to a thickness direction of the semiconductor substrate, the middle region being narrower in width than the central region and provided inside edge portions on both sides of the central region, the implantation region being implanted with a first type impurity, and the implantation region and the trench region in the second semiconductor region being formed simultaneously;
wherein an impurity concentration of the implantation region is within ±10% of a difference between an impurity concentration of the trench region in the second semiconductor region and an impurity concentration of the trench region in the first semiconductor region.
10. The semiconductor device according to claim 9, wherein the second semiconductor region is provided in a static random access memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310239019.0A CN115954358B (en) | 2023-03-14 | 2023-03-14 | Method for manufacturing semiconductor device and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310239019.0A CN115954358B (en) | 2023-03-14 | 2023-03-14 | Method for manufacturing semiconductor device and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115954358A CN115954358A (en) | 2023-04-11 |
| CN115954358B true CN115954358B (en) | 2023-05-26 |
Family
ID=85906986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310239019.0A Active CN115954358B (en) | 2023-03-14 | 2023-03-14 | Method for manufacturing semiconductor device and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115954358B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110078867A (en) * | 2009-12-31 | 2011-07-07 | 주식회사 동부하이텍 | Semiconductor device and method for manufacturing thesame |
| CN103579347A (en) * | 2012-08-03 | 2014-02-12 | 富士通半导体股份有限公司 | Semiconductor device and manufacturing method of semiconductor device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7388271B2 (en) * | 2005-07-01 | 2008-06-17 | Texas Instruments Incorporated | Schottky diode with minimal vertical current flow |
| US20080116528A1 (en) * | 2006-11-22 | 2008-05-22 | Tsuneichiro Sano | Semiconductor device and method of manufacturing the same |
| JP5530602B2 (en) * | 2008-04-09 | 2014-06-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| TWI384625B (en) * | 2008-06-30 | 2013-02-01 | Alpha & Omega Semiconductor | Enhancing schottky breakdown voltage (bv) without affecting an integrated mosfet-schottky device layout |
| CN101771088A (en) * | 2010-01-21 | 2010-07-07 | 复旦大学 | PN (positive-negative) junction and Schottky junction mixed type diode and preparation method thereof |
| CN102789979B (en) * | 2012-08-22 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | Schottky diode and forming method thereof |
| US8735950B2 (en) * | 2012-09-06 | 2014-05-27 | Freescale Semiconductor, Inc. | Tunable schottky diode with depleted conduction path |
| CN104900718B (en) * | 2014-03-05 | 2018-04-17 | 中芯国际集成电路制造(上海)有限公司 | A kind of Schottky diode and its manufacture method |
| JP6477106B2 (en) * | 2015-03-24 | 2019-03-06 | サンケン電気株式会社 | Semiconductor device |
| WO2018004682A1 (en) * | 2016-07-01 | 2018-01-04 | Intel IP Corporation | Schottky diodes using cmos technology |
| CN111697057B (en) * | 2020-06-09 | 2022-07-15 | 杰华特微电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
-
2023
- 2023-03-14 CN CN202310239019.0A patent/CN115954358B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110078867A (en) * | 2009-12-31 | 2011-07-07 | 주식회사 동부하이텍 | Semiconductor device and method for manufacturing thesame |
| CN103579347A (en) * | 2012-08-03 | 2014-02-12 | 富士通半导体股份有限公司 | Semiconductor device and manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115954358A (en) | 2023-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10553717B2 (en) | Medium voltage MOSFET device | |
| US9059141B2 (en) | Buried gate transistor | |
| US9728632B2 (en) | Deep silicon via as a drain sinker in integrated vertical DMOS transistor | |
| US6323525B1 (en) | MISFET semiconductor device having relative impurity concentration levels between layers | |
| US7846783B2 (en) | Use of poly resistor implant to dope poly gates | |
| JP2816353B2 (en) | Method of manufacturing integrated circuit having MOS field effect transistor | |
| US8294210B2 (en) | High voltage channel diode | |
| CN102446768B (en) | Semiconductor device and method of manufacturing semiconductor device | |
| US6888176B1 (en) | Thyrister semiconductor device | |
| US7989853B2 (en) | Integration of high voltage JFET in linear bipolar CMOS process | |
| US11545545B2 (en) | Superjunction device with oxygen inserted Si-layers | |
| KR20090075064A (en) | Method of fabricating semiconductor device having differential gate dielectric layer and related device | |
| US20120322216A1 (en) | Method for reducing poly-depletion in dual gate cmos fabrication process | |
| US11211382B2 (en) | Methods and apparatuses including a boundary of a well beneath an active area of a tap | |
| US20080272439A1 (en) | Small geometry mos transistor with thin polycrystalline surface contacts and method for making | |
| US9184163B1 (en) | Low cost transistors | |
| US20130164915A1 (en) | Method for fabricating power semiconductor device with super junction structure | |
| KR20170074344A (en) | Semiconductor device and method of forming the same | |
| US20130026565A1 (en) | Low rdson resistance ldmos | |
| KR100910230B1 (en) | Dual gate of semiconductor device and method for forming the same | |
| CN112242445A (en) | LDMOS device and forming method thereof | |
| CN115954358B (en) | Method for manufacturing semiconductor device and semiconductor device | |
| CN112133758B (en) | Power semiconductor device and method of manufacture | |
| US8026507B2 (en) | Two terminal quantum device using MOS capacitor structure | |
| US6933564B2 (en) | Semiconductor integrated circuit device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |