CN115952004B - Resource allocation method, device, electronic equipment and storage medium - Google Patents
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- CN115952004B CN115952004B CN202310134406.8A CN202310134406A CN115952004B CN 115952004 B CN115952004 B CN 115952004B CN 202310134406 A CN202310134406 A CN 202310134406A CN 115952004 B CN115952004 B CN 115952004B
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Abstract
The disclosure provides a resource allocation method, a device, an electronic device and a storage medium, wherein the method comprises the following steps: sampling the system-level chip to obtain a first sampling result; confirming the resource configuration corresponding to the system-level chip based on the first sampling result and a pre-configured resource configuration comparison table; loading corresponding resources for the system-level chip based on the resource configuration corresponding to the system-level chip; the system-level chip is a multi-core heterogeneous chip at least comprising a first core and a second core, so that resource configuration can be uniformly carried out on the system-level chips of different products according to sampling results of the system-level chip and a pre-configured resource configuration comparison table, and a software version does not need to be independently developed for a certain system-level chip.
Description
Technical Field
The disclosure relates to the technical field of chips, and in particular relates to a resource allocation method, a device, electronic equipment and a storage medium.
Background
In the related art, the resources of System on chips (SoC) adapted by different products are different, so that in order to adapt the same series of System on chips to different products, different software versions need to be independently developed for each System on Chip to configure corresponding resources, which can definitely increase a large amount of development time and reduce the resource configuration efficiency of the System on Chip.
Disclosure of Invention
The present disclosure provides a resource allocation method, apparatus, electronic device, and storage medium, so as to at least solve the above technical problems in the prior art.
According to a first aspect of the present disclosure, there is provided a resource allocation method, including: sampling the system-level chip to obtain a first sampling result; confirming the resource configuration corresponding to the system-level chip based on the first sampling result and a pre-configured resource configuration comparison table; loading corresponding resources for the system-level chip based on the resource configuration corresponding to the system-level chip; the system-on-chip is a multi-core heterogeneous chip at least comprising a first core and a second core.
According to a second aspect of the present disclosure, there is provided a resource allocation apparatus comprising: the sampling unit is used for sampling the system-level chip to obtain a first sampling result; the confirming unit is used for confirming the resource configuration corresponding to the system-level chip based on the first sampling result and a pre-configured resource configuration comparison table; the configuration unit is used for loading corresponding resources for the system-level chip based on the resource configuration corresponding to the system-level chip; the system-on-chip is a multi-core heterogeneous chip at least comprising a first core and a second core.
According to a third aspect of the present disclosure, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the present disclosure.
According to a fourth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of the present disclosure.
According to the resource allocation method, a first sampling result is obtained by sampling a system-in-chip; confirming the resource configuration corresponding to the system-level chip based on the first sampling result and a pre-configured resource configuration comparison table; loading corresponding resources for the system-level chip based on the resource configuration corresponding to the system-level chip; the system-on-chip is a multi-core heterogeneous chip at least comprising a first core and a second core. Therefore, the resource configuration can be uniformly carried out for the system-level chips of different products according to the sampling result of the system-level chips and the pre-configured resource configuration comparison table, and a software version does not need to be independently developed for a certain system-level chip.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which: in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 illustrates an alternative flow diagram of a resource allocation method provided by an embodiment of the present disclosure; FIG. 2 illustrates another alternative flow diagram of a resource allocation method provided by an embodiment of the present disclosure; FIG. 3 illustrates yet another alternative flow diagram of a resource allocation method provided by an embodiment of the present disclosure; FIG. 4 is a schematic diagram of an alternative configuration of a resource allocation apparatus according to an embodiment of the present disclosure; fig. 5 shows a schematic diagram of a composition structure of an electronic device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
The proper nouns to which the present disclosure relates are explained first.
1) A system-on-chip.
The conventional chip mainly comprises a single unit, such as a conventional central processing unit (Central Processing Unit, CPU) mainly comprises a computing unit; and the system-in-chip can also comprise a memory, a power supply controller, a clock controller, an interrupt controller, a processor core and other components.
2) Hardware domain.
The system-on-chip may be implemented based on a scheme of hard isolation. That is, the plurality of hardware resources inside the system-in-chip are divided into several groups, each group includes resources required by one or more units (such as a computing unit, a clock controller, an interrupt controller, a processor core, etc.), and the resources in each group use the same number, respond to the data access requirement mutually, and do not affect the hardware access requirements of other groups. Each set hardware resource group is a hardware domain, each hardware domain independently runs an operating system, and data interaction is completed between different hardware domains in a mode of inter-core communication.
Different hardware resources may be partitioned into different groups as needed, e.g., one or more processor cores, graphics processor (Graphics Processing Unit, GPU) GPU, and other hardware resources suitable for high performance computing are partitioned into a group, operating system is run, executing tasks with high performance requirements; meanwhile, one or more processor cores and other hardware resources are divided into a group, an RTOS operating system is operated, and tasks with high real-time requirements are executed. Different groups, i.e. different hardware domains.
3) Inter-core communication.
There is also a need for information communication between different hardware domains, and this communication mode is called inter-core communication, and has more advantages than chip-to-chip communication, such as no need to transmit signals off-chip, and thus security and speed are improved greatly. Internuclear communications come in a variety of forms, such as mailbox (mailbox) mechanisms suitable for transmitting instructions, and shared memory mechanisms suitable for sharing data.
4) And (3) isomerism.
There may be differences between the multiple hardware domains that are considered heterogeneous if they reach a point where they cannot be uniformly scheduled by the operating system, even though the same processor core is used. Multiple hardware domains may be homogenous or heterogeneous. It should be noted that heterogeneous is an additional limitation on multiple hardware domains, and multi-core heterogeneous is a hardware concept, not a software concept.
With the development of semiconductor technology, the integration level of SoC is higher and higher, and the functions to be realized are also more and more complex. The heterogeneous SoC of many cores has processor cores (such as Cortex-R5 (R5 core)) supporting high real-time performance, runs RTOS system or BAREMETA, and has powerful processor cores (such as Cortex-A55 (A55 core)) and runs linux or Android system. Under the multi-core heterogeneous platform, peripheral interface resources are divided into a plurality of hardware resource domains for management, a security (security) domain (based on R5 core implementation, running an RTOS system or BAREMETA) manages allocation of all resources, and an application domain (Cortex-A55, running a linux or Android system) uses the resources allocated by the security domain. When related resources need to be invoked across domains, a series of processes need to be performed. For terminal product manufacturers, a series of products may have the same core function, and the difference is that the external interfaces are different, so that the method for enabling the firmware to be compatible with a plurality of products is provided for the scene, the workload of software development and maintenance is reduced, and the product marketing is accelerated.
For each SoC used by different companies, products with different types and different market directions can be developed. The core functions of the products are similar, the difference is that the external interfaces are different, and when the products are developed, one firmware corresponds to one hardware platform, and each product needs to be realized completely. Each product development cycle is almost the same as the cost of post maintenance.
Aiming at the defects of the system-on-chip resource allocation in the related art, the disclosure provides a resource allocation method to at least solve some or all of the above technical problems.
Fig. 1 is a schematic flow chart of an alternative resource allocation method according to an embodiment of the disclosure, and will be described according to the steps.
Step S101, sampling is carried out on a system-in-chip to obtain a first sampling result.
In some embodiments, the resource allocation device (hereinafter referred to as a device) may sample the system-in-chip based on an analog-to-digital converter (Analog to Digital Converter, ADC) built-in the system-in-chip, or may sample the system-in-chip based on an ADC external to the system-in-chip.
In some alternative embodiments, the device may weld different resistors on the ADC detection circuits of different products, where the voltage division results of the different resistors are different, and the corresponding sampling results are different, so that the product corresponding to the system-in-chip may be determined based on the sampling results.
Step S102, confirming the resource configuration corresponding to the system-in-chip based on the first sampling result and a pre-configured resource configuration comparison table.
In some embodiments, the pre-configured resource configuration lookup table may include: sampling results, products corresponding to the system level chip and corresponding relation among resource allocation of each core of the system level chip; the products corresponding to the system-level chips are different, and the sampling results are different.
In some embodiments, the apparatus confirms a product corresponding to the system-on-chip and a resource configuration corresponding to the system-on-chip in a pre-configured resource configuration lookup table based on the first sampling result. The resource configuration corresponding to the system-level chip may include hardware resources of each domain included in the system-level chip. Each domain includes the same class of processor cores (first core or second core).
In some alternative embodiments, in response to a change in the content of the pre-configured resource configuration lookup table, the apparatus updates the pre-configured resource configuration lookup table during the system on chip in-memory initialization and loading phase. Wherein, the content change of the resource configuration comparison table can include content addition, deletion, update and the like in the resource configuration comparison table.
Step S103, based on the resource configuration corresponding to the system-level chip, corresponding resources are loaded for the system-level chip.
In some embodiments, the apparatus loads respective resources for each core included in the system-on-chip based on a resource configuration corresponding to the system-on-chip; the resource may be a hardware resource.
Thus, by the resource allocation method provided by the embodiment of the present disclosure, only a resource allocation comparison table needs to be pre-allocated, and different resources are allocated to different products; after the system-level chip is sampled, products corresponding to the system-level chip are confirmed based on sampling results, so that resource allocation of each core of the system-level chip can be determined, and corresponding resources are loaded for the system-level chip. Therefore, the resource configuration can be carried out for the system-level chips of different products in batches, and software does not need to be independently developed for a certain system-level chip. In addition, the resource allocation comparison table can flexibly add and delete related contents and is suitable for different series of system-level chips.
Fig. 2 is a schematic flowchart of another alternative resource allocation method according to an embodiment of the disclosure, and will be described according to the steps.
Step S201, based on the first sampling result, loading corresponding resources for the system-in-chip.
In some embodiments, after the system on chip is powered up, the first core enters a memory initialization and loading (DDR Initializer and Loader, DIL 2) stage, and after the initialization of the analog-to-digital converter is completed, the system on chip is sampled, and a first sampling result is obtained. And confirming a product corresponding to the system-level chip and resources (handover resources) of each core of the system-level chip based on the first sampling result and a pre-configured resource configuration comparison table. That is, it is determined which resources are used in the security domain corresponding to the first core and which resources are used in the application domain corresponding to the second core. Wherein the first core and the second core are both processor cores. The device loads corresponding resources for each core included in the system-level chip based on the resource configuration corresponding to the system-level chip; the resource may be a hardware resource.
Step S202, loading each pin configuration corresponding to the first core.
In some embodiments, after loading the corresponding resources for the system-in-chip based on the resource configuration corresponding to the system-in-chip, the device responds to the first core entering the start-up stage to sample the system-in-chip and obtain a second sampling result; and comparing the first sampling result with the second sampling result, restarting the first core if the first sampling result is inconsistent with the second sampling result, or loading each pin configuration corresponding to the first core based on a pin list if the first sampling result is consistent with the second sampling result. The pin list may be pinumx, including the functions implemented by each pin (pin) target.
In some alternative embodiments, in response to the pin list requiring updating, the pin list is updated at the first core entering a startup phase.
The purpose of comparing the first sampling result with the second sampling result is to prevent the sampling result from being wrong due to unstable state in the initial stage of powering on the system-in-chip, and further the device confirms the error of the resource configuration corresponding to the system-in-chip. If the first sampling result is consistent with the second sampling result, the fact that the sampling result of the initial stage of power-on of the system-in-chip is correct is indicated, the device confirms that the result of the resource configuration corresponding to the system-in-chip is correct, and then the loaded resources are correct; otherwise, if the first sampling result and the second sampling result are inconsistent, it indicates that the sampling result in the initial stage of powering on the system-in-chip is wrong, and at this time, the first core needs to be restarted, so that the system-in-chip (and the first core) reenters the memory initialization and loading stage, and samples the system-in-chip again, and step S201 is executed.
It should be noted that, in the process of sampling the system-in-chip in the memory initialization and loading stage, the first core can obtain the first sampling result, but the second core cannot obtain the first sampling result, so the first core is required to send the first sampling result to the second core in an inter-core communication manner.
Step S203, loading the resources corresponding to the device tree of the second core.
In some embodiments, in response to the second core entering the start-up phase, sampling the system-on-chip to obtain a third sampling result; and comparing the first sampling result with the third sampling result, restarting the system-level chip if the first sampling result is inconsistent with the third sampling result, or loading resources corresponding to the equipment tree of the second core based on a resource configuration table if the first sampling result is consistent with the third sampling result. The resource configuration table may be a flat device tree (Flattened Device Tree, FDT) configuration table, which is used to determine to load different kernel (kernel) device trees and determine peripheral resources that can be used under the kernel.
In the implementation, in order to ensure the safety and reliability of the system, whether the first sampling result and the third sampling result are always required to be confirmed, if so, the system is safe and reliable, and the resources corresponding to the equipment tree can be loaded; if the inconsistency indicates that the system is not safe and reliable, the first core needs to be restarted at this time, so that the system-in-chip (and the first core) reenters the memory initialization and loading stage, and the system-in-chip is sampled again, and step S201 is executed.
In some alternative embodiments, the pin list is updated at the second core entering a startup phase in response to the resource configuration table requiring an update.
Thus, by using the resource allocation method provided by the embodiment of the present disclosure, a software developer only needs to spend time developing related functions on a first product using a certain series of system-in-chip, count possible changes of the same series of products on hardware into a pre-configured resource allocation comparison table, directly burn firmware after a new hardware platform (SoC) is manufactured, without redevelopment, and one firmware is compatible with a plurality of hardware products. Even if the new hardware platform appears without considering the change of the cycle before, only the pre-configured resource configuration comparison table needs to be modified. The development time of the product is greatly shortened, and the software version is simple and convenient to maintain. The production efficiency is greatly improved, a plurality of software versions are not required to be provided by research personnel, the communication cost is reduced, the production problem of firmware version burning errors is avoided, and the product is accelerated to be marketed.
Fig. 3 is a schematic flowchart of another alternative resource allocation method according to an embodiment of the disclosure, and will be described according to the steps.
In step S301, the first core is in the memory initialization and loading stage, starts ADC sampling, and loads corresponding resources according to the first sampling result.
In some embodiments, after the system-on-chip is powered on and started, the first core is in a memory initialization and loading stage, and after the initialization of the analog-to-digital converter is completed, the system-on-chip is sampled to obtain a first sampling result. And loading corresponding handover resources by the device based on the first sampling result and a pre-configured resource configuration comparison table. I.e. it is determined which resources are used in the security domain corresponding to the first core and which resources are used in the application domain corresponding to the second core.
The pre-configured resource configuration comparison table is maintained in the memory initialization and loading stage, that is, in response to the content change of the pre-configured resource configuration comparison table, the pre-configured resource configuration comparison table is updated in the system-in-chip memory initialization and loading stage.
Step S302, in a first core starting stage, ADC sampling is carried out, and whether a first sampling result and a second sampling result are consistent or not is judged.
In some embodiments, the first core enters a start-up phase (or enters a security OS of the first core), the device starts ADC sampling again, obtains a second sampling result, compares the first sampling result with the second sampling result, if they are consistent, executes step S303, and if they are inconsistent, restarts the first core, and executes step S301.
The purpose of comparing the first sampling result and the second sampling result is to prevent the system from being powered on in the initial stage, because the sampling result is wrong due to unstable state.
Step S303, configuring each pin corresponding to the first core.
In some embodiments, in response to the first sampling result being consistent with the second sampling result, a pin configuration (pinmux) corresponding to the first core is loaded based on the pin list, and a function implemented by each pin in the system-in-chip is determined.
The pin list is maintained during a first core startup phase, that is, in response to a change in the content of the pin list, the pin list is updated during the first core entry startup phase.
Step S304, in the second core starting stage, ADC sampling is carried out, and whether the first sampling result is consistent with the third sampling result is judged.
In some embodiments, the second core enters a start-up phase (or enters UBOOT of the second core), the device starts ADC sampling again, obtains a third sampling result, compares the first sampling result with the third sampling result, if they are consistent, executes step S305, and if they are inconsistent, restarts the system-on-chip, executes step S301.
The purpose of comparing the first sampling result with the third sampling result is to confirm whether the energy supply of the system corresponding to the system-level chip is normal or not and whether the environment is safe or not.
Step S305, loading the resources corresponding to the device tree of the second core.
In some embodiments, if the first sampling result and the third sampling result are consistent, the apparatus loads a resource corresponding to the device tree of the second core based on the resource configuration table.
Wherein, the resource configuration table may be a UBOOT self-contained FDT table. The resource allocation table is maintained during the second core startup phase, that is, in response to a change in the contents of the resource allocation table, the resource allocation table is updated during the second core entry startup phase.
In some alternative embodiments, the first core may be Cortex-R5 and the second core may be Cortex-A55.
In this way, by the resource allocation method provided by the embodiment of the disclosure, different resistors are welded on the ADC sampling circuit, the voltage division results are different, and the ADC sampling results are also different, so that different products are judged; and modifying the single resource list into a plurality of pre-configured resource configuration comparison tables, forming a resource list group according to the planning of the hardware circuit, loading different resources through the ADC sampling circuit, and realizing that one firmware is matched with a plurality of hardware platforms. And if the newly added hardware planning exists in the later period, only the pre-configured resource configuration comparison table is updated. And the RTOS or the baremetal system on Cortex-R5 and the Linux or Android system on Cortex-A55 share data through RPMSG (inter-core communication), so that the correctness of the sampling result is confirmed. Because the state that the voltage is unstable possibly exists in the initial stage of power-on, the detection result on the R5 core in the initial stage of power-on is synchronously transmitted to the Linux/Android system on the A55 core through the RPMSG, and if the front detection result and the rear detection result are inconsistent, the system is restarted to detect again, so that the safety and the reliability of the system are ensured.
Fig. 4 is a schematic diagram showing an alternative configuration of a resource allocation apparatus according to an embodiment of the present disclosure, and will be described in terms of the respective parts.
In some embodiments, the resource allocation apparatus 400 includes a sampling unit 401, a confirmation unit, and a allocation unit 403.
The sampling unit 401 is configured to sample a system-in-chip to obtain a first sampling result; the confirmation unit 402 is configured to confirm the resource configuration corresponding to the system-in-chip based on the first sampling result and a pre-configured resource configuration comparison table; the configuration unit 403 is configured to load corresponding resources for the system-level chip based on the resource configuration corresponding to the system-level chip; the system-on-chip is a multi-core heterogeneous chip at least comprising a first core and a second core.
The configuration unit 403 is specifically configured to load corresponding resources for each core included in the system-on-chip.
The configuration unit 403 is further configured to sample the system-in-chip after loading the corresponding resources for the system-in-chip based on the resource configuration corresponding to the system-in-chip, and obtain a second sampling result in response to the first core entering the startup phase; and comparing the first sampling result with the second sampling result, restarting the first core if the first sampling result is inconsistent with the second sampling result, or loading each pin configuration corresponding to the first core based on a pin list if the first sampling result is consistent with the second sampling result.
The configuration unit 403 is further configured to send the first sampling result to the second core by using an inter-core communication manner.
The configuration unit 403 is further configured to sample the system-in-chip to obtain a third sampling result in response to the second core entering the start-up phase; and comparing the first sampling result with the third sampling result, restarting the system-level chip if the first sampling result is inconsistent with the third sampling result, or loading resources corresponding to the equipment tree of the second core based on a resource configuration table if the first sampling result is consistent with the third sampling result.
In some embodiments, the pre-configured resource configuration lookup table includes: sampling results, products corresponding to the system level chip and corresponding relation among resource allocation of each core of the system level chip; the products corresponding to the system-level chips are different, and the sampling results are different.
The configuration unit 403 is further configured to update the pre-configured resource configuration reference table when the system-on-chip enters the memory initialization and loading stage in response to the content change of the pre-configured resource configuration reference table.
According to embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.
Fig. 5 shows a schematic block diagram of an example electronic device 800 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 5, the electronic device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.
Various components in electronic device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the electronic device 800 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.
The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the respective methods and processes described above, such as a resource allocation method. For example, in some embodiments, the resource allocation method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 800 via the ROM 802 and/or the communication unit 809. When a computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the resource allocation method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the resource configuration method by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above can be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems on chip (socs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. A method of resource allocation, the method comprising:
sampling the system-level chip to obtain a first sampling result;
confirming the resource configuration corresponding to the system-level chip based on the first sampling result and a pre-configured resource configuration comparison table;
loading corresponding resources for the system-level chip based on the resource configuration corresponding to the system-level chip;
responding to the first core entering a starting stage, sampling the system-level chip, and obtaining a second sampling result;
comparing the first sampling result with the second sampling result, restarting the first core if the first sampling result is inconsistent with the second sampling result, or loading each pin configuration corresponding to the first core based on a pin list if the first sampling result is consistent with the second sampling result;
the system-on-chip is a multi-core heterogeneous chip at least comprising the first core and the second core.
2. The method of claim 1, wherein loading the system-on-chip with the respective resources based on the corresponding resource configuration of the system-on-chip comprises:
respective resources are loaded for each core included in the system-on-chip.
3. The method according to claim 1, wherein the method further comprises:
the first core sends the first sampling result to the second core in an inter-core communication mode.
4. A method according to claim 3, characterized in that the method further comprises:
responding to the second core entering a starting stage, sampling the system-level chip, and obtaining a third sampling result;
and comparing the first sampling result with the third sampling result, restarting the system-level chip if the first sampling result is inconsistent with the third sampling result, or loading resources corresponding to the equipment tree of the second core based on a resource configuration table if the first sampling result is consistent with the third sampling result.
5. The method of claim 1, wherein the pre-configured resource configuration lookup table comprises:
sampling results, products corresponding to the system level chip and corresponding relation among resource allocation of each core of the system level chip;
the products corresponding to the system-level chips are different, and the sampling results are different.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
and in response to the content change of the pre-configured resource configuration comparison table, updating the pre-configured resource configuration comparison table in the stage of the system-in-chip entering the memory initialization and loading.
7. A resource allocation apparatus, the apparatus comprising:
the sampling unit is used for sampling the system-level chip to obtain a first sampling result;
the confirming unit is used for confirming the resource configuration corresponding to the system-level chip based on the first sampling result and a pre-configured resource configuration comparison table;
the configuration unit is used for loading corresponding resources for the system-level chip based on the resource configuration corresponding to the system-level chip; responding to the first core entering a starting stage, sampling the system-level chip, and obtaining a second sampling result; comparing the first sampling result with the second sampling result, restarting the first core if the first sampling result is inconsistent with the second sampling result, or loading each pin configuration corresponding to the first core based on a pin list if the first sampling result is consistent with the second sampling result;
the system-on-chip is a multi-core heterogeneous chip at least comprising the first core and the second core.
8. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.
9. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-6.
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| US11463439B2 (en) * | 2017-04-21 | 2022-10-04 | Qwerx Inc. | Systems and methods for device authentication and protection of communication on a system on chip |
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