CN115940882A - Multiplexing error correction circuit and method under high-pass mode and low-pass mode - Google Patents

Abstract

The invention discloses a circuit and a method for correcting multiplexing errors in a high-pass mode and a low-pass mode, wherein the circuit comprises a high-pass/low-pass filtering module, a low-pass filtering module and a filtering module, wherein the high-pass/low-pass filtering module is used for performing high-pass filtering on an input signal when the stray frequency spectrum of a stray wave signal is in a high frequency and performing low-pass filtering when the stray frequency spectrum is in a low frequency; the time sequence path/direct current bias module is used for outputting a clock signal subjected to level shift when the stray wave signal is in a high-frequency state and outputting a direct current bias signal when the stray wave signal is in a low-frequency state; and the frequency mixing amplification module is respectively connected with the high-pass/low-pass filtering module and the time sequence path/direct current offset module, and is used for mixing the input signal at the high frequency position to the low frequency position when receiving the high-pass filtering signal and the clock signal and amplifying the input signal at the low frequency position when receiving the low-pass filtering signal and the direct current offset signal. The invention realizes the functions of screening high-frequency and low-frequency stray wave signals and mixing amplification, and simultaneously reduces the chip size and the chip cost.

Description

Multiplexing error correction circuit and method under high-pass mode and low-pass mode

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to a circuit and a method for correcting a multiplexing error in a high-pass mode and a low-pass mode.

Background

In high-speed optical communication design, a time domain interleaving mode is often required to increase the signal speed, and a difficulty of the time domain interleaving technology is synchronization of clocks of multiple channels, when the clocks among the channels have phase errors, an output signal of a transmitting end may exhibit nonlinearity, and the nonlinearity may be represented as a spur with a specific frequency in a frequency domain.

In order to eliminate the phase error between the detection channels and avoid the interference of the stray wave signals, a low-pass filter is respectively needed to suppress the interference of the high-frequency stray wave signals, and a high-pass filter is needed to suppress the interference of the low-frequency stray wave signals, an amplifier is used for amplifying the low-frequency stray wave signals, a mixer is used for mixing the high-frequency stray wave signals to the low frequency and providing gain, so that the stray wave signals can be conveniently quantized by a post-module, and therefore the high-pass filter and the low-pass filter are integrated in a chip to respectively filter the stray wave signals, and the mixer and the amplifier are integrated to correspondingly process the stray wave signals.

Therefore, there is a need for a multiplexing error correction circuit in high-pass mode and low-pass mode, which can reduce chip size and chip cost while realizing the functions of high-frequency and low-frequency stray wave signal screening and mixing amplification.

Disclosure of Invention

In order to solve the technical problem that the elimination of phase errors among detection channels can influence the size and the cost of a chip, the invention provides a multiplexing error correction circuit and a method under a high-pass mode and a low-pass mode, and the specific technical scheme is as follows:

the invention provides a multiplexing error correction circuit under a high-pass mode and a low-pass mode, which comprises:

the high-pass/low-pass filtering module is used for receiving a stray wave signal and an input signal, carrying out high-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a high frequency, and carrying out low-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a low frequency;

the time sequence path/direct current bias module is used for receiving a clock signal, a direct current bias signal and an enable signal representing the high-low frequency state of the stray wave signal, outputting the clock signal subjected to level shift when the stray wave signal is in the high-frequency state, and outputting the direct current bias signal when the stray wave signal is in the low-frequency state;

and the frequency mixing amplification module is respectively connected with the high-pass/low-pass filtering module and the time sequence path/direct current bias module, and is used for inhibiting low-frequency interference signals and mixing the input signals at a high frequency position to a low frequency position when receiving high-pass filtering signals and the clock signals, and inhibiting high-frequency interference and amplifying the input signals at a low frequency position when receiving low-pass filtering signals and the direct current bias signals.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode realizes the effects that the same circuit not only carries out high-frequency filtering and mixes high-frequency signals to a low-frequency position when receiving high-frequency signals, but also carries out low-frequency filtering and signal amplification when receiving low-frequency signals through module multiplexing, avoids the influence of stray wave signals on the communication effect of a chip, reduces the size of the chip and reduces the cost of the chip.

In some embodiments, the high/low pass filtering module includes a first high/low pass filtering unit, the first high/low pass filtering unit includes two first differential branches receiving different differential input signals in a mirror arrangement, each of the first differential branches includes:

a grounding switch;

a first filter capacitor;

a first filter resistor;

the grid electrode of the first PMOS tube is connected with the stray wave signal input end;

the grid electrode of the second PMOS tube is connected with the common-mode signal input end;

a grid electrode of the third PMOS tube is connected with an input end of an externally input bias voltage signal;

the input end of the differential input signal is respectively connected with the first end of the first PMOS tube and the first end of the third PMOS tube, the second end of the first PMOS tube is respectively connected with the first end of the second PMOS tube and the first end of the first filter resistor, the second end of the first filter resistor is respectively connected with the first end of the first filter capacitor and the signal output end of the first differential branch, and the second end of the first filter capacitor is respectively connected with the ground switch and the second end of the third PMOS tube;

and the two first differential branches arranged in a mirror image mode are connected through the second end of the second PMOS tube.

The invention provides a high-pass mode and low-pass mode reusability error correction circuit, and particularly discloses a circuit structure of a high-pass/low-pass filtering module, which realizes the technical effects of carrying out high-pass filtering on an input signal when a stray wave signal is high frequency and carrying out low-pass filtering on the input signal when the stray wave signal is low frequency.

In some embodiments, when the spurious spectrum of the spurious signal is at a high frequency, the ground switch is turned off, the gates of the second PMOS transistor and the third PMOS transistor are both at a low level, and the differential input signal is sequentially subjected to high-frequency filtering by the third PMOS transistor and the first filter capacitor and then output at the signal output end of the first differential branch;

when the stray frequency spectrum of the stray wave signal is at a low frequency, the grounding switch is closed, the gates of the second PMOS tube and the third PMOS tube are at a high level, and the differential input signal passes through the first PMOS tube and the first filter resistor in sequence, is subjected to low-frequency filtering according to the first filter capacitor connected with the grounding switch, and is output at the signal output end of the first differential branch.

In some embodiments, the high-pass/low-pass filtering module includes at least two first high-pass/low-pass filtering units, and the differential input signal input terminal of the latter first high-pass/low-pass filtering unit is connected between the first filtering capacitor and the first filtering resistor in the former first high-pass/low-pass filtering unit.

The multiplexing error correction circuit under the high-pass mode and the low-pass mode improves the filtering effect of the high-pass/low-pass filtering module by integrating a plurality of first high-pass/low-pass filtering units in the circuit structure of the high-pass/low-pass filtering module.

In some embodiments, the high-pass/low-pass filtering module comprises at least one first high-pass/low-pass filtering unit and at least one second high-pass filtering unit;

the differential input signal input end of the second high-pass filtering unit is connected between the first filtering capacitor and the first filtering resistor in the last high-pass/low-pass filtering unit;

the second high-pass filtering unit comprises two second differential branches which are arranged in a mirror image mode and used for receiving different differential input signals, and each second differential branch comprises:

a second filter capacitor;

a second filter resistor;

a grid electrode of the fourth PMOS tube is connected with the stray wave signal input end;

a grid electrode of the fifth PMOS tube is connected with the common-mode signal input end;

the input end of the differential input signal is connected with the first end of the second filter capacitor, the second end of the second filter capacitor is respectively connected with the first end of the second filter resistor and the signal output end of the second differential branch, the second end of the second filter resistor is connected with the first end of the fifth PMOS tube, and the fourth PMOS tube is connected in parallel with the two ends of the second filter capacitor;

and the two second differential branches arranged in a mirror image manner are connected through the second end of the fifth PMOS tube.

The reusability error correction circuit under the high-pass mode and the low-pass mode provided by the invention has the advantages that at least one first high-pass/low-pass filtering unit and at least one second high-pass filtering unit are sequentially integrated in the high-pass/low-pass filtering module, the circuit structures of the first high-pass/low-pass filtering unit and the second high-pass filtering unit are specifically disclosed, signals filtered by a plurality of first high-pass/low-pass filtering units are only subjected to high-pass filtering, and the cost of a chip is further reduced under the condition of ensuring the filtering effect.

In some embodiments, when the stray spectrum of the stray wave signal is at a high frequency, the gate of the fifth PMOS transistor is at a low level, and the differential input signal is output at the signal output end of the second differential branch after being high-frequency filtered by the second filter capacitor;

when the stray frequency spectrum of the stray wave signal is at a low frequency, the grid electrode of a fifth PMOS tube is at a high level, and the differential input signal is sequentially output at the signal output end of the second differential branch circuit through the fifth PMOS tube.

In some embodiments, the gate voltage of the third PMOS transistor is kept constant by a gate voltage bootstrap branch, where the gate voltage bootstrap branch includes:

a gate voltage bootstrap capacitor;

a sixth PMOS tube;

the device comprises a first linkage switch, a second linkage switch, a third linkage switch and a fourth linkage switch, wherein the opening and closing states of the first linkage switch and the second linkage switch are the same, and the opening and closing states of the third linkage switch and the fourth linkage switch are the same;

the input end of the differential input signal is connected with the source electrode of the third PMOS tube, the input end of the differential input signal sequentially passes through the first linkage switch, the grid voltage bootstrap capacitor and the second linkage switch are connected with the grid electrode of the third PMOS tube, the first linkage switch and the grid voltage bootstrap capacitor are connected with a first bias voltage signal input end through the second linkage switch, the grid voltage bootstrap capacitor and the second linkage switch are connected with a second bias voltage signal input end through the sixth PMOS tube, and the second linkage switch and the grid electrode of the third PMOS tube are connected with a third bias voltage signal input end through the fourth linkage switch.

The invention provides a reusability error correction circuit in a high-pass mode and a low-pass mode, and discloses a grid voltage bootstrap branch structure connected with a third PMOS (P-channel metal oxide semiconductor) tube in a high-pass/low-pass filtering module, which avoids the discharge of a grid voltage bootstrap capacitor in the grid voltage bootstrap branch caused by the electric leakage of the third PMOS tube, realizes the technical effect of grid voltage stabilization input of the third PMOS tube, and inhibits the nonlinearity of a signal transmission path in the high-pass/low-pass filtering module.

In some embodiments, when the gate voltage bootstrapping branch is in a reset state, the first and second ganged switches are opened, the third and fourth ganged switches are closed, the gate of the first PMOS transistor is communicated with the third bias voltage signal input end, the first PMOS transistor is in an off state, and the charging voltages at the two ends of the gate voltage bootstrapping capacitor are the voltage at the first bias voltage signal input end and the voltage at the second bias voltage signal input end respectively;

when the grid voltage bootstrap branch is in a working state, the first linkage switch and the second linkage switch are closed, the third linkage switch and the fourth linkage switch are disconnected, the grid electrode of the first PMOS tube is connected with the grid voltage bootstrap capacitor in a discharging state, and the grid voltage bootstrap capacitor is connected with the sixth PMOS tube in the discharging state.

In some embodiments, the first PMOS transistor is a PMOS transistor with adjustable cutoff frequency;

the filter coefficient of the first differential branch circuit changes along with the change of the cut-off frequency of the first PMOS tube.

In some embodiments, the timing path/dc offset module includes two third differential branches receiving different differential timing signals in a mirror arrangement, and each of the third differential branches includes:

a buffer, an input of which receives the differential timing signal and the enable signal;

the third capacitor is connected between the output end of the buffer and the signal output end of the third differential branch;

a common mode voltage signal input end connected between the third capacitor and the signal output end of the third differential branch;

the third resistor is connected between the common-mode voltage signal input end and the signal output end of the third differential branch circuit through a first node;

a fifth ganged switch connected between the third resistor and the first node;

two third differential branches arranged in a mirror image manner are connected to the common-mode voltage signal input end in parallel, the first node in one third differential branch is further connected to a third bias voltage signal input end, and the first node in the other third differential branch is further connected to a fifth bias voltage signal input end;

and a sixth linkage switch is arranged between the first node and the third bias voltage signal input end, and seventh linkage switches are arranged between the first node and the grounding end.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode disclosed by the invention discloses a circuit structure of a third differential branch circuit, which realizes the effects of carrying out level shift on a clock input signal through a buffer and a third capacitor in the high-pass mode and outputting a direct current bias signal through a common-mode voltage signal input end in the low-pass mode, and is convenient for realizing the functions of frequency mixing and amplification according to an output signal of a circuit of the third differential branch circuit.

In some embodiments, when the buffer receives the enable signal indicating that the stray wave signal is in a high frequency state, the buffer is enabled, the fifth linkage switch is closed, the sixth linkage switch and the seventh linkage switch are both opened, the differential timing signal is level-shifted through the buffer and the third capacitor, and the level-shifted clock signal is output at the signal output terminal of the third differential branch;

when the buffer receives the enable signal indicating that the stray wave signal is in a low-frequency state, the buffer is blocked, the fifth linkage switch is disconnected, the sixth linkage switch and the seventh linkage switch are both closed, one signal output end of the third differential branch outputs a first direct-current bias voltage signal, and the other signal output end of the third differential branch outputs a second direct-current bias voltage signal.

In some embodiments, the mixer amplifier module includes two fourth differential branches arranged in a mirror image, and each of the fourth differential branches includes:

a fourth bias voltage signal input;

a source of the seventh PMOS transistor is connected to the fourth bias voltage signal input terminal, and provides a bias current for the fourth differential branch;

a source of the eighth PMOS tube is connected with a drain of the seventh PMOS tube, and a gate of the eighth PMOS tube is connected with a signal output end of the high-pass/low-pass filtering module;

a source of the ninth PMOS transistor is connected to a drain of the eighth PMOS transistor, a gate of the ninth PMOS transistor is connected to a signal output end of one of the third differential branches in the timing path/dc offset module, and a drain of the ninth PMOS transistor is connected to a first signal output end of the fourth differential branch through a fourth resistor;

a source of the tenth PMOS transistor is connected to a drain of the eighth PMOS transistor, a gate of the tenth PMOS transistor is connected to a signal output end of another third differential branch in the timing path/dc bias module, and a drain of the tenth PMOS transistor is connected to the fourth resistor in another fourth differential branch in the mirror image configuration, and is connected to a first signal output end of another fourth differential branch through the fourth resistor in another fourth differential branch.

The invention provides a multiplexing error correction circuit under a high-pass mode and a low-pass mode, and particularly discloses a circuit structure diagram of a mixing amplification module.

In some embodiments, when the gate of the eighth PMOS transistor receives the high-pass filtered signal, the gates of the ninth PMOS transistor and the tenth PMOS transistor respectively receive the clock signals output by the signal outputs of the two third differential branches, and the fourth differential branch operates in a mixing mode;

when the gate of the eighth PMOS transistor receives the low-pass filtered signal, the gate of the ninth PMOS transistor receives the low-level dc bias signal, the gate of the tenth PMOS transistor receives the high-level dc bias signal, and the fourth differential branch operates in an amplification mode.

In some embodiments, the fourth differential branch further includes:

the drain electrode of the first NMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the first NMOS tube is connected with the pole voltage signal input end, and the source stage of the first NMOS tube is connected with the second signal output end of the fourth differential branch through a current source.

According to the reusability error correction circuit in the high-pass mode and the low-pass mode, the first NMOS tube is integrated in the working of the fourth differential branch, so that the transconductance of the eighth PMOS tube is increased, and the gain effect of the fourth differential branch is further increased.

In some embodiments, according to another aspect of the present invention, the present invention further provides a method for correcting multiplexing errors in a high-pass mode and a low-pass mode, comprising the steps of:

receiving a stray wave signal and an input signal, performing high-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a high frequency, and performing low-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a low frequency;

receiving a clock signal, a direct current bias signal and an enable signal, outputting the clock signal subjected to level shift when the stray wave signal is in a high-frequency state, and outputting the direct current bias signal when the stray wave signal is in a low-frequency state, wherein the enable signal is used for representing the high-low frequency state of the stray wave signal;

when receiving a high-pass filtering signal and the clock signal, suppressing a low-frequency interference signal and mixing the input signal at a high frequency to a low frequency;

suppressing high frequency interference and amplifying the input signal at low frequencies upon receiving a low pass filtered signal and the DC bias signal.

The invention provides a multiplexing error correction circuit and method under a high-pass mode and a low-pass mode, which at least have the following technical effects:

(1) Through module multiplexing, the effect that the same circuit not only carries out high-frequency filtering and mixes high-frequency signals to a low-frequency position when receiving high-frequency signals, but also carries out low-frequency filtering and signal amplification when receiving low-frequency signals is realized, the influence of stray wave signals on the communication effect of a chip is avoided, and the size and the cost of the chip are reduced;

(2) The circuit structure of the high-pass/low-pass filtering module is particularly disclosed, and the technical effects of carrying out high-pass filtering on an input signal when a stray wave signal is high frequency and carrying out low-pass filtering on the input signal when the stray wave signal is low frequency are achieved;

(3) The filtering effect of the high-pass/low-pass filtering module is improved by integrating a plurality of first disclosed high-pass/low-pass filtering units in the circuit structure of the high-pass/low-pass filtering module;

(4) The high-pass/low-pass filtering module is integrated with at least one first high-pass/low-pass filtering unit and at least one second high-pass filtering unit in sequence, and the circuit structures of the first high-pass/low-pass filtering unit and the second high-pass filtering unit are specifically disclosed, so that signals filtered by the first high-pass/low-pass filtering units are only subjected to high-pass filtering, and the cost of a chip is further reduced under the condition of ensuring the filtering effect;

(5) The grid voltage bootstrap branch structure connected with a third PMOS tube in the high-pass/low-pass filtering module is disclosed, so that the grid voltage bootstrap capacitor in the grid voltage bootstrap branch is prevented from being discharged due to the electric leakage of the third PMOS tube, the technical effect of grid voltage stabilization input of the third PMOS tube is realized, and the nonlinearity of a signal transmission path in the high-pass/low-pass filtering module is inhibited;

(6) The circuit structure of the third differential branch circuit is disclosed, level displacement is carried out on a clock input signal through a buffer and a third capacitor in a high-pass mode, and the effect of a direct-current bias signal output through a common-mode voltage signal input end is achieved in a low-pass mode, so that the functions of frequency mixing and amplification are conveniently achieved according to the output signal of the circuit of the third differential branch circuit;

(7) The circuit structure diagram of the frequency mixing amplification module integrates the frequency mixing and amplification functions into the same frequency mixing amplification module, and realizes the technical effects of executing the frequency mixing function in a high-pass mode and executing the amplification function in a low-pass mode;

(8) And the transconductance of the eighth PMOS tube is increased by integrating the first NMOS tube in the working of the fourth differential branch, so that the gain effect of the fourth differential branch is increased.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a schematic diagram of a multiplexing error correction circuit in a high pass mode and a low pass mode according to the present invention;

FIG. 2 is a schematic diagram of a high pass/low pass filter module of the multiplexing error correction circuit in the high pass mode and the low pass mode according to the present invention;

FIG. 3 is a schematic diagram of a gate bootstrapping branch in the multiplexing error correction circuit in the high pass mode and the low pass mode according to the invention when the gate bootstrapping branch is in a reset state;

FIG. 4 is a diagram of a gate bootstrapping branch in the multiplexing error correction circuit in a high pass mode and a low pass mode according to the invention;

FIG. 5 is a schematic diagram of the timing path/DC offset module of the multiplexing error correction circuit in the high pass mode and the low pass mode according to the present invention;

FIG. 6 is a schematic diagram of a mixing amplifier module in the multiplexing error correction circuit in the high-pass mode and the low-pass mode according to the present invention;

FIG. 7 is a flow chart of a method for multiplexing error correction in high-pass mode and low-pass mode according to the present invention.

Reference numbers in the figures: <xnotran> / -100, / -110, -111, -120, -121, / -200, -210, -300, -310, -S0, -C, -C1, -C2, -C3, -R1, -R2, -R3, PMOS -MP1, PMOS -MP2, PMOS -MP3, PMOS -MP4, PMOS -MP5, PMOS -MP6, PMOS -MP7, PMOS -MP8, PMOS -MP9, PMOS -MP10, NMOS -MN1, -S1, -S2, -S3, -S4, -S5, -S6, -S7, -B1, -EN, -VCM, -Vin, -Vup, -Vdn, -V3 -V4. </xnotran>

Detailed description of the preferred embodiments

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

For the sake of simplicity, only the parts relevant to the present invention are schematically shown in the drawings, and they do not represent the actual structure as a product. Moreover, in an effort to provide a concise understanding of the drawings, components having the same structure or function may be shown in some of the drawings in a single schematic representation or may be labeled in multiple representations. In this document, "a" means not only "only one of this but also a case of" more than one ".

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

In addition, in the description of the present application, the terms "first," "second," and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.

In one embodiment of the present invention, as shown in fig. 1, the present invention provides a multiplexing error correction circuit in a high-pass mode and a low-pass mode, which includes a high-pass/low-pass filtering module 100, a timing path/dc offset module 200, and a mixing amplification module 300.

Illustratively, when the sampling frequency of the transmitting end adopting the 8-channel time-domain interleaving structure is fs and the signal frequency is fin, the frequency corresponding to the stray waves is N fs/8 ± fin, where N is an integer between 0 and 8. Taking the stray wave at fs/8-fin as an example, when fin is close to fs/8, the frequency of the stray wave is close to 0; when fin is close to 0, the frequency of the spurious wave is close to fs/8. For the former case, it is necessary that the multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment operates in the low-pass filter mode to suppress the interference at the high frequency, and simultaneously, the amplifier is used to amplify the spurs at the low frequency to the post-stage module for quantization processing; for the latter case, it is necessary that the multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment operates in a high-pass filter mode to suppress interference at a low frequency, and at the same time, the mixer is used to mix spurious at a high frequency to a low frequency, and a certain gain is provided to perform quantization processing on the spurious at a later stage.

The high-pass/low-pass filtering module 100 is configured to receive a stray wave signal and an input signal, perform high-pass filtering on the input signal when a stray frequency spectrum of the stray wave signal is at a high frequency, and perform low-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a low frequency.

The timing path/dc offset module 200 is configured to receive a clock signal, a dc offset signal, and an enable signal indicating a high-frequency state and a low-frequency state of the stray wave signal, output the clock signal subjected to level shift when the stray wave signal is in the high-frequency state, and output the dc offset signal when the stray wave signal is in the low-frequency state;

the mixing amplifying module 300 is respectively connected to the high-pass/low-pass filtering module 100 and the timing path/dc offset module 200, and is configured to suppress low-frequency interference signals and mix high-frequency input signals to a low-frequency location when receiving the high-pass filtered signals and the clock signals, and suppress high-frequency interference and amplify low-frequency input signals when receiving the low-pass filtered signals and the dc offset signals.

Illustratively, when fin is close to 0, the spurious spectrum fs/8-fin is at a high frequency, the input signal is high-pass filtered by the high-pass/low-pass filtering module 100 to reach the filtering signal input end of the mixing amplifying module 300, the clock with frequency fs/8 in the timing path/dc offset module 200 reaches the signal input end of the mixing amplifying module 300, and the mixing amplifying module 300 suppresses the low-frequency interference signal and mixes the input signal at the high frequency to a low frequency;

when fin is close to fs/8, the spurious spectrum fs/8-fin is at a low frequency, the input signal is low-pass filtered by the high-pass/low-pass filtering module 100 to reach the filtering signal input end of the mixing amplification module 300, the clock path with the frequency of fs/8 in the timing path/dc bias module 200 is turned off, the timing path/dc bias module 200 provides a dc bias voltage to reach the signal input end of the mixing amplification module 300, and the mixing amplification module 300 suppresses high-frequency interference and amplifies the input signal at the low frequency.

The reusability error correction circuit in the high-pass mode and the low-pass mode provided by the embodiment realizes the effects that the same circuit not only carries out high-frequency filtering and mixes high-frequency signals to a low-frequency part when receiving high-frequency signals, but also carries out low-frequency filtering and signal amplification when receiving low-frequency signals through module multiplexing, and reduces the size and the cost of a chip while avoiding the influence of stray wave signals on the communication effect of the chip.

In an embodiment, as shown in fig. 2, the high-pass/low-pass filtering module 100 includes a first high-pass/low-pass filtering unit 110, where the first high-pass/low-pass filtering unit 110 includes two first differential branches receiving different differential input signals, and each first differential branch includes a ground switch S0, a first filtering capacitor C1, a first filtering resistor R1, a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3.

The grid of the first PMOS transistor MP1 is connected to a stray wave signal input terminal, the grid of the second PMOS transistor MP2 is connected to a common mode signal input terminal, the grid of the third PMOS transistor MP3 is connected to an externally input bias voltage signal input terminal, differential input signals are respectively connected to the first end of the first PMOS transistor MP1 and the first end of the third PMOS transistor MP3, the second end of the first PMOS transistor MP1 is respectively connected to the first end of the second PMOS transistor MP2 and the first end of the first filter resistor R1, the second end of the first filter resistor R1 is respectively connected to the first end of the first filter capacitor R1 and a signal output terminal of the first differential branch, the second end of the first filter capacitor C1 is respectively connected to the ground switch S0 and the second end of the third PMOS transistor MP3, and two first differential branches of the mirror image setting are connected to the second end of the second PMOS transistor MP 2.

Specifically, when the stray frequency spectrum of the stray wave signal is at a high frequency, the grounding switch S0 is controlled to be turned off in a numerical control manner, the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are both at a low level, the first PMOS transistor MP1 is turned off, the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned on, and the differential input signal is output at the signal output end of the first differential branch after being subjected to high-frequency filtering sequentially through the third PMOS transistor MP3 and the first filter capacitor C1.

When the stray frequency spectrum of the stray wave signal is at a low frequency, the grounding switch S0 is controlled to be closed in a numerical control mode, the grid electrode of the second PMOS tube MP2 and the grid electrode of the third PMOS tube MP3 are both at a high level, the first PMOS tube MP1 is conducted, the second PMOS tube MP2 and the third PMOS tube MP3 are cut off, the differential input signal sequentially passes through the first PMOS tube MP1 and the first filter resistor R1, and is output at the signal output end of the first differential branch circuit after low-frequency filtering is carried out according to the first filter capacitor C1 connected with the grounding switch S0.

The reusability error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment specifically discloses a circuit structure of a high-pass/low-pass filtering module, which achieves the technical effects of performing high-pass filtering on an input signal when a stray wave signal is high frequency and performing low-pass filtering on the input signal when the stray wave signal is low frequency.

In one embodiment, as shown in fig. 2, the high-pass/low-pass filtering module 100 includes at least two first high-pass/low-pass filtering units 110, and a differential input signal input terminal of a subsequent first high-pass/low-pass filtering unit 110 is connected between the first filtering capacitor C1 and the first filtering resistor R1 in the previous first high-pass/low-pass filtering unit 110.

In the multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by this embodiment, a plurality of first disclosed high-pass/low-pass filtering units are integrated in the circuit structure of the high-pass/low-pass filtering module, so that the filtering effect of the high-pass/low-pass filtering module is improved.

In one embodiment, as shown in fig. 2, the high-pass/low-pass filtering module 100 includes at least one first high-pass/low-pass filtering unit 110 and at least one second high-pass filtering unit 120, a differential input signal input end of the second high-pass filtering unit 120 is connected between a first filtering capacitor C1 and a first filtering resistor R1 in the last first high-pass/low-pass filtering unit 110, the second high-pass filtering unit 120 includes two second differential branches arranged in a mirror image manner and receiving different differential input signals, and each second differential branch includes a second filtering capacitor C2, a second filtering resistor R2, a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5.

The grid of the fourth PMOS transistor MP4 is connected to the stray wave signal input terminal, the grid of the fifth PMOS transistor MP5 is connected to the common mode signal input terminal, the differential input signal input terminal is connected to the first end of the second filter capacitor C2, the second end of the second filter capacitor C2 is connected to the first end of the second filter resistor R2 and the signal output terminal of the second differential branch, the second end of the second filter resistor R2 is connected to the first end of the fifth PMOS transistor MP5, the fourth PMOS transistor MP4 is connected in parallel to the two ends of the second filter capacitor C2, and the two second differential branches of the mirror image are connected to the second end of the fifth PMOS transistor MP5.

Specifically, when the stray spectrum of the stray wave signal is at a high frequency, the gate of the fifth PMOS transistor MP5 is at a low level, and the differential input signal is high-pass filtered by the first high-pass/low-pass filtering unit 110, high-frequency filtered by the second filtering capacitor C2 in the second high-pass/low-pass filtering unit 120, and output at the signal output end of the second differential branch.

When the stray spectrum of the stray wave signal is at a low frequency, the gate of the fifth PMOS transistor MP5 is at a high level, and the differential input signal is low-pass filtered by the first high-pass/low-pass filtering unit 110 and then directly output at the signal output end of the second differential branch through the fifth PMOS transistor MP5.

In the multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment, at least one first high-pass/low-pass filtering unit and at least one second high-pass filtering unit are sequentially integrated in the high-pass/low-pass filtering module, and the circuit structures of the first high-pass/low-pass filtering unit and the second high-pass filtering unit are specifically disclosed, so that only high-pass filtering is performed on signals filtered by the first high-pass/low-pass filtering units, and the chip cost is further reduced under the condition of ensuring the filtering effect.

In one embodiment, as shown in fig. 3 and 4, the gate voltage of the third PMOS transistor MP3 is kept constant by a gate voltage bootstrap branch, and the gate voltage bootstrap branch includes a gate voltage bootstrap capacitor C, a sixth PMOS transistor MP6, a first ganged switch S1, a second ganged switch S2, a third ganged switch S3, and a fourth ganged switch S4.

The opening and closing states of the first linkage switch S1 and the second linkage switch S2 controlled by numerical control are the same, the opening and closing states of the third linkage switch S3 and the fourth linkage switch S4 are the same, an input end Vin of a differential input signal in the grid voltage bootstrap branch is connected with a source electrode of a third PMOS tube MP3, the input end Vin of the differential input signal in the grid voltage bootstrap branch is further connected with a grid electrode of the third PMOS tube MP3 through the first linkage switch S1, a grid voltage bootstrap capacitor C and the second linkage switch S2 in sequence, the first linkage switch S1 and the grid voltage bootstrap capacitor C are connected with a first bias voltage signal input end Vup through the second linkage switch S2, a second bias voltage signal input end Vdn is connected between the grid voltage bootstrap capacitor C and the second linkage switch S2 through a sixth PMOS tube MP6, and a third bias voltage signal input end VDD is connected between the second linkage switch S2 and the grid electrode of the third PMOS tube MP3 through the fourth linkage switch S4.

Specifically, as shown in fig. 3, when the gate voltage bootstrap branch is in a reset state, the first ganged switch S1 and the second ganged switch S2 are disconnected, the third ganged switch S3 and the fourth ganged switch S4 are closed, the gate of the first PMOS transistor MP1 is connected to the third bias voltage signal input terminal VDD, the first PMOS transistor MP1 is in a turn-off state, and the charging voltages at the two ends of the gate voltage bootstrap capacitor C are respectively the voltage of the first bias voltage signal input terminal Vup and the voltage of the second bias voltage signal input terminal Vdn, so that the charging voltage of the gate voltage bootstrap capacitor C is Vup-Vdn;

as shown in fig. 4, when the gate voltage bootstrap branch is in an operating state, the first linkage switch S1 and the second linkage switch S2 are closed, the third linkage switch S3 and the fourth linkage switch S4 are disconnected, the gate of the first PMOS transistor MP1 is connected to the gate voltage bootstrap capacitor C in a discharging state, the gate voltage bootstrap capacitor C in the discharging state conducts the sixth PMOS transistor MP6, the upper plate voltage of the gate voltage bootstrap capacitor C is Vin, and the initial voltage of the lower plate is Vin-Vup + Vdn, so that the absolute value of the gate-source voltage of the first PMOS transistor MP1 is Vup-Vdn, which is irrelevant to the input voltage of the input terminal Vin of the differential input signal in the gate voltage bootstrap branch, and the weakly-opened sixth PMOS transistor MP6 is equivalent to a large resistor when being opened, when the gate voltage bootstrap capacitor C discharges charges, the voltage of the lower plate is increased, so that the weakly opened current of the sixth PMOS transistor MP6 is increased, and when the weakly opened current is equal to the current of the first PMOS transistor MP1, the gate voltage bootstrap capacitor C no longer maintains the charges on the gate voltage at both ends of the gate voltage bootstrap capacitor C, thereby maintaining the constant leakage voltage of the two ends of the gate voltage capacitor C.

The reusability error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment discloses a gate voltage bootstrap branch structure connected to the third PMOS transistor in the high-pass/low-pass filter module, so as to avoid the drain of a gate voltage bootstrap capacitor in the gate voltage bootstrap branch caused by the leakage of the third PMOS transistor, achieve the technical effect of gate voltage stabilization input of the third PMOS transistor, and suppress the nonlinearity of a signal transmission path in the high-pass/low-pass filter module.

In one embodiment, the first PMOS transistor MP1 is a PMOS transistor with adjustable cut-off frequency, and the filter coefficient of the first differential branch changes with the change of the cut-off frequency of the first PMOS transistor MP 1.

In one embodiment, as shown in fig. 5, the timing path/dc bias module 200 includes two third differential branches receiving different differential timing signals in a mirror arrangement, where each third differential branch includes a buffer B1, a third capacitor C3, a common mode voltage signal input terminal VCM, a third bias voltage signal input terminal V3, a third resistor R3, and a fifth ganged switch S5.

The input end of the buffer B1 receives a differential timing signal and an enable signal EN, the third capacitor C3 is connected between the output end of the buffer B1 and the signal output end of the third differential branch, the common-mode voltage signal input end VCM is connected between the third capacitor C3 and the signal output end of the third differential branch, the third resistor R3 is connected between the common-mode voltage signal input end VCM and the signal output end of the third differential branch through a first node, the fifth linkage switch S5 is connected between the third resistor R3 and a first node, two mirror-image third differential branches are connected in parallel to the common-mode voltage signal input end VCM, the first node in one third differential branch is further connected to a third bias voltage signal input end V3, the first node in the other third differential branch is further connected to a fifth bias voltage signal input end V5, a sixth linkage switch S6 is arranged between the first node and the third bias voltage signal input end V3, and seventh linkage switches S7 are arranged between the first node and the fifth bias voltage signal input end V5.

Specifically, when the buffer B1 receives an enable signal EN indicating that the stray wave signal is in a high-frequency state, the buffer B1 is enabled, the fifth linkage switch S5 is closed, the sixth linkage switch S6 and the seventh linkage switch are both opened, the differential timing signal is subjected to level shift through the buffer B1 and the third capacitor, and a clock signal subjected to level shift is output at a signal output end of the third differential branch; when the buffer B1 receives the enable signal EN indicating that the stray wave signal is in the low frequency state, the buffer B1 is blocked, the fifth linkage switch S5 is opened, the sixth linkage switch S6 and the seventh linkage switch are both closed, the signal output terminal LON of the third differential branch is combined with the third bias voltage signal input terminal V3 and the common mode voltage signal input terminal VCM to output a first dc bias voltage signal at a high level, and the signal output terminal LOP of the third differential branch is combined with the fifth bias voltage signal input terminal V5 and the common mode voltage signal input terminal VCM to output a second dc bias voltage signal at a low level.

The reusability error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment discloses a circuit structure of a third differential branch, which implements level shifting of a clock input signal through a buffer and a third capacitor in the high-pass mode, and implements the effect of a dc bias signal output through a common-mode voltage signal input end in the low-pass mode, so as to implement the functions of frequency mixing and amplification according to an output signal of a circuit of the third differential branch.

In one embodiment, as shown in fig. 6, the mixer amplifier module 300 includes two fourth differential branches arranged in a mirror image manner, and each of the fourth differential branches includes a fourth bias voltage signal input terminal V4, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and a tenth PMOS transistor MP10.

A source of the seventh PMOS transistor MP7 is connected to the fourth bias voltage signal input terminal V4 to provide a bias current for the fourth differential branch, a source of the eighth PMOS transistor MP8 is connected to a drain of the seventh PMOS transistor MP7, a gate of the eighth PMOS transistor MP8 is connected to a signal output terminal of the high-pass/low-pass filter module 100, a source of the ninth PMOS transistor MP9 is connected to a drain of the eighth PMOS transistor MP8, a gate of the ninth PMOS transistor MP9 is connected to a signal output terminal of one third differential branch of the timing path/dc bias module 200, a drain of the ninth PMOS transistor MP9 is connected to a first signal output terminal of the fourth differential branch via a fourth resistor R4, a source of the tenth PMOS transistor MP10 is connected to a drain of the eighth PMOS transistor MP8, a gate of the tenth PMOS transistor MP10 is connected to a signal output terminal of a third differential branch of the timing path/dc bias module 200, a drain of the tenth PMOS transistor MP10 is connected to a fourth differential branch of the other fourth differential branch of the mirror image setting, and is connected to another signal output terminal of the fourth differential branch via another fourth differential resistor R4.

Specifically, when the gate of the eighth PMOS transistor MP8 receives the high-pass filtered signal, the gates of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 respectively receive the clock signals output by the signal output terminals of the two third differential branches, and the fourth differential branch operates in the frequency mixing mode.

When the gate of the eighth PMOS transistor MP8 receives the low-pass filtered signal, the gate of the ninth PMOS transistor MP9 receives the low-level dc bias signal, the gate of the tenth PMOS transistor MP10 receives the high-level dc bias signal, and the fourth differential branch operates in the amplifying mode.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment specifically discloses a circuit structure diagram of a mixing amplification module, and integrates mixing and amplification functions in the same mixing amplification module, so as to achieve the technical effects of executing the mixing function in the high-pass mode and executing the amplification function in the low-pass mode.

In some embodiments, as shown in fig. 6, the fourth differential branch further includes a first NMOS transistor MN1 therein.

The drain electrode of the first NMOS transistor MN1 is connected to the drain electrode of the eighth PMOS transistor MP8, the gate electrode of the first NMOS transistor MN1 is connected to the pole voltage signal input terminal, and the source of the first NMOS transistor MN1 is connected to the second signal output terminal of the fourth differential branch via the current source.

In the multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment, the first NMOS transistor is integrated in the fourth differential branch circuit, so that the transconductance of the eighth PMOS transistor is increased, and further, the gain effect of the fourth differential branch circuit is increased.

In one embodiment, as shown in fig. 7, according to another aspect of the present invention, the present invention further provides a method for correcting multiplexing errors in a high-pass mode and a low-pass mode, comprising the steps of:

s100, receiving a stray wave signal and an input signal, carrying out high-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a high frequency, and carrying out low-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a low frequency.

S200 receives the clock signal, the DC bias signal and the enable signal, outputs the clock signal after level shift when the stray wave signal is in a high-frequency state, and outputs the DC bias signal when the stray wave signal is in a low-frequency state.

Specifically, the enable signal is used to indicate the high and low frequency states of the stray wave signal, wherein the steps S100 and S200 are not limited in sequence.

S310 suppresses the low frequency interference signal and mixes the input signal at the high frequency to the low frequency while receiving the high pass filtered signal and the clock signal.

S320 suppresses high frequency interference and amplifies the input signal at low frequency when receiving the low pass filtered signal and the dc offset signal.

Illustratively, when the sampling frequency of the transmitting end adopting the 8-channel time-domain interleaving structure is fs and the signal frequency is fin, the frequency corresponding to the stray waves is N fs/8 ± fin, where N is an integer between 0 and 8. Taking the stray wave at fs/8-fin as an example, when fin is close to fs/8, the frequency of the stray wave is close to 0; when fin is close to 0, the frequency of the spurious wave is close to fs/8. For the former case, the interference at the high frequency is required to be suppressed, and the spurious at the low frequency is amplified by the amplifier and is quantized by the post-stage module; in the latter case, it is necessary to suppress the interference at the low frequency, and simultaneously use the mixer to mix the spurious at the high frequency to the low frequency, and provide a certain gain to the subsequent module for quantization processing.

When fin is close to 0, stray spectrum fs/8-fin is located at a high frequency, an input signal passes through high-pass filtering, according to a clock with the frequency of fs/8, a low-frequency interference signal is suppressed and the input signal at the high frequency is mixed to a low frequency, when fin is close to fs/8, stray spectrum fs/8-fin is located at a low frequency, the input signal passes through low-pass filtering, a clock path is cut off, and according to a direct-current bias voltage, high-frequency interference is suppressed and the input signal at the low frequency is amplified.

The reusability error correction method in the high-pass mode and the low-pass mode provided by this embodiment achieves the effects that the same circuit performs high-frequency filtering and mixes high-frequency signals to a low frequency when receiving high-frequency signals, and performs low-frequency filtering and signal amplification when receiving low-frequency signals, thereby reducing the chip size and chip cost while avoiding the influence of stray wave signals on the chip communication effect.

In the foregoing embodiments, the descriptions of the respective embodiments have their respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or recited in detail in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed direct fractional division circuit and method can be implemented in other ways. For example, the above-described direct fractional division circuit and method embodiments are merely illustrative, and for example, the division of the modules or units is only a logical division, and there may be other divisions when actually implemented, for example, a plurality of units or modules may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the communication links shown or discussed may be through interfaces, devices or units, or integrated circuits, and may be electrical, mechanical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

It should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (15)

1. A multiplexing error correction circuit in a high pass mode and a low pass mode, comprising:

the high-pass/low-pass filtering module is used for receiving a stray wave signal and an input signal, carrying out high-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a high frequency, and carrying out low-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a low frequency;

the timing path/direct current bias module is used for receiving a clock signal, a direct current bias signal and an enable signal representing the high-low frequency state of the stray wave signal, outputting the clock signal subjected to level shift when the stray wave signal is in the high-frequency state, and outputting the direct current bias signal when the stray wave signal is in the low-frequency state;

and the frequency mixing amplification module is respectively connected with the high-pass/low-pass filtering module and the time sequence path/direct current offset module, and is used for inhibiting low-frequency interference signals and mixing the input signals at a high frequency position to a low frequency position when receiving high-pass filtering signals and the clock signals, and inhibiting high-frequency interference and amplifying the input signals at the low frequency position when receiving low-pass filtering signals and the direct current offset signals.

2. A multiplexing error correction circuit in high-pass mode and low-pass mode according to claim 1, wherein the high-pass/low-pass filtering module comprises a first high-pass/low-pass filtering unit, the first high-pass/low-pass filtering unit comprises two first differential branches receiving different differential input signals and arranged in a mirror image manner, each of the first differential branches comprises:

a grounding switch;

a first filter capacitor;

a first filter resistor;

the grid electrode of the first PMOS tube is connected with the stray wave signal input end;

the grid electrode of the second PMOS tube is connected with the common-mode signal input end;

the grid electrode of the third PMOS tube is connected with an externally input bias voltage signal input end;

the input end of the differential input signal is respectively connected with the first end of the first PMOS tube and the first end of the third PMOS tube, the second end of the first PMOS tube is respectively connected with the first end of the second PMOS tube and the first end of the first filter resistor, the second end of the first filter resistor is respectively connected with the first end of the first filter capacitor and the signal output end of the first differential branch, and the second end of the first filter capacitor is respectively connected with the ground switch and the second end of the third PMOS tube;

and the two first differential branches arranged in a mirror image manner are connected through the second end of the second PMOS tube.

3. The circuit of claim 2, wherein the error correction circuit is further configured to correct the error between the high-pass mode and the low-pass mode,

when the stray frequency spectrum of the stray wave signal is at a high frequency, the grounding switch is switched off, the gates of the second PMOS tube and the third PMOS tube are at a low level, and the differential input signal is output at the signal output end of the first differential branch after sequentially passing through the third PMOS tube and the first filter capacitor for high-frequency filtering;

when the stray frequency spectrum of the stray wave signal is at a low frequency, the grounding switch is closed, the gates of the second PMOS tube and the third PMOS tube are at a high level, and the differential input signal sequentially passes through the first PMOS tube and the first filter resistor, is subjected to low-frequency filtering according to the first filter capacitor connected with the grounding switch, and is output at the signal output end of the first differential branch.

4. The multiplexing error correction circuit in high pass mode and low pass mode of any of claims 2 or 3,

the high-pass/low-pass filtering module comprises at least two first high-pass/low-pass filtering units, and the differential input signal input end of the latter first high-pass/low-pass filtering unit is connected between the first filtering capacitor and the first filtering resistor in the former first high-pass/low-pass filtering unit.

5. The circuit of claim 4, wherein the error correction circuit is further configured to correct the multiplexing errors in the high-pass mode and the low-pass mode,

the high-pass/low-pass filtering module comprises at least one first high-pass/low-pass filtering unit and at least one second high-pass filtering unit;

the differential input signal input end of the second high-pass filtering unit is connected between the first filtering capacitor and the first filtering resistor in the last high-pass/low-pass filtering unit;

the second high-pass filtering unit comprises two second differential branches which are arranged in a mirror image mode and used for receiving different differential input signals, and each second differential branch comprises:

a second filter capacitor;

a second filter resistor;

a grid electrode of the fourth PMOS tube is connected with the stray wave signal input end;

a grid electrode of the fifth PMOS tube is connected with the common-mode signal input end;

the input end of the differential input signal is connected with the first end of the second filter capacitor, the second end of the second filter capacitor is respectively connected with the first end of the second filter resistor and the signal output end of the second differential branch, the second end of the second filter resistor is connected with the first end of the fifth PMOS tube, and the fourth PMOS tube is connected to the two ends of the second filter capacitor in parallel;

and the two second differential branches arranged in a mirror image manner are connected through the second end of the fifth PMOS tube.

6. The circuit of claim 5, wherein the error correction circuit is further configured to correct the error between the high-pass mode and the low-pass mode,

when the stray frequency spectrum of the stray wave signal is at a high frequency, the grid electrode of a fifth PMOS tube is at a low level, and the differential input signal is output at the signal output end of the second differential branch circuit after being subjected to high-frequency filtering by the second filter capacitor;

when the stray frequency spectrum of the stray wave signal is at a low frequency, the grid electrode of a fifth PMOS tube is at a high level, and the differential input signal is output at the signal output end of the second differential branch circuit through the fifth PMOS tube.

7. The multiplexing error correction circuit in high-pass mode and low-pass mode according to any one of claims 2 or 3, wherein the gate voltage of the third PMOS transistor is kept constant by a gate voltage bootstrap branch, and the gate voltage bootstrap branch comprises:

a gate voltage bootstrap capacitor;

a sixth PMOS tube;

the device comprises a first linkage switch, a second linkage switch, a third linkage switch and a fourth linkage switch, wherein the opening and closing states of the first linkage switch and the second linkage switch are the same, and the opening and closing states of the third linkage switch and the fourth linkage switch are the same;

the input end of the differential input signal is connected with the source electrode of the third PMOS tube, the input end of the differential input signal sequentially passes through the first linkage switch, the grid voltage bootstrap capacitor and the second linkage switch are connected with the grid electrode of the third PMOS tube, the first linkage switch and the grid voltage bootstrap capacitor are connected with a first bias voltage signal input end through the second linkage switch, the grid voltage bootstrap capacitor and the second linkage switch are connected with a second bias voltage signal input end through the sixth PMOS tube, and the second linkage switch and the grid electrode of the third PMOS tube are connected with a third bias voltage signal input end through the fourth linkage switch.

8. The circuit of claim 7, wherein the error correction circuit is further configured to correct the error between the high-pass mode and the low-pass mode,

when the gate voltage bootstrap branch is in a reset state, the first linkage switch and the second linkage switch are disconnected, the third linkage switch and the fourth linkage switch are closed, the gate of the first PMOS transistor is communicated with the third bias voltage signal input end, the first PMOS transistor is in a turn-off state, and the charging voltages at two ends of the gate voltage bootstrap capacitor are respectively the voltage at the first bias voltage signal input end and the voltage at the second bias voltage signal input end;

when the grid voltage bootstrap branch is in a working state, the first linkage switch and the second linkage switch are closed, the third linkage switch and the fourth linkage switch are disconnected, the grid electrode of the first PMOS tube is connected with the grid voltage bootstrap capacitor in a discharging state, and the grid voltage bootstrap capacitor is connected with the sixth PMOS tube in the discharging state.

9. The multiplexing error correction circuit in high pass mode and low pass mode of any of claims 2 or 3,

the first PMOS tube is a PMOS tube with adjustable cut-off frequency;

the filter coefficient of the first differential branch circuit changes along with the change of the cut-off frequency of the first PMOS tube.

10. The circuit of claim 1, wherein the timing path/dc offset module comprises two third differential branches receiving different differential timing signals, and each of the third differential branches comprises:

a buffer having an input receiving the differential timing signal and the enable signal;

the third capacitor is connected between the output end of the buffer and the signal output end of the third differential branch;

a common mode voltage signal input end connected between the third capacitor and the signal output end of the third differential branch;

the third resistor is connected between the common-mode voltage signal input end and the signal output end of the third differential branch circuit through a first node;

a fifth ganged switch connected between the third resistor and the first node;

two third differential branches arranged in a mirror image manner are connected in parallel to the common-mode voltage signal input end, the first node in one third differential branch is further connected to a third bias voltage signal input end, and the first node in the other third differential branch is further connected to a fifth bias voltage signal input end;

and a sixth linkage switch is arranged between the first node and the third bias voltage signal input end, and seventh linkage switches are arranged between the first node and the grounding end.

11. The circuit of claim 10, wherein the error correction circuit is further configured to correct the error between the high-pass mode and the low-pass mode,

when the buffer receives the enable signal indicating that the stray wave signal is in a high-frequency state, the buffer is enabled, the fifth linkage switch is closed, the sixth linkage switch and the seventh linkage switch are both opened, the differential timing signal is subjected to level shift through the buffer and the third capacitor, and the clock signal subjected to level shift is output at the signal output end of the third differential branch;

when the buffer receives the enable signal indicating that the stray wave signal is in a low-frequency state, the buffer is blocked, the fifth linkage switch is disconnected, the sixth linkage switch and the seventh linkage switch are both closed, one signal output end of the third differential branch outputs a first direct-current bias voltage signal, and the other signal output end of the third differential branch outputs a second direct-current bias voltage signal.

12. The circuit of claim 10, wherein the mixer amplifier module comprises two fourth differential branches arranged in a mirror manner, and each of the fourth differential branches comprises:

a fourth bias voltage signal input;

a source of the seventh PMOS transistor is connected to the fourth bias voltage signal input terminal, and provides a bias current for the fourth differential branch;

a source of the eighth PMOS transistor is connected to a drain of the seventh PMOS transistor, and a gate of the eighth PMOS transistor is connected to a signal output end of the high-pass/low-pass filtering module;

a source of the ninth PMOS transistor is connected to a drain of the eighth PMOS transistor, a gate of the ninth PMOS transistor is connected to a signal output end of one of the third differential branches in the timing path/dc offset module, and a drain of the ninth PMOS transistor is connected to a first signal output end of the fourth differential branch through a fourth resistor;

a source of the tenth PMOS transistor is connected to a drain of the eighth PMOS transistor, a gate of the tenth PMOS transistor is connected to a signal output end of another third differential branch in the timing path/dc bias module, and a drain of the tenth PMOS transistor is connected to the fourth resistor in another fourth differential branch in the mirror image configuration, and is connected to a first signal output end of another fourth differential branch through the fourth resistor in another fourth differential branch.

13. The circuit of claim 12, wherein the error correction circuit is further configured to correct the error between the high-pass mode and the low-pass mode,

when the grid electrode of the eighth PMOS tube receives the high-pass filtering signal, the grid electrodes of the ninth PMOS tube and the tenth PMOS tube respectively receive the clock signals output by the signal output ends of the two third differential branches, and the fourth differential branch works in a frequency mixing mode;

when the gate of the eighth PMOS transistor receives the low-pass filtered signal, the gate of the ninth PMOS transistor receives the low-level dc bias signal, the gate of the tenth PMOS transistor receives the high-level dc bias signal, and the fourth differential branch operates in an amplification mode.

14. The multiplexing error correction circuit in high pass mode and low pass mode according to any of claims 12 or 13, wherein the fourth differential branch further comprises:

the drain electrode of the first NMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the first NMOS tube is connected with the pole voltage signal input end, and the source stage of the first NMOS tube is connected with the second signal output end of the fourth differential branch through a current source.

15. A method for multiplexing error correction in a high pass mode and a low pass mode, comprising the steps of:

receiving a stray wave signal and an input signal, performing high-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a high frequency, and performing low-pass filtering on the input signal when the stray frequency spectrum of the stray wave signal is at a low frequency;

receiving a clock signal, a direct current bias signal and an enable signal, outputting the clock signal subjected to level shift when the stray wave signal is in a high-frequency state, and outputting the direct current bias signal when the stray wave signal is in a low-frequency state, wherein the enable signal is used for representing the high-low frequency state of the stray wave signal;

suppressing a low frequency interference signal and mixing the input signal at a high frequency to a low frequency while receiving a high pass filtered signal and the clock signal;

suppressing high frequency interference and amplifying the input signal at low frequencies upon receiving a low pass filtered signal and the DC bias signal.

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