CN115940594A - Adaptive turn-off time and phase delay control circuit for multiphase DC-DC converter - Google Patents

Abstract

Embodiments of the present disclosure provide an adaptive turn-off time and phase delay control circuit for a multiphase DC-DC converter, comprising: a plurality of cascaded control sub-circuits. And the ith-stage control sub-circuit generates the PWM signal of the ith phase under the control of the PWM signal of the ith-1 phase, the inductive current peak signal of the ith phase and the system switching frequency signal. And if the PWM signal of the ith phase is at the first level when the first preset time is reached after the PWM signal of the ith-1 phase is inverted from the second level to the first level, controlling the time length of the next time that the PWM signal of the ith phase is at the second level to be equal to the minimum turn-off time of the multi-phase DC-DC converter. The first-stage control sub-circuit controls the PWM signal of the main phase to transition from the first level to the second level when the main-phase inductor current peak signal transitions from the second level to the first level, and to transition from the second level to the first level after a longer time of the adaptive turn-off time and the minimum turn-off time elapses. i is an integer greater than 1.

Description

Adaptive turn-off time and phase delay control circuit for multiphase DC-DC converter

Technical Field

Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to an adaptive turn-off time and phase delay control circuit for a multiphase DC-DC converter.

Background

DC-DC (direct current-direct current) converters are often used for converting a direct current voltage in various electronic devices. In current multiphase DC-DC converters (which may also be referred to in this context as multiphase control systems alternatively), when the main phase loop is designed in an adaptive on or off time control mode, the secondary phase loop may achieve an even distribution of power stage energy in a sequential time-delayed control manner. Taking a multi-phase control system with a main phase loop designed as an adaptive turn-off time control mode as an example, the first and second phases use the rising edge of a main phase PWM (pulse width modulation) signal as a clock signal for turning on the upper power tube and turning off the lower power tube in their own loop, and turn off the upper power tube and turn on the lower power tube when the peak value of their own inductor current reaches the amplitude of the error amplification signal, thereby completing loop regulation of each period. Similarly, the (i + 1) th secondary phase also uses the rising edge of the PWM signal of the (i) th secondary phase as a clock signal for turning on the upper power tube and turning off the lower power tube in its own loop, and turns off the upper power tube and turns on the lower power tube when the peak value of the self inductor current reaches the amplitude of the error amplification signal, thereby completing loop regulation of each period. Based on the above principle, all the secondary phases except the primary phase follow the control pattern of the peak current mode. Therefore, each phase loop needs to introduce a slope compensation circuit so as to avoid subharmonic oscillation of the system in the application with the duty ratio larger than 50% on the premise of keeping the energy balance of the power level.

Disclosure of Invention

Embodiments described herein provide an adaptive turn-off time and phase delay control circuit for a multiphase DC-DC converter, and a multiphase DC-DC converter.

According to a first aspect of the present disclosure, an adaptive turn-off time and phase delay control circuit for a multiphase DC-DC converter is provided. The adaptive turn-off time and phase delay control circuit comprises: a plurality of cascaded control sub-circuits. Wherein the ith stage control sub-circuit is configured to: and generating the PWM signal of the ith phase under the control of the PWM signal of the ith-1 phase output by the ith-1 stage control sub-circuit, the inductive current peak signal of the ith phase and the system switching frequency signal. And if the PWM signal of the ith phase is at the first level when the PWM signal of the ith-1 phase reaches a first preset time after the PWM signal of the ith phase is inverted from the second level to the first level, controlling the time length of the next time that the PWM signal of the ith phase is at the second level to be equal to the minimum turn-off time of the multi-phase DC-DC converter. Wherein the first stage control sub-circuit is configured to: the PWM signal controlling the main phase is flipped from the first level to the second level when the main phase inductor current peak signal is flipped from the second level to the first level, and from the second level to the first level after a longer time of the adaptive off-time and the minimum off-time has elapsed. Wherein the adaptive off-time is determined from the system switching frequency signal. Wherein i is an integer greater than 1.

In some embodiments of the present disclosure, if the PWM signal of the i-th phase is at the second level when a first preset time is reached after the PWM signal of the i-1-th phase is inverted from the second level to the first level, the PWM signal of the i-th phase is controlled to be inverted from the second level to the first level.

In some embodiments of the present disclosure, the ith stage control sub-circuit comprises: the circuit comprises an ith-stage trigger circuit, an ith-stage first delay circuit, an ith-stage setting control circuit, an ith-stage first RS trigger, an ith-stage state recording circuit and an ith-stage reset circuit. Wherein the ith stage trigger circuit is configured to: and generating an ith trigger signal according to the PWM signal of the ith-1 phase and an ith reset signal from the ith stage reset circuit. The ith trigger signal is turned to the first level when the PWM signal of the ith-1 phase is turned from the second level to the first level, and is at the second level when the ith reset signal is at the effective level. The ith stage first delay circuit is configured to: and generating an ith phase delay indication signal according to the ith trigger signal. The ith phase delay indicating signal is turned from the second level to the first level when a first preset time is reached after the ith trigger signal is turned from the second level to the first level, and is turned from the first level to the second level after the ith trigger signal is turned from the first level to the second level. The ith-stage set control circuit is configured to: and generating an ith set signal according to the ith phase delay indication signal and the ith phase PWM signal. And the ith set signal is at an effective level under the condition that the time when the ith phase delay indication signal is at a first level and the PWM signal of the ith phase is at a second level reaches the minimum turn-off time. The set end of the ith stage first RS flip-flop is provided with an ith set signal. The reset end of the ith stage first RS trigger is provided with an inductive current peak signal of the ith phase. And outputting the ith-phase PWM signal from the non-inverting output end of the ith-stage first RS trigger. The i-th stage state recording circuit is configured to: and generating an ith state indicating signal according to the PWM signal of the ith phase and the ith phase delay indicating signal. And the ith state indicating signal is at the first level when the ith phase delay indicating signal is at the first level, and is inverted to the second level when a second preset time is reached after the ith phase PWM signal is inverted to the first level. The ith-stage reset circuit is configured to: and generating an ith reset signal according to the ith phase delay indication signal, the ith phase PWM signal and the ith state indication signal. And the ith reset signal is turned to an active level when third preset time is reached after the ith phase delay indication signal, the ith phase PWM signal and the ith state indication signal are all at the first level, and is at an inactive level when any one of the ith phase delay indication signal, the ith phase PWM signal and the ith state indication signal is at the second level.

In some embodiments of the present disclosure, the ith stage trigger circuit includes: an ith stage D flip-flop. And the data input end of the ith-stage D flip-flop is coupled with the inverted output end of the ith-stage D flip-flop. The clock signal terminal of the ith stage D flip-flop is supplied with the PWM signal of the (i-1) th phase. The reset end of the ith-stage D flip-flop is coupled with the output end of the ith-stage reset circuit. The non-inverting output end of the ith stage D flip-flop is coupled with the input end of the ith stage first delay circuit.

In some embodiments of the present disclosure, the ith stage set control circuit includes: the circuit comprises an ith stage first AND gate, an ith stage first inverter and an ith stage minimum turn-off time delay circuit. And the first input end of the ith stage first AND gate is coupled with the output end of the ith stage first delay circuit. And the second input end of the ith stage first AND gate is coupled to the output end of the ith stage minimum turn-off time delay circuit. The output end of the ith-stage first AND gate is coupled to the set end of the ith-stage first RS trigger. The input end of the ith stage first inverter is coupled with the non-inverting output end of the ith stage first RS trigger. The output end of the ith stage first inverter is coupled with the input end of the ith stage minimum turn-off time delay circuit. The ith stage minimum off-time delay circuit is configured to: controlling its output signal to be inverted to a first level when a minimum off time is reached after its input signal is inverted to the first level, and controlling its output signal to be at a second level if its input signal is at the second level.

In some embodiments of the present disclosure, the ith stage state recording circuit includes: the second delay circuit of the ith stage and the second RS trigger of the ith stage. Wherein the ith stage second delay circuit is configured to: and controlling the output signal of the ith phase to be inverted to the first level when a second preset time is reached after the PWM signal of the ith phase is inverted from the second level to the first level, and controlling the output signal of the ith phase to be at the second level when the PWM signal of the ith phase is at the second level. And the set end of the ith-stage second RS trigger is coupled with the output end of the ith-stage first delay circuit. And the reset end of the ith-stage second RS trigger is coupled with the output end of the ith-stage second delay circuit. And outputting an ith state indication signal from a non-inverting output end of the ith stage second RS trigger.

In some embodiments of the present disclosure, the ith stage second delay circuit includes: the second inverter of the ith stage, the third inverter of the ith stage and the capacitor of the ith stage. And the input end of the ith stage second inverter is coupled with the non-inverting output end of the ith stage first RS trigger. The output end of the ith stage second inverter is coupled with the input end of the ith stage third inverter. The output end of the ith stage third inverter is coupled with the first end of the ith stage capacitor and the output end of the ith stage second delay circuit. The second terminal of the ith stage capacitor is coupled to the second voltage terminal.

In some embodiments of the present disclosure, the ith stage reset circuit includes: the first and second delay circuit comprises an ith stage, a second AND gate, an ith stage, a third delay circuit and an ith stage fourth inverter. And the first input end of the ith stage second AND gate is coupled with the output end of the ith stage first delay circuit. And the second input end of the ith stage second AND gate is coupled with the non-inverting output end of the ith stage first RS trigger. And the third input end of the ith stage second AND gate is coupled with the output end of the ith stage state recording circuit. And the output end of the second AND gate of the ith stage is coupled with the input end of the third delay circuit of the ith stage. The ith stage third delay circuit is configured to: and delaying the input signal for a third preset time and then outputting the delayed input signal. The input end of the ith stage fourth inverter is coupled to the output end of the ith stage third delay circuit. An ith reset signal is output from an output terminal of the ith stage fourth inverter.

In some embodiments of the disclosure, the first stage control sub-circuit comprises: the self-adaptive turn-off time control circuit comprises a main phase inverter, a main phase AND gate, a main phase RS trigger, a self-adaptive turn-off time calculation circuit and a main phase minimum turn-off time control circuit. Wherein the adaptive off-time computation circuit is configured to: an adaptive turn-off time is calculated from the system switching frequency signal and a signal at a first level is output when the adaptive turn-off time is reached after the PWM signal of the main phase is inverted from the first level to a second level. The main phase minimum off-time control circuit is configured to: the signal at the first level is output when a minimum off-time is reached after its input signal is inverted from the second level to the first level. The input end of the main phase inverter is coupled with the in-phase output end of the main phase RS trigger. The output end of the main phase inverter is coupled with the input end of the main phase minimum turn-off time control circuit. The first input end of the main phase AND gate is coupled with the output end of the self-adaptive turn-off time calculation circuit. The first input end of the main phase AND gate is coupled with the output end of the main phase minimum turn-off time control circuit. The output end of the main phase AND gate is coupled with the position end of the main phase RS trigger. The reset terminal of the main phase RS trigger is provided with a main phase inductive current peak value signal. And outputting the PWM signal of the main phase from the in-phase output end of the main phase RS trigger.

According to a second aspect of the present disclosure, a multiphase DC-DC converter is provided. The multiphase DC-DC converter includes an adaptive off-time and phase delay control circuit according to the first aspect of the disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, it being understood that the drawings described below relate only to some embodiments of the present disclosure, and not to limit the present disclosure, wherein:

FIG. 1 is an exemplary circuit diagram of a multiphase DC-DC converter;

FIG. 2 is an exemplary circuit diagram of the slope compensation circuit of FIG. 1;

FIG. 3 is an exemplary circuit diagram of the adaptive turn-off time and phase delay control circuit of FIG. 1;

FIG. 4 is a timing diagram of some of the signals for the multiphase DC to DC converter shown in FIG. 1;

FIG. 5 is a timing diagram of some signals for a multiphase DC to DC converter including the adaptive turn-off time and phase delay control circuit shown in FIG. 3;

FIG. 6 is a schematic block diagram of an adaptive turn-off time and phase delay control circuit for a multiphase DC-DC converter in accordance with an embodiment of the present disclosure;

FIG. 7 is a schematic block diagram of a first stage control sub-circuit in the adaptive off-time and phase delay control circuit shown in FIG. 6;

FIG. 8 is a schematic block diagram of the ith stage control subcircuit in the adaptive off-time and phase delay control circuit shown in FIG. 6;

FIG. 9 is an exemplary circuit diagram of the ith stage control sub-circuit shown in FIG. 8; and

fig. 10 is a timing diagram of some signals for a multi-phase DC-DC converter including the adaptive turn-off time and phase delay control circuit shown in fig. 6.

It should be noted that the elements in the figures are schematic and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are also within the scope of protection of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components.

In all embodiments of the present disclosure, since the source and the drain of a Metal Oxide Semiconductor (MOS) transistor are symmetric and the on-currents between the source and the drain of an N-type transistor and a P-type transistor are opposite in direction, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control electrode, and the remaining two terminals of the MOS transistor are referred to as a first electrode and a second electrode, respectively. The transistors employed in the embodiments of the present disclosure are primarily switching transistors. In addition, terms such as "first" and "second" are only used to distinguish one element (or part of an element) from another element (or another part of an element).

Fig. 1 shows an exemplary circuit diagram of a multiphase DC-DC converter. The multiphase DC-DC converter is used to convert an input voltage VIN to an output voltage VOUT. The multiphase DC-DC converter includes: the driving circuit includes a plurality of driving circuits (including a first driving circuit, a second driving circuit, \ 8230; \ 8230;, an ith driving circuit, and an ith +1 driving circuit), a plurality of upper power transistors S1_1, S1_2, \ 8230; \ 8230; S1_ i, S1_ i +1, a plurality of lower power transistors S2_1, S2_2, \ 8230, S2_ i, S2_ i +1, a plurality of inductors L1, L2, \ 8230; \ 8230;, li, li +1, a plurality of sampling resistors Ri (each corresponding to one sampling resistor), a superimposing circuit, an output capacitor COUT, a resistor r1, a resistor r2, an error amplifier EA, a PWM comparator COMP, a self-adaptive off time and phase delay control circuit 110, and a slope compensation circuit 120. Also shown in fig. 1 is a load ILOAD.

The adaptive off-time and phase delay control circuit 110 outputs PWM signals PWM _ i of each phase, and controls the on/off of the upper power transistor and the lower power transistor through each corresponding driving circuit. Sampling resistors Ri of each phase sample the inductor currents IL1, IL2, 8230, ILi 821, li and Li +1 of the corresponding inductor L1, L2, 8230, ILi and ILi +1, and generate an inductor current peak sampling signal VCS _ i of each phase. The slope compensation circuit 120 is coupled to the superposition circuit through a node O _ i. The superimposing circuit may superimpose the inductor current peak sampling signal VCS _ i of each phase and the slope compensation signal output by the slope compensation circuit 120 to generate the superimposed signal VSUM _ i.

The non-inverting input terminal of the error amplifier EA is coupled to the reference voltage terminal VREF, and the inverting input terminal of the error amplifier EA is coupled to the feedback node FB. The error amplifier EA is capable of amplifying an error voltage between a reference voltage from the reference voltage terminal VREF and a feedback voltage at the feedback node FB, and providing an error amplification signal EAO to the PWM comparator COMP. The peak inductor current signal IPEAK _ i output by the PWM comparator COMP may control the adaptive turn-off time and phase delay control circuit 110 to generate a corresponding PWM signal PWM _ i. When the superimposed signal VSUM _ i reaches the error amplification signal EAO, the PWM comparator COMP outputs an inductor current peak signal IPEAK _ i of a high level to control the i-th phase PWM signal PWM _ i to be inverted to a low level. Fig. 4 shows a relationship diagram of the superimposed signal VSUM _ i, the error amplification signal EAO, and the inductor current peak signal IPEAK _ i.

Fig. 2 illustrates an exemplary circuit diagram of the slope compensation circuit 220 in fig. 1. The slope compensation circuit 220 includes a plurality of cascaded slope compensation subcircuits. Since the structure of each slope compensation sub-circuit is the same, for ease of illustration, only one exemplary circuit structure of a slope compensation sub-circuit is shown in fig. 2. In the example of FIG. 2, i represents the phase order to which the current PWM signal corresponds, where i ≧ 1. In case i equals 1, the current phase is the main phase. In the case where i is equal to 2, the current phase is the first sub-phase. And so on.

The PWM signal PWM _ i may be input to the rise time control circuit. The rise time control circuit is, for example, a delay circuit. For example, the rising time control circuit may start timing from a rising edge of the PWM signal PWM _ i, and after a period of time expires, the output signal of the rising time control circuit is inverted to a low level, thereby controlling the and gate ANDi to output a low level signal. The low level signal is input to the inverter NGi, so that the inverter NGi outputs the high level signal. The high level signal controls transistor Mi to turn on, releasing the charge stored on capacitor Ci.

The current source IBIASi may output a fixed bias current. In each switching period of the ith phase, when the upper power tube S1_ i is turned on and the lower power tube S2_ i is turned off, the PWM signal PWM _ i is inverted from low level to high level, so that the transistor Mi is turned off. The current source IBIASi charges the capacitor Ci, and generates a ramp voltage signal VRAMP _ i on the upper plate of the capacitor Ci. The ramp voltage signal VRAMP _ i is input to the voltage controlled current source VCCSi, where Gi is the gain of the voltage controlled current source VCCSi. The voltage-controlled current source VCCSi converts the ramp voltage signal VRAMP _ i into a ramp current signal IRAMP _ i. The ramp current signal IRAMP _ i may be superimposed with the inductor current peak sampling signal VCS _ i through a resistor Ri to generate a superimposed signal VSUM _ i. The timing duration of the rising time control circuit determines the duration of the ramp voltage signal VRAMP _ i from the beginning to the zero clearing, and the timing duration can be adaptively adjusted according to the switching frequency Freq of the current system. For example, when the system switching frequency signal Freq is set to F _SW The timing length can be set to Kx 1/F _SW And K is a pre-designed fixed proportionality coefficient.

Fig. 3 illustrates an exemplary circuit diagram of the adaptive turn-off time and phase delay control circuit 310 of fig. 1. The adaptive turn-off time and phase delay control circuit 310 includes a plurality of cascaded control sub-circuits 311-1 \8230 \ 8230; 311-i. The first-stage control sub-circuit 311-1 is used to generate the PWM signal PWM _1 of the main phase. The first-stage control sub-circuit 311-1 includes: a main phase inverter NG _1, a main phase AND gate AND _1, a main phase RS flip-flop 313, an adaptive off-time calculation circuit 311, AND a minimum off-time control circuit 312. The adaptive off-time calculation circuit 311 calculates an adaptive off-time from the system switching frequency signal Freq. The adaptive off-time calculation circuit 311 outputs a high level signal when the adaptive off-time is reached after the PWM signal PWM _1 of the main phase is inverted from the high level to the low level. After the PWM signal PWM _1 of the main phase is inverted from the high level to the low level, the minimum off-time control circuit 312 is inputted with the high level signal due to the inversion action of the main phase inverter NG _1, and when the minimum off-time is reached, the minimum off-time control circuit 312 outputs the high level signal. In the case where the high-level signal is input to both input terminals of the main-phase AND gate AND _1, the signal OFF output from the output terminal of the main-phase AND gate AND _1 is inverted to the high level, thereby setting the main-phase RS flip-flop 313. When the main phase inductor current peak signal IPEAK _1 flips to a high level, the main phase RS flip-flop 313 is reset.

The structures of the control sub-circuits other than the first-stage control sub-circuit 311-1 are the same. To avoid repetition, only the ith-stage control sub-circuit 311-i for generating the PWM signal PWM _ i of the ith phase (i.e., the (i-1) th sub-phase) is shown in fig. 3. The ith stage control sub-circuit 311-i includes: the circuit comprises an ith stage D trigger Di, an ith stage first delay circuit 314-i, an ith stage first AND gate AND1i, an ith stage RS trigger 315-i, a minimum turn-off time control circuit 316-i, an ith stage second AND gate AND2i, an ith stage first inverter NG1i AND an ith stage second inverter NG2i. Where i is an integer greater than 1. In some embodiments of the present disclosure, the principle of operation of the minimum off-time control circuit 316-i is the same as the principle of operation of the minimum off-time control circuit 312.

When the PWM signal PWM _ i-1 of the i-1 th phase is inverted from a low level to a high level, the i-th stage D flip-flop Di is triggered to output a high level signal. The ith-stage first delay circuit 314-i delays the first time and then outputs the high-level signal DLY _ OUT _ i. If the time that the ith phase PWM signal PWM _ i is at the low level at this time exceeds the minimum off time, the minimum off time control circuit 316-i also outputs a signal of the high level. The ith-stage first AND gate AND1i outputs a high level signal to trigger the ith-phase PWM signal PWM _ i output by the ith-stage RS flip-flop 315-i to be inverted to a high level. When the ith phase inductor current peak signal IPEAK _ i is inverted to a high level, the ith stage RS flip-flop 315-i is reset, and the ith phase PWM signal PWM _ i is inverted to a low level. In fig. 3, due to the setting of the minimum off-time control circuit, the low level durations of the PWM signals of all phases cannot be lower than the fixed delay (minimum off-time) set by the minimum off-time control circuit.

The delay selection of the ith stage first delay circuit 314-i is related to the switching frequency of the present multi-phase control system. The delay is designed to be shorter when the switching frequency is higher and longer when the switching frequency is lower. Taking a 6-phase control system with a switching frequency of 1MHz as an example, the single-phase switching period of the system is designed to be 1 mus. In order to maintain uniform energy distribution in steady state when the phase is turned on, the delay τ of the ith stage of the first delay circuit 314-i should satisfy:

fig. 5 illustrates a timing diagram of some signals for a multi-phase DC-DC converter including the adaptive turn-off time and phase delay control circuit shown in fig. 3. In the multiphase DC-DC converter with sequential phase delay, after a delay from an inductor current valley point of the ith phase (a rising edge of the PWM signal of the ith phase) for a certain period of time (the time point after the delay for the certain period of time may be referred to as an inductor current valley delay point in the context), the PWM signal of the (i + 1) th phase is inverted to a high level, thereby achieving sequential phase delay. In fig. 5, when the applied load ILOAD of the multiphase DC-DC converter is switched from a light load to a heavy load, the error amplification signal EAO may overshoot due to the drop of the output voltage VOUT. As described above, when the i-th phase superimposed signal VSUM _ i reaches the error amplification signal EAO, the PWM comparator COMP outputs a high level signal to control the i-th phase PWM signal to be inverted to a low level, thereby turning off the upper power transistor S1_ i. As the error amplified signal EAO increases, the superimposed signal takes longer to reach the error amplified signal EAO. Therefore, the phase loop in high duty cycle application may experience a long time on operation of the upper power transistor S1 — i.

In fig. 5, the inductor current valley delay time point of the (i + 1) th phase (the point marked as 1 in the figure is delayed by a certain time) makes the (i + 2) th phase enter the working state that the upper power tube is turned on for a long time. In the continuous process of the on state of the power tube of the i +1 th phase, due to the existence of the compensation voltage signal VRAMP _ i +1, the superposed signal VSUM _ i +1 quickly rises to reach the error amplification signal EAO, namely the inductive current of the i-th phase quickly reaches the peak value, and the working process of the on state of the upper power tube and the off state of the lower power tube is completed. Thereafter, the (i + 1) th phase enters the 2 nd switching period, and the (i + 2) th phase misses the 2 nd inductor current valley delay time point of the (i + 1) th phase (the point marked as 2 in the figure is delayed by a certain time) due to the working state of the power tube which is continuously turned on. In the duration that the inductive current of the (i + 2) th phase reaches the peak value and the delay time point of the inductive current valley value of the (i + 1) th phase (the point marked as 3 in the figure after delaying for a period of time) does not reach, the (i + 2) th phase enters the working state that the lower power tube is opened for a long time. Therefore, the inductor current dc of the (i + 2) th phase is lower than that of the (i + 1) th phase, and the dc difference is increased with the cycle-by-cycle adjustment of the system until the two-phase loop enters the respective "steady" state. In fig. 5, since the superimposed signal VSUM _ i +2 misses the inductor current valley delay time of the i +1 th phase once in the process of rising each switching period, the switching period of the i +2 th phase PWM _ i +2 is finally maintained twice as long as the switching period of the i +1 th phase PWM _ i + 1. More seriously, the multiple phase loops of the multiphase DC-DC converter can be operated in multiple different states by the phase-by-phase propagation of the above-mentioned problems, so that the overall stability of the multiphase DC-DC converter is impaired.

In order to maintain the overall stability of the multiphase DC-DC converter, embodiments of the present disclosure propose an adaptive turn-off time and phase delay control circuit for the multiphase DC-DC converter. Fig. 6 shows a schematic block diagram of an adaptive turn-off time and phase delay control circuit 610 for a multiphase DC-DC converter, according to an embodiment of the disclosure. The adaptive off-time and phase delay control circuit 610 includes: multiple cascaded control subcircuits 611-1, 611-2, 611-3 \8230, 8230and 611-i. The first-stage control sub-circuit 611-1 is used to generate a PWM signal PWM _1 of the main phase. The second-stage control sub-circuit 611-2 is configured to generate the first secondary-phase PWM signal PWM _2. The third-stage control sub-circuit 611-3 is configured to generate the PWM signal PWM _3 of the second secondary phase. And so on.

The first level control subcircuit 611-1 may be coupled to the second level control subcircuit 611-2. The first level control subcircuit 611-1 may be configured to: the PWM signal PWM _1 controlling the main phase is flipped from the first level to the second level when the main phase inductor current peak signal IPEAK _1 is flipped from the second level (e.g., low level) to the first level (e.g., high level), and from the second level to the first level after the longer time of the adaptive off-time and the minimum off-time elapses. Wherein the adaptive off-time is determined from the system switching frequency signal Freq.

The ith stage control sub-circuit 611-i may couple an (i-1) th stage control sub-circuit (not shown) and an (i + 1) th stage control sub-circuit (not shown). The ith stage control subcircuit 611-i may be configured to: and generating the PWM signal PWM _ i of the ith phase under the control of the PWM signal PWM _ i-1 of the ith-1 phase, the inductive current peak value signal IPEAK _ i of the ith phase and the system switching frequency signal Freq output by the control sub-circuit of the ith-1 stage. If the PWM signal PWM _ i of the ith phase is at the first level (the multiphase DC-DC converter is switched from the light load to the heavy load) when the first preset time is reached after the PWM signal PWM _ i-1 of the ith-1 phase is inverted from the second level to the first level, the time length of the next time the PWM signal of the ith phase is at the second level is controlled to be equal to the minimum turn-off time of the multiphase DC-DC converter. In this case, the first preset time is equal to the inter-phase delay time of the multiphase DC-DC converter.

In some embodiments of the present disclosure, if the PWM signal PWM _ i of the i-th phase is at the second level (the multiphase DC-DC converter operates in a steady state) when a first preset time is reached after the PWM signal of the i-1-th phase is inverted from the second level to the first level, the PWM signal of the i-th phase is controlled to be inverted from the second level to the first level. Thus, the phase delay of the i-th phase PWM signal with respect to the i-1 th phase PWM signal is equal to the first preset time.

In the example of fig. 6, i is an integer greater than 1.

For ease of understanding, control sub-circuits of i =2 and 3 are also shown in fig. 6. The second level control sub-circuit 611-2 is coupled to the first level control sub-circuit 611-1 and the third level control sub-circuit 611-3. The second level control subcircuit 611-2 may be configured to: the second phase PWM signal PWM _2 is generated under the control of the main phase PWM signal PWM _1 output from the first stage control sub-circuit, the second phase (i.e., the first secondary phase) peak inductor current signal IPEAK _2, and the system switching frequency signal Freq. And if the PWM signal PWM _2 of the second phase is at the first level when the first preset time is reached after the PWM signal PWM _1 of the main phase is reversed from the second level to the first level, controlling the time length of the next time that the PWM signal PWM _2 of the second phase is at the second level to be equal to the minimum turn-off time of the multi-phase DC-DC converter.

The third level control sub-circuit 611-3 couples the second level control sub-circuit 611-2 and a fourth level control sub-circuit (not shown). The third level control subcircuit 611-3 may be configured to: the PWM signal PWM _3 of the third phase (i.e., the second sub-phase) is generated under the control of the PWM signal PWM _2 of the second phase, the inductor current peak signal IPEAK _3 of the third phase, and the system switching frequency signal Freq output from the second-stage control sub-circuit. And if the PWM signal PWM _3 of the third phase is at the first level when the first preset time is reached after the PWM signal PWM _2 of the second phase is reversed from the second level to the first level, controlling the time length of the next time that the PWM signal PWM _3 of the third phase is at the second level to be equal to the minimum turn-off time of the multi-phase DC-DC converter.

According to the adaptive turn-off time and phase delay control circuit for the multiphase DC-DC converter, when the inductive current peak value sampling signal of the current phase misses the inductive current valley delay point of the current period in the continuous rising process, the PWM signal of the current phase is forced to automatically enter the next switching period after maintaining the duration of the minimum turn-off time, so that the difference between the inductive current direct current level of each phase and the previous phase can be converged cycle by cycle, and the overall stability of the multiphase DC-DC converter is further maintained.

Fig. 7 shows a schematic block diagram of the first stage control sub-circuit 711-1 in the adaptive off-time and phase-delay control circuit 610 shown in fig. 6. The first level control sub-circuit 711-1 may include: a main phase inverter NG _1, a main phase AND gate AND _1, a main phase RS flip-flop 7113, an adaptive off-time calculation circuit 7111, AND a main phase minimum off-time control circuit 7112. Wherein the adaptive off-time calculation circuit 7111 may be configured to: the adaptive off-time is calculated from the system switching frequency signal Freq and a signal at the first level is output when the adaptive off-time is reached after the PWM signal PWM _1 of the main phase is inverted from the first level to the second level. The main phase minimum off time control circuit 7112 may be configured to: the signal at the first level is output when a minimum off-time is reached after its input signal is inverted from the second level to the first level. An input terminal of the main phase inverter NG _1 is coupled to the non-inverting output terminal Q of the main phase RS flip-flop 7113. The output terminal of the master phase inverter NG _1 is coupled to the input terminal of the master phase minimum off-time control circuit 7112. A first input terminal of the main AND gate AND _1 is coupled to the output terminal of the adaptive off-time calculation circuit 7111. A first input terminal of the main phase AND gate AND _1 is coupled to the output terminal of the main phase minimum off-time control circuit 7112. The output terminal of the main phase AND gate AND _1 is coupled to the set terminal S of the main phase RS flip-flop 7113, so that the output signal OFF of the main phase AND gate AND _1 is provided to the set terminal S of the main phase RS flip-flop 7113. The reset terminal R of the main phase RS flip-flop 7113 is provided with a main phase inductor current peak signal IPEAK _1. The main-phase PWM signal PWM _1 is output from the non-inverting output Q of the main-phase RS flip-flop 7113.

Fig. 8 shows a schematic block diagram of the ith stage control sub-circuit 811-i in the adaptive off-time and phase delay control circuit 610 shown in fig. 6. The ith stage control sub-circuit 811-i may include: the circuit comprises an i-th stage trigger circuit 8114-i, an i-th stage first delay circuit 8115-i, an i-th stage setting control circuit 8116-i, an i-th stage first RS trigger RS1_ i, an i-th stage state recording circuit 8117-i and an i-th stage reset circuit 8118-i.

The ith stage trigger circuit 8114-i may be coupled to an output terminal of the previous stage control sub-circuit to receive the PWM signal PWM _ i-1 of the ith-1 phase. The ith stage trigger circuit 8114-i may be coupled to the ith stage reset circuit 8118-i to receive an ith reset signal RST _ i. An output of the ith stage trigger circuit 8114-i may be coupled to the ith stage first delay circuit 8115-i. The ith stage trigger circuit 8114-i may be configured to: an ith trigger signal TRG _ i is generated from the PWM signal PWM _ i-1 of the i-th phase and the ith reset signal RST _ i from the ith stage reset circuit 8118-i, and the ith trigger signal TRG _ i is supplied to the ith stage first delay circuit 8115-i. The ith trigger signal TRG _ i is inverted to the first level when the PWM signal PWM _ i-1 of the i-1 th phase is inverted from the second level to the first level, and is at the second level when the ith reset signal RST _ i is at the active level.

The ith stage first delay circuit 8115-i may be coupled to the ith stage trigger circuit 8114-i to receive the ith trigger signal TRG _ i. The output of the ith stage first delay circuit 8115-i may be coupled to the ith stage set control circuit 8116-i, the ith stage state recording circuit 8117-i, and the ith stage reset circuit 8118-i. The ith stage first delay circuit 8115-i may be provided with a system switching frequency signal Freq. The ith stage first delay circuit 8115-i may be configured to: and generating an ith phase delay indication signal DLY _ OUT _ i according to the ith trigger signal TRG _ i. The ith phase delay indicating signal DLY _ OUT _ i is inverted from the second level to the first level when a first preset time is reached after the ith trigger signal TRG _ i is inverted from the second level to the first level, and is inverted from the first level to the second level after the ith trigger signal TRG _ i is inverted from the first level to the second level. In some embodiments of the present disclosure, the first preset time is determined according to the system switching frequency signal Freq.

The ith stage set control circuit 8116-i may be coupled to an output terminal of the ith stage first delay circuit 8115-i to receive the ith phase delay indication signal DLY _ OUT _ i. The ith stage set control circuit 8116-i may be coupled to the non-inverted output terminal Q of the ith stage first RS flip-flop RS1_ i to receive the ith phase PWM signal PWM _ i. The ith stage set control circuit 8116-i may also be coupled to the set terminal S of the ith stage first RS flip-flop RS1_ i. The ith stage set control circuit 8116-i may be configured to: and generating an ith SET signal SET _ i according to the ith phase delay indication signal DLY _ OUT _ i and the ith phase PWM signal PWM _ i. Wherein the ith SET signal SET _ i is at an active level in a case where a time when the ith phase delay indication signal DLY _ OUT _ i is at a first level and the ith phase PWM signal PWM _ i is at a second level reaches a minimum off-time.

The SET terminal S of the ith stage first RS flip-flop RS1_ i may be supplied with an ith SET signal SET _ i. The reset terminal R of the ith stage first RS flip-flop RS1_ i may be provided with the i-th phase inductor current peak signal IPEAK _ i. And outputting the ith-phase PWM signal PWM _ i from the non-inverting output end Q of the ith-stage first RS trigger RS1_ i.

The ith stage status recording circuit 8117-i may be coupled to the non-inverted output terminal Q of the ith stage first RS flip-flop RS1_ i to receive the ith phase PWM signal PWM _ i. The ith stage state recording circuit 8117-i may be coupled to an output of the ith stage first delay circuit 8115-i to receive the ith phase delay indication signal DLY _ OUT _ i. The ith stage state recording circuit 8117-i may also be coupled to the ith stage reset circuit 8118-i. The i-th stage state recording circuitry 8117-i may be configured to: and generating an ith state indicating signal STA _ i according to the ith phase PWM signal PWM _ i and the ith phase delay indicating signal DLY _ OUT _ i. The ith state indicating signal STA _ i is at the first level when the ith phase delay indicating signal DLY _ OUT _ i is at the first level, and is inverted to the second level when a second preset time is reached after the ith phase PWM signal PWM _ i is inverted to the first level. In some embodiments of the present disclosure, the second preset time may be, for example, greater than or equal to 15ns.

The ith stage reset circuit 8118-i may be coupled to an output of the ith stage first delay circuit 8115-i to receive the ith phase delay indication signal DLY _ OUT _ i. The ith stage reset circuit 8118-i may be coupled to the non-inverted output terminal Q of the ith stage first RS flip-flop RS1_ i to receive the ith phase PWM signal PWM _ i. The ith stage reset circuit 8118-i may be coupled to an output of the ith stage state recording circuit 8117-i to receive the ith state indication signal STA _ i. The ith stage reset circuit 8118-i may also be coupled to the ith stage trigger circuit 8114-i. The i-th stage reset circuit 8118-i may be configured to: the ith reset signal RST _ i is generated according to the ith phase delay indication signal DLY _ OUT _ i, the ith phase PWM signal PWM _ i, and the ith status indication signal STA _ i. The ith reset signal RST _ i is inverted to an active level when a third preset time is reached after the ith phase delay indication signal DLY _ OUT _ i, the ith phase PWM signal PWM _ i and the ith state indication signal STA _ i are all at the first level, and is at an inactive level when any one of the ith phase delay indication signal DLY _ OUT _ i, the ith phase PWM signal PWM _ i and the ith state indication signal STA _ i is at the second level. In some embodiments of the present disclosure, the third preset time may be, for example, greater than or equal to 15ns.

Fig. 9 illustrates an exemplary circuit diagram of the ith stage control subcircuit 911-i shown in fig. 8. The ith stage flip-flop circuit 9114-i may include: the ith stage D flip-flop D _ i. Wherein, the data input end D of the ith stage D flip-flop D _ i is coupled with the inverted output end of the ith stage D flip-flop D _ i

The clock signal terminal Clk of the ith stage D flip-flop D _ i is supplied with the PWM signal PWM _ i-1 of the i-1 th phase. The Reset terminal Reset of the ith stage D flip-flop D _ i is coupled to the output terminal of the ith stage Reset circuit 9118-i. The non-inverting output terminal Q of the ith stage D flip-flop D _ i is coupled to the input terminal of the ith stage first delay circuit 8115-i.

The ith-stage set control circuit 9116-i may include: an ith stage first AND gate AND1_ i, an ith stage first inverter NG1_ i, AND an ith stage minimum off-time delay circuit 91161. The first input terminal of the ith stage first AND gate AND1_ i is coupled to the output terminal of the ith stage first delay circuit 8115-i. A second input terminal of the ith stage first AND gate AND1_ i is coupled to an output terminal of the ith stage minimum off-time delay circuit 91161/i. The output end of the ith stage first AND gate AND1_ i is coupled to the set end S of the ith stage first RS flip-flop RS1_ i. An input end of the ith stage first inverter NG1_ i is coupled to the non-inverting output end Q of the ith stage first RS flip-flop RS1_ i. An output terminal of the ith stage first inverter NG1_ i is coupled to an input terminal of the ith stage minimum off-time delay circuit 91161 \. The i-th stage minimum off-time delay circuit 91161 \ is configured to control its output signal to flip to the first level when the minimum off-time is reached after its input signal flips to the first level, and to control its output signal to be at the second level if its input signal is at the second level.

The ith stage status recording circuit 9117-i may comprise: an ith stage of the second delay circuit 91171\ u i, and an ith stage of the second RS flip-flop RS2_ i. Wherein the ith stage second delay circuit 91171\ u i may be configured to: and controlling the output signal of the ith phase to be inverted to the first level when a second preset time is reached after the PWM signal PWM _ i of the ith phase is inverted from the second level to the first level, and controlling the output signal of the ith phase to be at the second level when the PWM signal PWM _ i of the ith phase is at the second level. The set end S of the ith stage second RS flip-flop RS2_ i is coupled to the output end of the ith stage first delay circuit 8115-i. A reset terminal R of the ith-stage second RS flip-flop RS2_ i is coupled to an output terminal of the ith-stage second delay circuit 91171\\. And an ith state indication signal STA _ i is output from a non-inverting output end Q of the ith stage second RS flip-flop RS2_ i. In some embodiments of the present disclosure, the ith stage second delay circuit 91171\ is a rising edge delay circuit.

In some embodiments of the present disclosure, the ith stage second delay circuit 91171\ u i may include: an ith stage, a second inverter NG2_ i, an ith stage, a third inverter NG3_ i, and an ith stage capacitor C _ i. An input end of the ith stage second inverter NG2_ i is coupled to the non-inverting output end Q of the ith stage first RS flip-flop RS1_ i. An output terminal of the second inverter NG2_ i of the ith stage is coupled to an input terminal of the third inverter NG3_ i of the ith stage. An output terminal of the ith stage third inverter NG3_ i is coupled to the first terminal of the ith stage capacitor C _ i and the output terminal of the ith stage second delay circuit 91171\\. The second terminal of the ith stage capacitor C _ i is coupled to the second voltage terminal V2.

The ith stage reset circuit 9118-i may include: the second AND gate AND2_ i of the ith stage, the third delay circuit 91181-i of the ith stage, AND the fourth inverter NG4_ i of the ith stage. AND a first input end of the ith stage second AND gate AND2_ i is coupled to an output end of the ith stage first delay circuit 8115-i. A second input end of the ith stage second AND gate AND2_ i is coupled to the non-inverting output end Q of the ith stage first RS flip-flop RS1_ i. A third input terminal of the ith stage second AND gate AND2_ i is coupled to an output terminal of the ith stage state recording circuit 9117-i. The output terminal of the second AND-gate AND2_ i of the ith stage is coupled to the input terminal of the third delay circuit 91181-i of the ith stage. The ith stage third delay circuit 91181-i may be configured to: and delaying the input signal for a third preset time and then outputting the delayed input signal. An input terminal of the ith stage fourth inverter NG4_ i is coupled to an output terminal of the ith stage third delay circuit 91181-i. The ith reset signal RST _ i is output from an output terminal of the ith stage fourth inverter NG4_ i.

In the example of fig. 9, the second voltage terminal V2 is grounded. The first level is a high level. The second level is a low level. The active level of the ith reset signal RST _ i is a low level. The inactive level of the ith reset signal RST _ i is a high level. The active level of the ith SET signal SET _ i is a high level. The inactive level of the ith SET signal SET _ i is a low level. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 9 based on the inventive concepts described above are intended to fall within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different arrangements from the example shown in fig. 9.

Fig. 10 illustrates a timing diagram of some of the signals for a multiphase DC-DC converter including the adaptive turn-off time and phase delay control circuit 610 shown in fig. 6. The operation of the adaptive turn-off time and phase delay control circuit for a multiphase DC-DC converter according to an embodiment of the present disclosure is described below with reference to the examples of fig. 9 to 10.

When the PWM signal PWM _ i-1 of the i-1 th phase is inverted from the low level to the high level, the i-th trigger signal TRG _ i is inverted to the high level. The ith phase delay indication signal DLY _ OUT _ i is toggled from a low level to a high level when a first preset time is reached after the ith trigger signal TRG _ i is toggled from a low level to a high level. At this time, the inductive current valley time point of the i-1 phase is reached.

If the i-th phase PWM signal PWM _ i is at a high level at this time, the i-th stage minimum off-time delay circuit 91161 \ outputs a low level, so that the i-th SET signal SET _ i is at a low level. In this case, the reset terminal R of the ith stage second RS flip-flop RS2_ i is at a high level, and thus the state indicating signal STA _ i is at a low level. The third input terminal of the second AND gate AND2_ i of the ith stage is at a low level, AND thus the second AND gate AND2_ i of the ith stage outputs a low level signal. Therefore, the ith reset signal RST _ i is at a high level, and the ith stage D flip-flop D _ i is not reset. The ith phase delay indication signal DLY _ OUT _ i remains at a high level.

When the inductor current peak signal IPEAK _ i of the ith phase is inverted to a high level, the PWM signal PWM _ i of the ith phase is reset to a low level. The set terminal S of the ith stage second RS flip-flop RS2_ i is at a high level, and thus the status indication signal STA _ i is at a high level. Since the second input terminal of the ith stage second AND gate AND2_ i is at a low level, the ith stage second AND gate AND2_ i still outputs a low level signal. Therefore, the ith reset signal RST _ i is at a high level, and the ith stage D flip-flop D _ i is not reset. The ith phase delay indication signal DLY _ OUT _ i remains at a high level.

When the minimum off-time (MIN-offset in fig. 10) is reached when the PWM signal PWM _ i of the i-th phase is at the low level, the i-th stage minimum off-time delay circuit 91161 \ outputs the high level, so that the i-th SET signal SET _ i is at the high level. The ith phase PWM signal PWM _ i is set to high level. Since the ith-stage second delay circuit 91171\ i delays the rising edge of the ith-phase PWM signal PWM _ i, the ith status indication signal STA _ i is reset to the low level only when the second preset time is reached after the ith-phase PWM signal PWM _ i is inverted to the high level. Thus, before the second preset time is reached, the high-level signals are input to the three input ends of the ith-stage second AND gate AND2_ i, so that the ith reset signal RST _ i is at a low level, AND the ith-stage D flip-flop D _ i is reset. The ith phase delay indication signal DLY _ OUT _ i flips to a low level. By arranging the ith-stage second delay circuit 91171\ u i, the error state that the ith-stage second RS trigger RS2_ i is reset directly when the ith-stage PWM signal PWM _ i is turned from a low level to a high level after the minimum turn-off time, so that the ith-stage delay indication signal DLY _ OUT _ i cannot be cleared, can be avoided.

When the multiphase DC-DC converter is switched from light load to heavy load, the adaptive turn-off time and phase delay control circuit for the multiphase DC-DC converter according to the embodiment of the disclosure automatically enters the next switching period by forcing the PWM signal of the current phase to maintain the duration of a minimum turn-off time, so that the difference between the direct current level of the inductor current of each phase and the previous phase can be converged cycle by cycle, and the overall stability of the multiphase DC-DC converter is further maintained.

If the i-th phase PWM signal PWM _ i is at a low level (the multiphase DC-DC converter operates in a steady state) when reaching the i-1 th phase inductor current valley delay time point, the i-th stage minimum off-time delay circuit 91161 \ outputs a high level, so that the i-th SET signal SET _ i is at a high level. The ith phase PWM signal PWM _ i is set to high level. After the second preset time, the reset terminal R of the ith stage second RS flip-flop RS2_ i is at the high level. Therefore, before the second preset time is reached, the high level signals are input to the three input terminals of the ith stage second AND gate AND2_ i, so that the ith reset signal RST _ i is at a low level, AND the ith stage D flip-flop D _ i is reset. The ith phase delay indication signal DLY _ OUT _ i flips to a low level. When the inductor current peak signal IPEAK _ i of the ith phase is inverted to a high level, the PWM signal PWM _ i of the ith phase is reset to a low level. The ith phase enters the next switching cycle. It can be seen that the adaptive off-time and phase delay control circuit according to embodiments of the present disclosure can operate normally in a steady state.

In summary, the adaptive turn-off time and phase delay control circuit for a multiphase DC-DC converter according to the embodiments of the present disclosure, when the inductor current peak sampling signal of the current phase misses the inductor current valley delay point of the previous phase inductor current peak sampling signal in the current cycle during the process of continuously rising (when the multiphase DC-DC converter switches from light load to heavy load), by forcing the PWM signal of the current phase to maintain the duration of a minimum turn-off time, automatically enter the next switching cycle, so that the difference between the inductor current DC level of each phase and the previous phase converges cycle by cycle, thereby maintaining the overall stability of the multiphase DC-DC converter.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such an interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.

Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. An adaptive turn-off time and phase delay control circuit for a multiphase DC-DC converter, comprising: a plurality of cascaded control sub-circuits,

wherein the ith stage control sub-circuit is configured to: generating an i-phase PWM signal under the control of an i-1-phase PWM signal, an i-phase inductive current peak signal and a system switching frequency signal which are output by an i-1-level control sub-circuit, wherein if the i-phase PWM signal is at a first level when a first preset time is reached after the i-1-phase PWM signal is inverted from a second level to the first level, the time length of the i-phase PWM signal at the second level next time is controlled to be equal to the minimum turn-off time of the multiphase DC-DC converter;

wherein the first stage control sub-circuit is configured to: controlling a PWM signal of a main phase to flip from the first level to the second level when a main phase inductor current peak signal flips from the second level to the first level and from the second level to the first level after a longer time of an adaptive off-time and the minimum off-time elapses, wherein the adaptive off-time is determined according to the system switching frequency signal;

wherein i is an integer greater than 1.

2. The adaptive off-time and phase-delay control circuit of claim 1, wherein the i-th phase PWM signal is controlled to be flipped from the second level to the first level if the i-th phase PWM signal is at the second level when the first preset time is reached after the i-1-th phase PWM signal is flipped from the second level to the first level.

3. An adaptive off-time and phase-delay control circuit according to claim 1 or 2, wherein the i-th stage control sub-circuit comprises: an ith stage trigger circuit, an ith stage first delay circuit, an ith stage setting control circuit, an ith stage first RS trigger, an ith stage state recording circuit and an ith stage reset circuit,

wherein the i-th stage trigger circuit is configured to: generating an ith trigger signal according to the PWM signal of the i-1 th phase and an ith reset signal from the ith-stage reset circuit, wherein the ith trigger signal is inverted to the first level when the PWM signal of the i-1 th phase is inverted from the second level to the first level, and is at the second level when the ith reset signal is at an active level;

the ith stage first delay circuit is configured to: generating an ith phase delay indication signal according to the ith trigger signal, wherein the ith phase delay indication signal is inverted from the second level to the first level when the first preset time is reached after the ith trigger signal is inverted from the second level to the first level, and is inverted from the first level to the second level after the ith trigger signal is inverted from the first level to the second level;

the i-th stage set control circuit is configured to: generating an ith set signal according to the ith phase delay indication signal and the ith-phase PWM signal, wherein the ith set signal is at an effective level when the ith phase delay indication signal is at the first level and the ith-phase PWM signal is at the second level for the minimum turn-off time;

the setting end of the ith-stage first RS trigger is provided with the ith setting signal, the resetting end of the ith-stage first RS trigger is provided with the ith phase inductive current peak signal, and the ith phase PWM signal is output from the in-phase output end of the ith-stage first RS trigger;

the i-th stage state recording circuit is configured to: generating an ith status indication signal according to the ith phase PWM signal and the ith phase delay indication signal, wherein the ith status indication signal is at the first level when the ith phase delay indication signal is at the first level, and is inverted to the second level when a second preset time is reached after the ith phase PWM signal is inverted to the first level;

the i-th stage reset circuit is configured to: generating an ith reset signal according to the ith phase delay indication signal, the ith phase PWM signal and the ith state indication signal, wherein the ith reset signal is inverted to the active level when a third preset time is reached after the ith phase delay indication signal, the ith phase PWM signal and the ith state indication signal are all at the first level, and is at an inactive level when any one of the ith phase delay indication signal, the ith phase PWM signal and the ith state indication signal is at the second level.

4. The adaptive off-time and phase-delay control circuit of claim 3, wherein the i-th stage trigger circuit comprises: the D-type flip-flop of the i-th stage,

the data input end of the ith-stage D flip-flop is coupled to the inverted output end of the ith-stage D flip-flop, the clock signal end of the ith-stage D flip-flop is provided with the PWM signal of the (i-1) th phase, the reset end of the ith-stage D flip-flop is coupled to the output end of the ith-stage reset circuit, and the non-inverted output end of the ith-stage D flip-flop is coupled to the input end of the ith-stage first delay circuit.

5. The adaptive off-time and phase-delay control circuit of claim 3, wherein the ith stage set control circuit comprises: the ith stage comprises a first AND gate, an ith stage first inverter and an ith stage minimum turn-off time delay circuit,

a first input end of the ith-stage first and gate is coupled to an output end of the ith-stage first delay circuit, a second input end of the ith-stage first and gate is coupled to an output end of the ith-stage minimum turn-off time delay circuit, and an output end of the ith-stage first and gate is coupled to a set end of the ith-stage first RS flip-flop;

the input end of the ith-stage first inverter is coupled to the in-phase output end of the ith-stage first RS trigger, and the output end of the ith-stage first inverter is coupled to the input end of the ith-stage minimum turn-off time delay circuit;

the ith stage minimum off-time delay circuit is configured to: controlling its output signal to flip to the first level when the minimum off-time is reached after its input signal is flipped to the first level, and controlling its output signal to be at the second level if its input signal is at the second level.

6. The adaptive off-time and phase-delay control circuit of claim 3, wherein the i-th stage state recording circuit comprises: an ith stage of second delay circuit and an ith stage of second RS flip-flop,

wherein the ith stage second delay circuit is configured to: controlling the output signal of the ith phase to be inverted to the first level when the second preset time is reached after the PWM signal of the ith phase is inverted from the second level to the first level, and controlling the output signal of the ith phase to be at the second level when the PWM signal of the ith phase is at the second level;

the setting end of the ith-stage second RS trigger is coupled to the output end of the ith-stage first delay circuit, the resetting end of the ith-stage second RS trigger is coupled to the output end of the ith-stage second delay circuit, and the ith state indication signal is output from the in-phase output end of the ith-stage second RS trigger.

7. The adaptive off-time and phase-delay control circuit of claim 6, wherein the ith stage second delay circuit comprises: an ith stage second inverter, an ith stage third inverter, and an ith stage capacitor,

the input end of the ith-stage second inverter is coupled to the non-inverting output end of the ith-stage first RS trigger, and the output end of the ith-stage second inverter is coupled to the input end of the ith-stage third inverter;

an output end of the ith stage third inverter is coupled to a first end of the ith stage capacitor and the output end of the ith stage second delay circuit;

the second terminal of the ith stage capacitor is coupled to the second voltage terminal.

8. The adaptive off-time and phase-delay control circuit of claim 3, wherein the ith stage reset circuit comprises: an ith stage, a second AND gate, an ith stage, a third delay circuit, and an ith stage, a fourth inverter,

a first input end of the ith-stage second and gate is coupled to an output end of the ith-stage first delay circuit, a second input end of the ith-stage second and gate is coupled to a non-inverting output end of the ith-stage first RS flip-flop, a third input end of the ith-stage second and gate is coupled to an output end of the ith-stage state recording circuit, and an output end of the ith-stage second and gate is coupled to an input end of the ith-stage third delay circuit;

the ith stage third delay circuit is configured to: delaying the input signal thereof for the third preset time and then outputting the delayed input signal;

the input end of the ith-stage fourth inverter is coupled to the output end of the ith-stage third delay circuit, and the ith reset signal is output from the output end of the ith-stage fourth inverter.

9. The adaptive off-time and phase-delay control circuit of claim 1, wherein the first stage control sub-circuit comprises: a main phase inverter, a main phase AND gate, a main phase RS trigger, a self-adaptive turn-off time calculation circuit and a main phase minimum turn-off time control circuit,

wherein the adaptive off-time calculation circuit is configured to: calculating the adaptive turn-off time according to the system switching frequency signal, and outputting a signal at the first level when the adaptive turn-off time is reached after the PWM signal of the main phase is inverted from the first level to the second level;

the main phase minimum off-time control circuit is configured to: outputting a signal at the first level when the minimum off-time is reached after its input signal is flipped from the second level to the first level;

the input end of the main phase inverter is coupled with the in-phase output end of the main phase RS trigger, and the output end of the main phase inverter is coupled with the input end of the main phase minimum turn-off time control circuit;

the first input end of the main phase AND gate is coupled with the output end of the self-adaptive turn-off time calculation circuit, the first input end of the main phase AND gate is coupled with the output end of the main phase minimum turn-off time control circuit, and the output end of the main phase AND gate is coupled with the position end of the main phase RS trigger;

the reset end of the main phase RS trigger is provided with the main phase inductive current peak value signal, and the main phase PWM signal is output from the in-phase output end of the main phase RS trigger.

10. A multiphase DC-DC converter comprising an adaptive off-time and phase delay control circuit according to any of claims 1 to 9.

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