CN115939076A

CN115939076A - Semiconductor structure and forming method thereof

Info

Publication number: CN115939076A
Application number: CN202110897703.9A
Authority: CN
Inventors: 叶昶麟; 黄耀霆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-08-05
Filing date: 2021-08-05
Publication date: 2023-04-07

Abstract

The invention relates to a semiconductor structure and a forming method thereof. The semiconductor structure includes: a carrier plate; the substrate is positioned on the carrier plate and provided with an external connecting circuit, and the external connecting circuit is provided with an external terminal; and a protective material covering the external terminal, wherein the protective material is separable from the external terminal for temporarily protecting the external terminal. Above-mentioned technical scheme can avoid the easy oxidized problem of terminal of external connection in the semiconductor structure at least.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In current wearable (wearable) products, devices or sensors with different functions are arranged at different locations of the module (module). These devices and sensors may have different functions, for example, a speaker (speaker) may face the user's ear, an antenna designed to face away from the user, a detection direction of a gesture radar facing away from the user, an Electrocardiogram (ECG) sensor or ear temperature sensor proximate to and facing the user, etc. If these functional designs are wired from only a single direction in the module, the routing of the device/sensor originally connected by the flexible board in the wearable product will be more complicated, and the miniaturization difficulty of the wearable product will be increased.

Therefore, in the conventional design, a circuit having external terminals (terminals) in a plurality of directions is provided on a substrate. However, these extra external terminals are usually made of conductive metal material, and are easily oxidized if not properly protected when no external device is connected, thereby affecting external connection.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, aiming at the problem that the externally connected terminal is easy to be oxidized in the related art.

According to an aspect of an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes: a carrier plate; the substrate is positioned on the carrier plate and provided with an external connecting circuit, and the external connecting circuit is provided with an external terminal; and a protective material covering the external terminals. Wherein the protective material is separable from the external terminal for temporarily protecting the external terminal.

In some embodiments, the external terminal is recessed within the line of the external connection line and has a surface exposed by the line, and the protective material covers the surface of the external terminal.

In some embodiments, the lines have surfaces exposed by the substrate, and the protective material also covers the surfaces of the lines.

In some embodiments, the external-to-external connection line has a side surface perpendicular to the upper surface of the carrier board, and the external terminal is located at least on the side surface of the external-to-external connection line.

In some embodiments, the external terminals are through holes of the external connection lines exposed from a surface of the substrate, which is perpendicular to the upper surface of the carrier plate.

In some embodiments, the external terminal is formed by partially overlapping a plurality of through holes.

In some embodiments, the semiconductor structure further comprises a mold that encapsulates the substrate and exposes at least one side of the protective material.

In some embodiments, the side of the protective material is aligned with the side of the carrier plate.

According to another aspect of an embodiment of the present invention, a method of forming a semiconductor structure is provided. The method comprises the following steps: providing a carrier and a substrate attached to the carrier, wherein the substrate has an external connection line having an external terminal, and a protective material embedded in the substrate covers the external terminal; the substrate and the carrier are cut to remove a portion of the substrate to expose the protective material.

In some embodiments, forming the external terminal includes; in a direction along the surface of the substrate, a plurality of drilling processes are performed to form an external terminal formed by stacking a plurality of through holes.

In some embodiments, before performing the cutting process, the method further comprises: a mold is formed on the carrier plate around the substrate.

In some embodiments, before performing the dicing process, the method further comprises: removing a portion of the molding to expose a side of the molding flush with the exposed protective material.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a schematic diagram of a semiconductor structure, according to some embodiments.

Fig. 1B is a schematic top view of the semiconductor structure of fig. 1A.

Fig. 2A illustrates top and side views of an external terminal according to some embodiments.

Fig. 2B and 2C are schematic diagrams illustrating exposed external terminals, respectively, according to some embodiments.

Fig. 3A, 4A, 5A and 6A respectively show schematic diagrams of stages of a method of forming a semiconductor structure according to an embodiment of the invention.

Fig. 3B, 4B, 5B and 6B show top views in the cross-sections through the substrate of fig. 3A, 4A, 5A and 6A, respectively.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present invention provide a semiconductor structure. Fig. 1A is a schematic diagram of a semiconductor structure 100 according to some embodiments. Referring to fig. 1A, a semiconductor structure 100 of the present invention has a carrier substrate 110, and a substrate 120 for connecting external devices (not shown) is disposed on the carrier substrate 110. The substrate 120 has a wiring 130 therein. The line 130 may include an external connection line 131. It is to be understood that the lines in the substrate 120 may also include other lines 132, such as a redistribution line (RDL), in addition to the external connection line 131. The lines 130 in the substrate 120 may include traces and vias for interconnecting the traces.

Fig. 1B is a schematic top view of the semiconductor structure of fig. 1A. As shown in conjunction with fig. 1A and 1B, the external connection wire 131 in the substrate 120 has an external terminal 133. In one embodiment, the external connection line 131 includes a via hole, in which a seed layer 131 (seed layer) is disposed along a sidewall of the via hole, and an external terminal 133 surrounded by the seed layer. As shown in fig. 1A, the substrate 120 is attached on the upper surface of the carrier board 110, and the external terminal 133 is located on a side of the substrate 120, which may be substantially perpendicular to the upper surface of the carrier board 110. In other embodiments, the side of the substrate 120 where the external terminal 133 is located may form other angles with the upper surface of the carrier board 110. The substrate 120 may be connected to an external element through the external terminal 133. The external terminals 133 may be electrically connected to the I/O112 on the carrier board 110 through the wires 130 in the substrate 120, so that the I/O112 on the carrier board 110 may be rotated to the external terminals 133 (also referred to as I/O) disposed on the vertical side of the substrate 120. In one embodiment, the carrier 110 and the substrate 120 may be connected by solder. In one embodiment, the substrate 120 includes a dielectric material covering the upper surfaces of the

external connection lines

131, 133 and 132.

The external terminal 133 of the substrate 120 is covered with a protective material 140. Also, the protective material 140 is detachable from the external terminal 133 for temporarily protecting the external terminal 133. Then, when the external terminal 133 of the substrate 120 is to be connected with an external element, for example, the protective material 140 covering the external terminal 133 may be removed. In some embodiments, the material of the protective material 140 may include photoresist, water-washing glue, or ultraviolet dissociation glue. In other embodiments, other suitable protective materials 140 may be used.

In the semiconductor structure 100 of the present invention, an additional external connection circuit is mainly disposed in the substrate 120 and the external terminal 133 is formed for external connection, the external terminal 133 is pre-protected by the protection material 140 after the external terminal 133 is formed, and the protection material 140 can be used as an oxidation-preventing layer, so that the external terminal 133 of the external connection line 131 is not oxidized during the assembly (assembly). Subsequently, when the external terminals 133 are to be connected to the outside, the passivation layer is removed.

In some embodiments, the substrate 120 is a build-up (build up) substrate. The build-up substrate 120 may include a plurality of dielectric layers stacked in a vertical direction and lines positioned in the plurality of dielectric layers, and the lines in adjacent dielectric layers may be electrically connected to each other. In other embodiments, any other suitable type of substrate 120 may be used for the substrate 120. In some embodiments, the line width/line spacing L/S of the lines in the substrate 120 may be up to 15/15 μm or less. The thickness of the substrate 120 may be less than 100 μm. In addition to the substrate 120, other electronic components 150 may also be bonded on the upper surface of the carrier plate 110. The semiconductor structure 100 may further comprise a mold 182, wherein the mold 182 covers the substrate 120 and exposes at least one side of the protection material 140.

As shown in fig. 1B, the external terminal 133 may be recessed within the external connection line 131, and a surface of the external terminal 133 is exposed by the external connection line 131 in the substrate 120. The protective material 140 covers exposed surfaces of the external terminal 133 and the external connection wire 131. In some embodiments, a part of the surface of the external connection wire 131 is exposed by the substrate 120 and may be flush with the surface of the external terminal 133, and a part of the surface of the external connection wire 131 is also covered by the protective material 140. As shown in fig. 1A and 1B, the side of the substrate 120 may have a groove 144 exposing the external terminal 133 and the external connection line 131. Wherein corner portions of the groove 144 may have a circular arc shape. The protective material 140 may be filled in the trench 144 to cover the external terminal 133 and the external connection line 131. In one embodiment, the trench 144 is defined by the dielectric material of the substrate 120 and the external connection line 131 and the external terminal 133. In one embodiment, the external terminals 133 covered by the protection material 140 are arranged in an array, which may be an N × M array, where N and M may be the same or different.

In some embodiments, the side of the protective material 140 and the side of the carrier plate 110 may be aligned in a vertical direction. In other not shown embodiments, the sides of the protective material 140 and the sides of the carrier plate 110 may be vertically offset from each other, i.e., not aligned. In some embodiments, in the vertical direction, a portion of the protective material 140 may be embedded within the substrate 120. In some embodiments, a portion of the protection material 140 may be embedded in the external connection line 131 in the substrate 120.

The lines in the substrate 120 may include traces and vias extending in a vertical direction and serving to interconnect the traces. In some embodiments, the external terminal 133 is formed by a portion of a through-hole in the substrate 120. The external terminals 133 may also comprise a portion of traces in the substrate 120. In other embodiments, the external terminals 133 may be any other applicable structure.

In particular, fig. 2A and 2B show top and side views, respectively, of the external terminal 133 according to some embodiments. Referring to fig. 2A and 2B, a plurality of through holes may be formed stacked on each other in a direction perpendicular to the side surface of the substrate 120, and the external terminal 133 may be formed by stacking a plurality of through holes in a direction perpendicular to the side surface of the substrate 120. The external terminal 133 formed of a plurality of via stacks may be formed by performing a plurality of drilling processes. The external terminal 133 may be a part of a through-hole formed by stacking a plurality of through-holes in a direction perpendicular to the side surface (vertical direction in fig. 1A) of the substrate 120. The through-hole forming the external terminal 133 may have a length in a direction perpendicular to the side of the substrate 120 in a plan view. In this way, when the cutting process is performed along the line L1 in fig. 2A to form the external terminals 133, even when the cutting is actually performed along the line L2 while the cutting line is offset from the preset cutting line L1, since the length of the external terminals 133 is increased in the direction perpendicular to the side surface of the substrate 120, the shape and area of the exposed external terminals 133 can be secured as shown in fig. 2B. And if it is a circular through hole which is single to the outer terminal 133, the resulting exposed area becomes small when the cutting position is shifted, as shown in fig. 2C.

There is also provided, in accordance with an embodiment of the present invention, a method of forming a semiconductor structure. Fig. 3A, 4A, 5A and 6A respectively show schematic diagrams of stages of a method of forming a semiconductor structure according to an embodiment of the invention. Fig. 3B, 4B, 5B, and 6B show top views in the cross-sections through the substrate 120 of fig. 3A, 4A, 5A, and 6A, respectively. For ease of illustration, like elements in fig. 3A-6B to fig. 1A-1B are given the same reference numerals.

First, as shown in fig. 3A and 3B, a carrier board 110 is provided, and a plurality of substrates 120 are placed over an upper surface of the carrier board 110. In addition to the substrate 120, other electronic components 150 are bonded on the upper surface of the carrier 110. The substrate 120 may include a dielectric layer and a line in the dielectric layer. The lines in the substrate 120 may include traces and vias for interconnecting the traces. The wires within the substrate 120 include a predetermined pair of external connection wires 131 and external terminals 133 buried in the external connection wires 131.

A protective material 140 is also disposed in the substrate 120 (fig. 3B). The protective material 140 covers the external terminal 133 of the external connection line 131. Before the substrate 120 is bonded to the carrier 110, a trench 144 may be formed in the substrate 120, the trench 144 exposes the external terminal 133, and the trench 144 is filled with the protective material 140. At this stage, the sides of the protective material 140 may be surrounded by the dielectric layer of the substrate 120 and thus not visible in the illustration of fig. 3A.

As shown in fig. 4A and 4B, a substrate 120 is bonded to the I/O112 at the upper surface of the carrier board 110. In the illustrated embodiment, substrate 120 may be bonded to I/O112 on carrier board 110 by solder 180. I/O112 on carrier 110 is bonded to circuitry at the lower surface of substrate 120.

As shown in fig. 5A and 5B, a molding 182 is formed over the carrier plate 110. The mold 182 surrounds the substrate 120 and also fills the space between the substrate 120 and the carrier 110. The molding 182 also encapsulates other electronic components on the carrier board 110. In some embodiments, the molding 182 may be flush with the upper surface of the substrate 120. The mold 182 may protect the various elements on the carrier board 110 and the external connection lines 131 in the substrate 120. In one embodiment, the molding 182 may cover the upper surface of the substrate 120. In one embodiment, the molding 182 may be disposed in a space between the substrate 120 and the carrier 110.

As shown in fig. 6A and 6B, a dicing process is performed. As shown in fig. 6A, a cutting process is performed between the two substrates 120 at a position passing through the protective material 140, and the protective material 140 within the substrates 120 is exposed. The dicing process may remove a portion of the substrate 120 to expose the protective material 140, thereby facilitating removal of the protective material 140 and direct connection of the external terminal 133 after removal of the protective material 140. A portion of the molding 182 may be removed before or during the cutting process to expose a side of the molding 182 flush with the exposed protective material.

In addition, as shown in fig. 6B, a cutting process may be performed along the cutting line L3 to separate each substrate 120 from a corresponding portion of the carrier 110, so as to form a single semiconductor structure (e.g., the semiconductor structure 100 shown in fig. 1A). The resulting semiconductor structure has benefits as discussed above with reference to fig. 1A and 1B.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, comprising:

a carrier plate;

the substrate is positioned on the carrier plate and provided with an external connecting line, and the external connecting line is provided with an external terminal;

a protective material covering the external terminal, wherein the protective material is separable from the external terminal for temporarily protecting the external terminal.

2. The semiconductor structure of claim 1, wherein the external terminals are recessed within lines of the external connection lines and have surfaces exposed by the lines, the protective material covering the surfaces of the external terminals.

3. The semiconductor structure of claim 2, wherein the line has a surface exposed by the substrate, the protective material further covering the surface of the line.

4. The semiconductor structure of claim 1, wherein the external connection line has a side perpendicular to an upper surface of the carrier board, and the external terminals are located at least on the side of the external connection line.

5. The semiconductor structure of claim 1, wherein the external terminals are through holes of the external connection lines exposed from a surface of the substrate, the surface of the substrate being perpendicular to an upper surface of the carrier.

6. The semiconductor structure of claim 5, wherein the pair of external terminals are formed by partial overlapping of a plurality of vias.

7. The semiconductor structure of claim 1, further comprising a mold that encapsulates the substrate and exposes at least one side of the protective material.

8. The semiconductor structure of claim 1, wherein a side of the protective material is aligned with a side of the carrier plate.

9. A method of forming a semiconductor structure, comprising:

providing a carrier board and a substrate attached on the carrier board, wherein the substrate has an external connection line having an external terminal on which a protective material embedded in the substrate is covered;

performing a cutting process on the substrate and the carrier, the cutting process removing a portion of the substrate to expose the protective material.

10. The method of forming a semiconductor structure according to claim 9, wherein forming the pair of external terminals comprises; performing a plurality of drilling processes in a direction along the surface of the substrate to form the pair of outer terminals formed by a plurality of via stacks.

11. The method of claim 9, further comprising, prior to performing said dicing process:

a molding is formed on the carrier plate around the substrate.

12. The method of claim 11, further comprising, prior to performing said dicing process: a portion of the molding is removed to expose a side of the molding flush with the exposed protective material.