CN115938428A

CN115938428A - Controller for dynamic random access memory, control method and electronic equipment

Info

Publication number: CN115938428A
Application number: CN202211664386.7A
Authority: CN
Inventors: 陶昱良; 彭凌飞; 潘于
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2022-12-23
Filing date: 2022-12-23
Publication date: 2023-04-07

Abstract

A controller, a control method and an electronic device for a dynamic random access memory are provided. The controller for a dynamic random access memory includes: the command scheduler comprises a command queue, is configured to receive the read command from the bus, cache the read command in the command queue, perform out-of-order scheduling on the read command cached in the command queue and sequentially send the read command to the dynamic random access memory according to a scheduling sequence; and the rearrangement controller is configured to receive the read data corresponding to the out-of-order scheduled read commands returned from the dynamic random access memory according to the scheduling sequence, reorder the read data corresponding to the read commands with the same identifier according to the sequence of the read commands with the same identifier entering the command scheduler, and return the read data to the bus. The controller supports out-of-order scheduling for the read commands with the same identifier, and reorders the read data according to the sequence of sending the read commands to the controller, so that the reading performance of the dynamic random access memory is improved.

Description

Controller for dynamic random access memory, control method and electronic equipment

Technical Field

Embodiments of the present disclosure relate to a controller for a dynamic random access memory, a control method for a dynamic random access memory, an electronic device, and a non-transitory computer-readable storage medium.

Background

DRAM (dynamic random access Memory) is widely used in various chip systems, for example, a CPU (central processing Unit) chip largely uses DDR (double data rate) dynamic random access Memory, a GPU (graphics processing Unit) chip largely uses GDDR (graphics double data rate) dynamic random access Memory, a mobile device chip largely uses LPDDR (low power double data rate) dynamic random access Memory, and a high performance computing chip largely uses HBM (high bandwidth Memory). The performance of the dram mainly depends on two factors, namely, the maximum bandwidth of the dram and the efficiency of the controller scheduling commands of the dram. The former is determined by the specific dram specification and the dram manufacturer, while the latter can be determined by the user at the time of chip design. Therefore, designing a high performance dynamic random access memory controller (also called DRAM controller) is the key to SoC (System-on-a-Chip) System performance.

Disclosure of Invention

At least one embodiment of the present disclosure provides a controller for a dynamic random access memory, including: the command scheduler comprises a command queue, is configured to receive a read command from a bus, cache the read command in the command queue, perform out-of-order scheduling on the read command cached in the command queue and sequentially send the read command to the dynamic random access memory according to a scheduling order, wherein each item of the read command has an identifier, and the identifier is an identity of a corresponding transaction to which the read command belongs; and the rearrangement controller is configured to receive read data which is returned from the dynamic random access memory according to the scheduling sequence and corresponds to the read command out-of-order scheduling, reorder the read data which corresponds to the read command with the same identifier according to the sequence of the read command with the same identifier entering the command scheduler, and return the read data to the bus.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, the reordering controller includes a token management module, a reordering virtual channel module, a scheduling token queue, and a read data memory, and the token management module is configured to allocate a unique corresponding token to each received read command, where the token is used to allocate a reordering virtual channel and a storage address in the read data memory to the corresponding read command; the reordering virtual channel module comprises a plurality of reordering virtual channels and is configured to manage and store read information related to the received read commands, so as to reorder the read data corresponding to the read commands with the same identifier according to the order in which the read commands with the same identifier enter the command scheduler, wherein each reordering virtual channel has a unique corresponding channel identifier, the channel identifier has a dynamic mapping relation with the identifier of the read command, and the read information stored in one reordering virtual channel belongs to the read commands with the same identifier; the scheduling token queue is configured to store token information of tokens corresponding to read commands which are scheduled and do not return read data according to the scheduling sequence; the read data memory is configured to store read data from the dynamic random access memory.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, when the token management module performs assigning a unique corresponding token to each received read command, the following operations are performed: selecting an unused storage address from the read data memory as a storage address of the current read command in the read data memory aiming at the received current read command; and distributing a reordering virtual channel for the current read command according to the identifier of the current read command.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, when the token management module performs allocating a reordering virtual channel to the current read command according to the identifier of the current read command, the following operations are performed: in response to the identifier of the current read command not being assigned a reordering virtual channel, selecting an unoccupied reordering virtual channel as the reordering virtual channel corresponding to the current read command; in response to the identifier of the current read command having been assigned a re-ordering virtual channel, treating the assigned re-ordering virtual channel as a re-ordering virtual channel corresponding to the current read command.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, each reordering virtual channel includes a plurality of cache entries, one cache entry is used to store read information related to one read command, the token information of the token includes a storage address, an end flag, a channel identifier, and an entry identifier, the storage address is used to indicate an address where read data of a read command corresponding to the token is stored in the read data memory; the end mark is used for indicating whether the read command corresponding to the token is the read command sent last in the corresponding transaction to which the token belongs; the channel identifier is used for indicating a reordering virtual channel for storing read information related to a read command corresponding to the token; the entry identifier is used for indicating the position of a cache entry storing read information related to the read command corresponding to the token in a reordering virtual channel allocated for the read command corresponding to the token.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, each reordering virtual channel is a first-in first-out storage queue, and each cache entry is a queue unit in the first-in first-out storage queue.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, read information related to each read command includes a data ready bit, an end flag, and a storage address, where the data ready bit is used to indicate whether read data of the read command is ready in the read data memory and can be read, and the reordering virtual channel module performs the following operations when managing and storing the read information related to the received read command: receiving token information of a token distributed for the current read command by a token management module aiming at the received current read command; determining a reordering virtual channel allocated to the current read command according to the token information of the current read command; determining a cache entry in the allocated reordering virtual channel, which is used for storing read information related to the current read command, and sending an entry identifier of the cache entry to the token management module, so as to serve as an entry identifier in the token information of the current read command; taking the storage address and the end mark in the token information of the current read command as the storage address and the end mark in the reading information of the current read command, and storing the storage address and the end mark in the cache entry; and responding to the read data of the current read command, returning from the dynamic random access memory and storing the read data to the storage address in the read data memory, and setting a data ready bit in the read information of the current read command to be in a ready state.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, the reordering virtual channel module further includes an arbitration unit, the data ready bit being in a ready state and indicating that data of the read command is ready in the read data memory and can be read, the arbitration unit is configured to select a target valid data channel from all valid data channels in a round robin manner, where one reordering virtual channel includes at most one valid data channel, the one valid data channel includes an end cache entry in the one reordering virtual channel and all cache entries before the end cache entry, and the data ready bit of all cache entries included in the one valid data channel is in a ready state, and the end cache entry is a cache entry in the one reordering virtual channel whose first end flag is valid from a front end of the one reordering virtual channel; the rearrangement controller is further configured to, according to the storage addresses in the N cache entries included in the target valid data channel, sequentially read N read data from the read data memory in the order in which the N cache entries are stored in the target valid data channel, and sequentially return the read data to the bus, where N is a positive integer.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, the command scheduler is further configured to: receiving token information of a token corresponding to each read command from the token management module, and correspondingly storing the read command and the corresponding token information into the command queue; and sending token information of tokens corresponding to the scheduled read commands to the scheduling token queue.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, the reordering controller is further configured to, in response to receiving read data returned by the dynamic random access memory, extract token information located at a forefront of the scheduling token queue, and write the received read data into the read data memory according to a memory address in the read token information.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, the token management module is further configured to, in response to reading of read data from the read data memory, recycle a token of a read command corresponding to the read data.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, when the token management module executes a token for recycling a read command corresponding to the read data, the following operations are performed: receiving the storage address of the read data in the read data memory, matching the read data storage address with the distributed token, and recycling the token with the matched storage address; and determining a reordering virtual channel corresponding to the matched token according to the channel identifier of the matched token, and recovering the reordering virtual channel corresponding to the matched token in response to that cache entries in the reordering virtual channel corresponding to the matched token are all empty.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, the reordering controller is further configured to return read data corresponding to read commands with different identifiers to the bus according to the scheduling order.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, the reorder controller is further configured to wait for a token to be recycled in response to the number of tokens that have been allocated reaching a maximum threshold, and send a suspend instruction to the command scheduler; the command scheduler is further configured to, in response to receiving the pause instruction, pause entry of the received read command into the command queue.

For example, in a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, the reordering controller further includes a selection module configured to turn on or off a reordering function according to a control instruction, wherein, in response to the reordering function being turned on, all read commands buffered in the command queue are scheduled out of order, and read data corresponding to read commands with the same identifier are reordered according to an order in which the read commands with the same identifier enter the command scheduler and returned to the bus; and responding to the closing of the reordering function, performing out-of-order scheduling on the read commands with different identifiers cached in the command queue, and returning read data corresponding to the read commands with different identifiers to the bus according to the scheduling sequence.

For example, at least one embodiment of the present disclosure provides a controller for a dynamic random access memory, further including: a bus interface controller configured to: receiving a read transaction from the bus, converting the read transaction into at least one read command and sending the at least one read command to the command scheduler and the rearrangement controller, wherein the identifier of the at least one read command is the identifier of the read transaction.

At least one embodiment of the present disclosure provides a control method for a dynamic random access memory, including: receiving a read command from a bus and caching the read command in a command queue, wherein each item of the read command has an identifier which is the identity of a corresponding transaction to which the read command belongs; performing out-of-order scheduling on the read commands cached in the command queue and sequentially sending the read commands to the dynamic random access memory according to a scheduling order; and receiving read data corresponding to the read commands dispatched out of order and returned from the dynamic random access memory according to the dispatching sequence, reordering the read data corresponding to the read commands with the same identifier according to the sequence of the read commands with the same identifier entering the command dispatcher, and returning the read data to the bus.

For example, in a control method for a dynamic random access memory provided in at least one embodiment of the present disclosure, receiving a read command from a bus and buffering the read command in a command queue includes: aiming at a received current read command, allocating a unique corresponding token for the current read command, wherein the token is used for allocating a reordering virtual channel and a storage address in a read data memory for the current read command, the read data memory is used for storing read data from the dynamic random access memory, and the reordering virtual channel has a one-to-one mapping relation with an identifier of the current read command; according to the token information of the token, determining reading information related to the current reading command, and storing the reading information into the reordering virtual channel; and storing the token information and the current read command into the command queue.

For example, in a control method for a dynamic random access memory provided in at least one embodiment of the present disclosure, assigning a unique corresponding token to the current read command includes: selecting an unused storage address from the read data storage as the storage address of the current read command in the read data storage; and distributing a reordering virtual channel for the current read command according to the identifier of the current read command.

For example, in a control method for a dynamic random access memory provided in at least one embodiment of the present disclosure, the read information includes a data ready bit, an end flag, and a storage address, the data ready bit is used to indicate whether data of the current read command is ready in the read data memory and can be read, the end flag is used to indicate whether the current read command is a read command sent last in the corresponding transaction to which the current read command belongs, the storage address is used to indicate an address of the read data of the current read command stored in the read data memory, and according to token information of the token, read information related to the current read command is determined and stored in the reordering virtual channel, including: determining a reordering virtual channel according to the token information of the token; determining a cache entry in the reordering virtual channel for storing the read information; taking the storage address and the end mark in the token information as the storage address and the end mark in the reading information and storing the storage address and the end mark in the cache entry; and setting a data ready bit in the read information to be in a non-ready state.

For example, in a control method for a dynamic random access memory provided in at least one embodiment of the present disclosure, out-of-order scheduling is performed on read commands cached in a command queue, and the read commands are sequentially sent to the dynamic random access memory according to a scheduling order, where the method includes: according to the scheduling sequence, sequentially sending the scheduled read commands to the dynamic random access memory to read data; and according to the scheduling sequence, sending the token information of the token corresponding to the scheduled read command to a scheduling token queue, wherein the scheduling token queue is configured to store the token information of the token corresponding to the read command which is scheduled and does not return read data according to the scheduling sequence.

For example, in a control method for a dynamic random access memory provided in at least one embodiment of the present disclosure, receiving read data corresponding to the out-of-order scheduled read commands returned from the dynamic random access memory according to the scheduling order, reordering the read data corresponding to the read commands with the same identifier according to the order in which the read commands with the same identifier enter the command scheduler, and returning the read data to the bus includes: in response to receiving the read data returned according to the scheduling sequence, storing the current read data into the read data memory for the received current read data, and updating a data ready bit of read information related to the current read data in a reordering virtual channel corresponding to the current read data to be in a ready state; selecting a target effective data channel, wherein the target effective data channel comprises N cache entries, and starting from the foremost end of the target effective data channel, the ending mark of the last cache entry in the N cache entries is effective, the ending marks of the rest N-1 cache entries are all ineffective, the data ready bits in the N cache entries are ready states, and N is a positive integer; and sequentially reading N pieces of read data from the read data memory according to the storage addresses in the read information in the N cache entries included in the target effective data channel and the sequence of storing the read information of the N cache entries into the target effective data channel, and sequentially returning the N pieces of read data to the bus.

For example, in a control method for a dynamic random access memory provided in at least one embodiment of the present disclosure, in response to receiving read data returned according to the scheduling order, for the received current read data, storing the current read data into the read data memory, and updating a data ready bit of read information related to the current read data in a reordering virtual channel corresponding to the current read data to a ready state, the method includes: reading token information positioned at the forefront end of the scheduling token queue, and writing the current read data into the read data memory according to a memory address in the token information; determining a cache entry for storing read information related to a read command corresponding to the current read data according to a channel identifier and an entry identifier in the token information; and updating a data ready bit of the read information in the cache entry to be in a ready state.

For example, in a control method for a dynamic random access memory provided in at least one embodiment of the present disclosure, selecting a target valid data channel includes: selecting the target effective data channel from all effective data channels in a round-robin manner, wherein one reordered virtual channel at most comprises one effective data channel, the one effective data channel comprises an ending cache entry in the one reordered virtual channel and all cache entries positioned before the ending cache entry, data ready bits of all cache entries included in the one effective data channel are in a ready state, and the ending cache entry is a cache entry in which a first ending mark from the foremost end of the one reordered virtual channel in the one reordered virtual channel is effective.

For example, at least one embodiment of the present disclosure provides a control method for a dynamic random access memory, further including: and returning the read data corresponding to the read commands with different identifiers to the bus according to the scheduling sequence.

For example, at least one embodiment of the present disclosure provides a control method for a dynamic random access memory, further including: and in response to the read data being read from the read data memory, recovering the token of the read command corresponding to the read data.

At least one embodiment of the present disclosure provides an electronic device including a controller for a dynamic random access memory according to any one of the embodiments of the present disclosure.

At least one embodiment of the present disclosure provides an electronic device, including: a memory non-transiently storing computer executable instructions; a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the control method for the dynamic random access memory according to any embodiment of the present disclosure.

At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, which when executed by a processor, implement a control method for a dynamic random access memory according to any one of embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 shows a schematic diagram of an SoC architecture including a dynamic random access memory;

fig. 2 is a schematic block diagram of a controller for a dynamic random access memory according to at least one embodiment of the present disclosure;

fig. 3 is a schematic structural block diagram of a reordering controller and a command scheduler according to at least one embodiment of the present disclosure;

fig. 4 is a schematic data format diagram of token information provided by at least one embodiment of the present disclosure;

fig. 5 is a schematic diagram of a reordering virtual channel according to at least one embodiment of the present disclosure;

fig. 6 is a schematic flow chart of a control method for a dynamic random access memory according to at least one embodiment of the present disclosure;

fig. 7 is a schematic control flow diagram for a dynamic random access memory according to at least one embodiment of the present disclosure;

8A-8B are schematic diagrams illustrating the operation of a controller for a dynamic random access memory according to an embodiment of the present disclosure;

9A-9B are schematic diagrams illustrating a working flow of a controller for a dynamic random access memory according to another embodiment of the present disclosure;

fig. 10 is a schematic diagram of an electronic device according to at least one embodiment of the present disclosure;

fig. 11 is a schematic view of another electronic device provided in at least one embodiment of the present disclosure;

fig. 12 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs 5. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and the equivalent thereof, but does not exclude the presence of other elements or items

An element or an article. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical 0 connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly. To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure.

Fig. 1 shows a typical application of the dram in an SoC, all CPUs, GPUs 5 or other devices need to store and exchange data through the dram, and the performance of the dram is a key to the performance of the whole SoC system.

As shown in FIG. 1, in a typical SoC system, one or more CPUs and GPUs (e.g., CPU0, GPU0, CPU1, GPU1, etc. of FIG. 1) are connected to the system via a system bus interface

And accessing the off-chip dynamic random access memory through the DRAM controller on the interconnection bus. All data storage and communication of 0 data depend on the dynamic random access memory, so that the bandwidth of the dynamic random access memory is SoC

Plays a very central role in the energy.

The dynamic random access memory pair is connected to a system interconnection bus through a system bus interface, such as an AXI (advanced extensible interface) bus, an ACE (advanced coherence extension protocol of AXI bus protocol) or a CHI (Coherent 5 HubInterface) bus; the DRAM is externally connected to the off-chip DRAM through a DRAM interface, the DRAM interface is determined by the type of the off-chip DRAM, for example, the off-chip DRAM uses GDDR6, the standard GDDR6DRAM interface is used, for example, the off-chip DRAM uses LPDDR4, and the standard LPDDR4DRAM interface is used.

0 access to the dynamic random access memory is divided into three steps: the first step opens a certain Row (Row) in a certain block (Bank), the second step is to read or write data, and the third step is to close the opened Row in the block. The minimum time interval requirement exists between every two of the three steps, the requirements bring limitations to the access of the dynamic random access memory, and the design of the controller of the dynamic random access memory minimizes the influence of the time sequence limitations to the greatest extent so as to achieve the maximum access efficiency of the dynamic random access memory. The method for optimizing the access efficiency of the dynamic random access memory by using the controller of the dynamic random access memory mainly comprises two methods:

(a) The proportion of continuous access to the same block and the same line (line hit) is improved, and the access efficiency is improved. This is because, in case of a row hit, the first and third steps of the three steps of dynamic random access need not be repeated, i.e. for an already open row, consecutive accesses are possible.

(b) And the access parallelism among different blocks is utilized to improve the access efficiency. The dynamic random access memory supports simultaneous opening of multiple blocks and simultaneous access to rows in the multiple blocks, which increases the parallelism of access. For example, the dynamic random access memory supports simultaneous opening of two blocks, and different blocks are accessed alternately, so that data reading of a first block can be performed during opening of a second block, and the time for opening the second block is hidden in the data reading of the first block, thereby improving the access efficiency.

At present, almost all DRAM controller designs consider the two methods for optimizing the access efficiency of the dynamic random access memory, and the core of the two optimization methods is that the DRAM controller can carry out-of-order scheduling on commands, so that the access efficiency is maximized according to the performance requirement. However, due to some system limitations, not all read and write transactions can be scheduled out of order.

As shown in FIG. 1, the access to the DRAM comes from various masters in the system, such as a CPU, GPU or other master. The read transaction or write transaction (transaction) from the master device enters the DRAM controller after passing through the system bus, and the command scheduling is carried out by the DRAM controller. Read or write transactions from the system bus are packed in accordance with the system bus protocols, such as the AXI, ACE, and CHI protocols, among others, which are common.

In order to distinguish between read transactions and write transactions and control the sequence of read transactions and write transactions, each transaction is typically accompanied by an Identifier (ID), such as AxID in AXI protocol/ACE protocol, txnID in CHI protocol, etc. For example, in the out-of-order scheduling, when a plurality of transactions are in transit, some transactions may be ready first, and therefore may be sent on the bus first, and some transactions may be sent on the bus later, and therefore, which transaction's data is returned may be determined by the identifier of the transaction.

For transactions with the same identifier, the bus protocol dictates that the responses must be returned in the order in which the transactions were issued. Such as two read transactions having the same identifier, the order in which the read data is returned must be consistent with the order in which the read transactions were issued. This specification places limitations on the design of DRAM controllers: for simple design, the DRAM controller will schedule the read commands with the same identifier in the order of the received read commands, and therefore must prohibit the use of the above-mentioned two methods for optimizing the access efficiency of the DRAM, which affects the read data efficiency of the DRAM, and thus the read data performance of the whole system.

In general, the identifiers in read transactions from different masters are not the same, and therefore these read transactions may be scheduled out of order in the DRAM controller. However, the identifiers may be the same for read transactions from the same master, which limits the out-of-order scheduling of these read transactions in the DRAM controller.

The reason that the identifiers of the read transactions from the same master device are the same is two, namely, the number of the identifiers supported by the master device is limited, for example, the master device supports 16 identifiers at most, and if more than 16 transactions are continuously sent out, the identifiers must be multiplexed, so that the transactions with the same identifier occur; secondly, the host device reads data in a large scale, the same read transaction must be split into a plurality of DRAM read commands, and the identifiers of the read commands are the same, so that the read commands can only be scheduled in sequence. For example, a DRAM read command can read 64 bytes of data, if the master initiates a transaction to read 512 bytes of data, the read transaction must be split into 8 DRAM read commands, and the identifiers of the 8 DRAM read commands are the same.

At present, the DRAM controller can realize out-of-order scheduling for read commands with different identifiers, and the maximum performance of the DRAM is exerted. However, for different read commands with the same identifier, as the read data returned to the system bus needs to be returned in sequence according to the sending sequence of the read commands, the read data needs to be scheduled in sequence according to the sequence of the read data entering the command queue, and the returned read data sequence meets the requirement of the system bus, so that out-of-order scheduling cannot be performed, DRAM access optimization cannot be performed, and the performance of the whole system is affected.

At least one embodiment of the present disclosure provides a controller for a dynamic random access memory, a control method for a dynamic random access memory, an electronic device, and a non-transitory computer-readable storage medium.

For example, the controller for a dynamic random access memory includes: the command scheduler comprises a command queue, a dynamic random access memory and a bus, wherein the command queue is configured to receive a read command from the bus and cache the read command in the command queue, perform out-of-order scheduling on the read command cached in the command queue and sequentially send the read command to the dynamic random access memory according to a scheduling sequence, each item of the read command has an identifier, and the identifier is an identity of a corresponding transaction to which the read command belongs; and the rearrangement controller is configured to receive read data corresponding to the read commands out of order and scheduled from the dynamic random access memory according to the scheduling sequence, reorder the read data corresponding to the read commands with the same identifier according to the sequence of the read commands with the same identifier entering the command scheduler, and return the read data to the bus.

In the controller for the dynamic random access memory provided in at least one embodiment of the present disclosure, for the read commands with the same identifier, any out-of-order scheduling method may still be used to optimize the access efficiency of the dynamic random access memory, and reorder the read data returned from the dynamic random access memory according to the order in which the read commands are sent to the controller, support the controller to perform out-of-order scheduling on the read commands with the same identifier, improve the read performance of the dynamic random access memory, so that the controller for the dynamic random access memory maximizes the access efficiency of the dynamic random access memory, thereby improving the performance of a system (for example, an SOC system).

The present disclosure also provides a control method for a dynamic random access memory, corresponding to a controller for a dynamic random access memory provided in at least one embodiment of the present disclosure. The control method for the dynamic random access memory comprises the following steps: receiving a read command from a bus and caching the read command in a command queue, wherein each item of the read command has an identifier which is the identity of a corresponding transaction to which the read command belongs; the read commands cached in the command queue are dispatched out of order and are sequentially sent to the dynamic random access memory according to the dispatching order; and receiving read data of the read commands which are correspondingly dispatched out of order and returned from the dynamic random access memory according to the dispatching sequence, reordering the read data corresponding to the read commands with the same identifier according to the sequence of the read commands with the same identifier entering the command scheduler, and returning the read data to the bus.

In the control method for the dynamic random access memory, all read commands (whether the identifiers are the same or different) can be dispatched out of order and sent to the dynamic random access memory for data reading; after the read data are obtained, the read data are returned to the system bus according to the sequence of sending the read commands to the controller (namely, the sequence of receiving the read commands from the bus) for the read commands with the same identifier, so that the bandwidth of the dynamic random access memory is utilized to the maximum extent, the access efficiency of the dynamic random access memory is fully exerted, the returned read data sequence is ensured to meet the requirement of the system bus, and the performance of a system (such as an SOC system) is improved.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

Fig. 2 is a schematic block diagram of a controller for a dynamic random access memory according to at least one embodiment of the present disclosure.

As shown in fig. 2, the controller 100 for a dynamic random access memory includes a command scheduler 101 and a reorder controller 102.

In addition, as shown in fig. 2, the controller 100 further includes a system bus interface controller, a write data buffer, a read data buffer, a dynamic random access memory interface controller, a configuration register, and the like.

It should be noted that, of course, the controller 100 shown in fig. 2 is a schematic block diagram, and does not set any particular limitation to the controller structure of the present invention. According to actual needs, other components besides the command scheduler 101 and the rearrangement controller 102 may be combined, adjusted, added and deleted according to needs, and the connection relationship between them may also be adjusted accordingly, which is not specifically limited by the present disclosure.

For the system bus interface controller shown in fig. 2, it is configured to receive a read transaction from the bus, convert the read transaction into at least one read command, and send the read command to the command scheduler 101 and the reordering controller 102, where the identifier of the converted at least one read command is the identifier of the read transaction, that is, the read commands belong to the same read transaction. For example, as previously described, in some examples, if the master device reads data in large scale, the same read transaction must be split into multiple read commands whose identifiers are identifiers of the read transactions; in other examples, the read transactions do not need to be further split, i.e., one read transaction may be sent as one read command to the command scheduler 101 and reorder controller 102.

In the present disclosure, if the read transaction can be further split, the split commands are referred to as read commands, and if the read transaction does not need to be further split, the read transaction itself can be used as a read command.

The system bus interface controller is also configured to pack and send the read data (from the read data cache) returned by the dynamic random access memory to the system bus; and receiving a register configuration command from the system bus to complete the register configuration.

The command scheduler 101 includes a command queue 1011, the command queue 1011 being configured to buffer bus commands from a system bus interface controller.

For example, the command scheduler 101 is configured to receive a read command from the bus and buffer the read command in a command queue, and perform out-of-order scheduling on the read command buffered in the command queue and sequentially send the read command to the dynamic random access memory according to a scheduling order.

For example, the command scheduler 101 is configured to perform out-of-order scheduling on the read command/write command in the command queue 1011 according to a certain rule and send the out-of-order scheduling to the dynamic random access memory interface controller, so as to ensure that the access efficiency of the dynamic random access memory is fully exerted. The certain rule may include the aforementioned manner of increasing the ratio of continuously accessing the same row of the same block, or the manner of opening multiple blocks in parallel, and may also include other rules/manners of optimizing the access efficiency of the dynamic random access memory.

For the dynamic random access memory interface controller shown in fig. 2, it is configured to receive the read command from the command scheduler 101 and convert it into a command conforming to the DRAM interface, meeting the timing requirements of the DRAM interface. The DRAM interface controller is further configured to receive read data from the DRAM according to DRAM timing requirements and feed it into the reorder controller 102.

The reordering controller 102 is configured to receive read data corresponding to the out-of-order scheduled read commands returned from the dram according to the scheduling order, reorder the read data corresponding to the read commands having the same identifier according to the order in which the read commands having the same identifier enter the command scheduler, and return the read data to the bus. For example, each read command has an identifier, which is the identity of the corresponding transaction to which the read command belongs. For the meaning of the identifier, reference is made to the above description, which is not repeated here.

Therefore, in the controller provided in at least one embodiment of the present disclosure, the command scheduler schedules all commands in the command queue out of order without distinguishing whether the identifiers are the same; the reordering controller 102 reorders the read data returned according to the out-of-order scheduling order, and for the read commands with the same identifier, returns the read data to the system bus according to the order in which the read commands are sent to the controller (i.e., the order in which the read commands are received from the bus), thereby maximizing the utilization of the bandwidth of the dynamic random access memory, fully utilizing the access efficiency of the dynamic random access memory, ensuring that the returned read data order meets the requirements of the system bus, and improving the performance of the system (e.g., an SOC system).

For example, in the present disclosure, for read commands with different identifiers, read data corresponding to the read commands may be returned to the bus according to a scheduling order, and of course, the read data may also be returned to the system bus according to an order in which the read commands are sent to the controller (i.e., an order in which the read commands are received from the bus), which is not particularly limited by the present disclosure.

Reference is made to the detailed description below regarding the specific structure and function of the rearrangement controller 102.

For the read data buffer shown in fig. 2, the read data buffer is configured to buffer the reordered read data from the reordering controller 102, and send the reordered read data to the system bus interface controller, and the reordered read data is forwarded to the bus by the system bus interface controller. Since the sequence of the reordered read data returned by the reorder controller 102 meets the system bus sequence design requirement (for read commands with the same identifier, the bus protocol dictates that the read data must be returned according to the sending sequence of the read commands), the read data buffer module is generally a simple FIFO (first in first out) queue design.

For the configuration register shown in fig. 2, it is configured to receive a register configuration command from the system bus, and to save the user configuration of the controller 100, such as the timing parameters of the dynamic random access memory.

Of course, the controller 100 for the dynamic random access memory provided in at least one embodiment of the present disclosure may also process the write command.

For example, the system bus interface controller may be further configured to parse write transactions in the system data, convert them into write commands corresponding to the dram, and send them to the command scheduler 101 (not shown in fig. 2).

And the dynamic random access memory interface controller sends write data to the dynamic random access memory according to the DRAM timing requirement after the write command is sent out so as to write the write data into the dynamic random access memory.

As shown in fig. 2, the controller may further include a write data buffer configured to buffer write data from the system bus, and when a write command corresponding to the write data is scheduled in the command scheduler, corresponding write and read data is read and sent to the dynamic random access memory interface controller.

In general, read commands occupy most of the operations in SoC systems to access DRAM, because write commands are typically generated only when a cache block is written back in the L2/L3 cache, with the probability of the cache block being written back being much less than the probability of reading data. Therefore, the disclosure focuses on the description of the read process of the controller, and details about the write operation process of the DRAM are not described, and reference may be made to the general DRAM write operation process.

Fig. 3 is a schematic structural block diagram of a reordering controller and a command scheduler according to at least one embodiment of the present disclosure.

For example, the command scheduler 101 may no longer consider whether the identifiers of the read commands are the same, and may schedule all read commands into the command queue out of order based solely on the demand for maximized DRAM bandwidth.

For example, the command scheduler 101 is further configured to: receiving token information of a token corresponding to each read command from a token management module, and correspondingly storing the read command and the corresponding token information into a command queue; and sending token information of the token corresponding to the scheduled read command to a scheduling token queue.

As shown in fig. 3, the reordering controller 102 includes a token management module 1021, a reordering virtual channel module 1022, a scheduling token queue 1023, and a read data memory 1024.

For example, token management module 1021 is configured to assign a unique token to each received read command. Here, the tokens are used to assign reordering virtual channels and memory addresses in read data memory 1024 for corresponding read commands.

For example, the reordering virtual channel module 1022 includes a plurality of reordering virtual channels, such as M reordering virtual channels shown in fig. 3, which are reordering virtual channel 1, reordering virtual channel 2, \8230, and reordering virtual channel M, where M is a positive integer.

For example, each reordering virtual channel has a unique corresponding channel identifier, the channel identifier has a dynamic mapping relation with the identifier of the read command, and the read information stored in one reordering virtual channel belongs to the read command with the same identifier. For example, M channel identifiers are allocated to M reordering virtual channels in advance, a dynamic mapping relationship is established between the M channel identifiers and identifiers of read commands, and read information related to the read commands with the same identifiers is stored in the same reordering virtual channel for storage and management.

For example, the reorder virtual channel module 1022 is configured to manage and store read information associated with received read commands such that read data corresponding to read commands having the same identifier is reordered in the order in which read commands having the same identifier enter the command scheduler.

For example, the scheduling token queue 1023 is configured to store token information for tokens corresponding to read commands that have been scheduled and have not returned read data in the scheduled order. For example, whenever a read command is scheduled from the command scheduler 101 and sent to the DRAM interface controller, its token information is stored in the scheduling token queue. For example, when read data is returned, the entry at the front end of the scheduling token queue is extracted to execute corresponding processing, and then the entry at the front end of the scheduling token queue is still the read command which is not returned in the read data and is scheduled earliest according to the scheduling sequence.

Read data memory 1024 is configured to store read data from the dynamic random access memory. For example, read data memory 1024 may be a static random access memory, e.g., the write address of the read data memory is from the scheduling token queue and the read address is from the arbitration unit.

The specific functions and interaction of the modules are described in detail below with reference to fig. 3.

For example, token management module 1021 is further configured to store token information for the assigned token into command queue 1011 in the corresponding re-ordering virtual channel and command scheduler 101.

Fig. 4 is a schematic data format diagram of token information provided in at least one embodiment of the present disclosure.

As shown in fig. 4, the token information of the token includes a storage address, an end flag, a channel identifier, and an entry identifier.

The storage address is used for indicating the address of the read data of the read command corresponding to the token stored in the read data memory.

The end flag is used to indicate whether the read command corresponding to the token is the last read command sent in the corresponding transaction to which the token belongs. Generally, a bus read transaction corresponds to a read command, and therefore the end flag in the token assigned to the bus read transaction is valid (e.g., 1), which indicates that the read command is the last read command sent in the corresponding transaction; in the case of a massively transmitted bus read transaction, the bus read transaction may be split into multiple read commands, the identifiers of the multiple read commands are the same, only the end flag of the last sent read command is valid, and the rest of the read commands are invalid (e.g., 0).

The channel identifier is used for indicating a reordering virtual channel of the read information related to the read command corresponding to the storage token. Each channel identifier corresponds to a reorder virtual channel and is dynamically bound to an identifier of a read command.

The entry identifier is used for indicating the position of a cache entry storing read information related to the read command corresponding to the token in a reordering virtual channel allocated for the read command corresponding to the token. Each reordering virtual channel comprises a plurality of cache entries, one cache entry is used for storing read information related to one read command, and each entry identifier corresponds to one cache entry.

For example, referring to fig. 3, it can be understood that a plurality of reordered virtual channels form a memory matrix, each memory cell is a cache entry, the row coordinate of the cache entry is a channel identifier, the column coordinate is an entry identifier, and a cache entry can be uniquely determined by the channel identifier and the entry identifier.

For example, when the token management module executes to assign a unique corresponding token to each received read command, the following operations are executed: selecting an unused storage address from the read data memory as the storage address of the current read command in the read data memory aiming at the received current read command; and distributing a reordering virtual channel for the current read command according to the identifier of the current read command.

For example, when the token management module executes the allocation of the reordering virtual channel to the current read command according to the identifier of the current read command, the following operations are executed: in response to the identifier of the current read command not being assigned a reordering virtual channel, selecting an unoccupied reordering virtual channel as the reordering virtual channel corresponding to the current read command; in response to the identifier of the current read command having been assigned the re-ordering virtual channel, the assigned re-ordering virtual channel is treated as the re-ordering virtual channel corresponding to the current read command.

For example, when a token is allocated each time, whether an already allocated reordering virtual channel exists or not is searched for according to an identifier of a read command, and if so, a channel identifier of the already allocated reordering virtual channel is directly used as a channel identifier in token information of the token; otherwise, an unoccupied reordering virtual channel is selected for allocation to the current read command.

For example, the reordering virtual lanes are first-in-first-out memory queues (FIFOs), and each cache entry is a queue element (entry) in the first-in-first-out memory queue.

Fig. 5 is a schematic diagram of a reordering virtual channel according to at least one embodiment of the present disclosure.

As shown in fig. 5, the reordering virtual channel may be in the form of a FIFO queue, and includes a plurality of cache entries (e.g., L cache entries in fig. 5, respectively, cache entry 1, cache entry 2, \ 8230;, cache entry L, L being a positive integer), each of which is a queue element in the FIFO.

For example, unlike a conventional FIFO queue, the queue elements written in the FIFO queue for acting as a reordering virtual channel in at least one embodiment of the present disclosure may be modified, rather than read-only.

For example, the entry identifier has a one-to-one correspondence with the cache entry to indicate the location of the cache entry storing the read information in the reorder virtual channel.

The cache entry 1 at the head of the reordering virtual channel is used to store the first read information stored in the reordering virtual channel. The following cache entries are analogized.

As shown in fig. 5, the read information stored in the cache entry includes three fields: a data ready bit, an end flag, and a memory address.

The storage address and the end mark have the same meaning as the corresponding domain in the token information, and the specific values of the storage address and the end mark are from the token management module, as shown in fig. 3, the token management module 1021, after allocating a token for the read command, sends the token information to the reordering virtual channel module, where the channel identifier is used to select the reordering virtual channel, and the storage address and the end mark in the token information are stored in the selected reordering virtual channel.

For example, each reordering virtual channel has a pointer, the pointer points to the next cache entry to which read information is to be written, the storage address and the end mark are stored in the cache entry pointed by the pointer in the selected reordering virtual channel, and the current value of the pointer is returned to the token management module as an entry identifier and stored in the token information. The pointer then points to the next cache entry next to the neighbor, waiting for the read information to be written.

The data ready bit is used to indicate whether the read data of the read command is ready in the read data memory and can be read. For example, the data ready bit includes a ready state (e.g., 1) and an not ready state (e.g., 0), the ready state indicating that read data of the read command has been returned from the dynamic random access memory and stored in the read data memory, and can be read.

For example, when the read information is initially written to the cache entry, i.e., when the memory address and the end flag are written, the data ready bit in the read information is initialized to the not ready state.

For example, the rearrangement controller is further configured to, in response to receiving read data returned by the dynamic random access memory, extract token information located at the forefront of the scheduling token queue, and write the received read data into the read data memory according to a memory address in the read token information.

For example, when a read data is returned, for example, a read data valid signal is received, the foremost entry of the scheduling token queue is extracted, the storage address in the stored token information is taken as the write address of the read data memory, the read data is written into the position specified by the write address, and the data ready bit in the cache entry pointed by the channel identifier and the entry identifier in the token information is updated to the ready state.

For example, the reordering of virtual channel modules when performing managing and storing read information associated with a received read command includes performing the following operations: receiving token information of a token distributed for the current read command by a token management module aiming at the received current read command; determining a reordering virtual channel distributed for the current read command according to the token information of the current read command; determining a cache entry in the distributed reordering virtual channel, which is used for storing read information related to the current read command, and sending an entry identifier of the cache entry to a token management module to serve as an entry identifier in the token information of the current read command; taking the storage address and the end mark in the token information of the current read command as the storage address and the end mark in the read information of the current read command, and storing the storage address and the end mark into a cache entry; and in response to the read data of the current read command being returned from the dynamic random access memory and stored to the memory address in the read data memory, setting the data ready bit in the read information of the current read command to be in a ready state.

As shown in FIG. 3, the reorder virtual channel module 1022 also includes an arbitration unit.

The arbitration unit is configured to select a target valid data channel from all valid data channels.

For example, a reordered virtual lane includes at most one valid data lane, one valid data lane includes an ending cache entry in the reordered virtual lane and all cache entries located before the ending cache entry, and the data ready bits of all cache entries included in one valid data lane are in a ready state, where the ending cache entry is a cache entry in the reordered virtual lane whose first ending flag starts from the forefront of one reordered virtual lane and is valid.

For example, the rearrangement controller is further configured to, according to the storage address in the N cache entries included in the target valid data channel, sequentially read N read data from the read data memory in the order in which the N cache entries are stored in the target valid data channel, and sequentially return the read data to the bus, where N is a positive integer.

For example, the valid data lane is a reordered virtual lane, and starting from the head of the reordered virtual lane, the first end flag is a valid cache entry (end cache entry) and all cache entries before the valid cache entry, and the data ready bits of the cache entries are ready states. For example, there are 4 cache entries in a reordering virtual channel for storing read information, where, starting from the head of the reordering virtual channel, the end flag of the read information in the 1 st cache entry is invalid, the end flag of the read information in the 2 nd cache entry is valid, and the data ready bits of the read information in the 1 st and 2 nd cache entries are in ready states, at this time, the 2 nd cache entry is considered to be an end cache entry, the 1 st cache entry and the second cache entry form a valid data channel, if the valid data channel is selected as a target valid data channel, the 1 st cache entry and the 2 nd cache entry are read one by one, the read data corresponding to the 1 st cache entry is read first, and then the read data corresponding to the 2 nd cache entry is read.

A plurality of read commands corresponding to the same identifier are stored in one reordering virtual channel, and the read commands are arranged from the forefront end to the rearmost end of the reordering virtual channel according to the sending sequence, so that the end mark is valid data ready and all the previous data are ready, which indicates that all the read data belonging to the same read transaction are ready; and then, taking the storage address in the reading information stored in the cache entries as a reading address, sequentially reading corresponding reading data from the reading data memory according to the sequence of the cache entries from the forefront end to the rearmost end, and sequentially returning the reading data to the bus, so that the reading data can be sequentially returned according to the sending sequence of the reading commands, and reordering is realized.

Generally, read data corresponding to different read transactions need not be returned together, and read data (e.g., multiple read data) corresponding to the same read transaction need to be returned sequentially in the order of read command transmission. Therefore, the cache entry (end cache entry) with the first end mark as valid and all the cache entries before the first end mark are selected as valid data channels, so as to read the read data in sequence and return the read data; for cache entries in the reorder virtual channel whose other end markers are valid, they may not be part of the valid data channel because they belong to different read transactions.

For example, the arbitration unit is configured to select a target valid data channel from all valid data channels in a round-robin manner.

For example, a Round-Robin (Round-Robin) manner is performed to select a target valid data channel once every fixed time, e.g., once every clock cycle.

For example, for the round-robin operation executed in the current period, if an effective data lane exists in the re-ordering virtual lane RVC0 with the lane identifier of 0, the effective data lane is used as a target effective data lane to be read, and the reading process is as described above and is not described here again. Then, in the next round of cycle, it is determined whether there is an effective data channel in the reordered virtual channel RVC1 with channel identifier 1, if there is an effective data channel, the effective data channel is read as a target effective data channel, if there is no effective data channel, it is continuously determined whether there is an effective data channel in the reordered virtual channel RVC2 with channel identifier 2, if no effective data channel is found, the round does not perform reading, if all reordered virtual channels are traversed, it is determined that there is an effective data channel in the reordered virtual channel RVC0, the effective data channel is read as a target effective data channel. The above process is repeatedly executed, and is not described herein again.

Therefore, the probability of reading each reordering virtual channel can be averaged through a round-robin mode, each reordering virtual channel can be accessed, and load balancing is achieved.

For example, the token and reorder virtual channel are pre-allocated predetermined number of tokens and reorder virtual channels, which are dynamically mapped with read commands, e.g., the total number of tokens is limited, consistent with the storage depth of the read data memory, indicating the number of read data that can accommodate reordering.

When all the read data of a read transaction are reordered, the reordered read data are read from the read data memory and sent to the read data cache module, and the tokens of the read commands are not needed any more, the tokens of the read data from the read data memory can be recycled, and the reordered virtual channels can be recycled when needed.

For example, the token management module may be further configured to recycle tokens of read commands corresponding to read data read in response to read data being read from the read data memory.

For example, when the token management module executes a token for recovering a read command corresponding to read data, the following operations are performed: receiving the storage address of the read data in the read data memory, matching the read storage address of the read data with the distributed token, and recovering the token with the matched storage address; and determining a reordering virtual channel corresponding to the matched token according to the channel identifier of the matched token, and recovering the reordering virtual channel corresponding to the matched token in response to that cache entries in the reordering virtual channel corresponding to the matched token are all empty.

For example, the memory address of the read data comes from the arbitration unit, and after the arbitration unit selects the target valid data channel, the read information of the cache entries in the target valid data channel is sequentially read, and the read data is read from the read data memory by using the memory address of the read information in the cache entries as the read address. Meanwhile, the read address is simultaneously sent into a token management module to serve as an identifier to match the distributed tokens, and the matched tokens are recycled to be distributed to subsequent read commands; if the cache entries in the re-ordered virtual channel indicated by the channel identifier are all empty in the token information of the matching token, the re-ordered virtual channel is recycled (marked as unoccupied).

For example, the reorder controller may be further configured to, in response to the number of tokens that have been allocated reaching a maximum threshold, wait for tokens to be reclaimed and send a pause instruction to the command scheduler; the command scheduler is further configured to, in response to receiving the suspend instruction, suspend the received read command from entering the command queue.

For example, when the token distribution reaches an upper limit, the token management module may generate a pause instruction to pause the received read command from entering the command queue of the command scheduler, and at the same time, may not receive a new read command.

For example, when a pause instruction generated by the token management module is received, the command scheduler can no longer receive any read command operations.

For example, in the controller for a dynamic random access memory provided in at least one embodiment of the present disclosure, a selection module configured to turn on or turn off a reordering function according to a control instruction is further included.

For example, in response to the starting of the reordering function, all the read commands buffered in the command queue are scheduled out of order, and the read data corresponding to the read commands with the same identifier are reordered according to the order of the read commands with the same identifier entering the command scheduler and returned to the bus.

For example, in response to the reordering function being turned off, the read commands with different identifiers buffered in the command queue are scheduled out of order, and the read data corresponding to the read commands with different identifiers are returned to the bus in the scheduled order.

For example, by bypassing the read data memory when reordering of the read data is not required by the selection module, latency for data storage and reading can be reduced.

For example, the control instruction of the selection module may come from a configuration register, and a user may selectively turn on or off the read data reordering function according to needs through the configuration register.

It should be noted that most of the steps described above are executed in parallel, such as receiving a read command from a bus, scheduling the command out of order by a command scheduler, distributing and recycling tokens, and the like, so that the controller can process a large number of read commands in parallel, and the performance of the system is improved.

In the controller for the dynamic random access memory provided in the above embodiment, through the distribution of the token distribution and the allocation of the reordering virtual channels, the read data of a plurality of read commands with the same identifier can be strictly returned to the system bus according to the sequence of the received read commands, and the read commands can be scheduled out of order in the command scheduler to achieve the maximum performance of the dynamic random access memory access, thereby improving the performance of the system reading data, reducing the number of row closing and row opening times caused by row collision, and reducing the power consumption of the dynamic random access memory access; the read data returned out of order is reordered according to the identifier of the read command, so that the correctness of the data is ensured; for the reading commands of different identifiers, data return is carried out according to the principle of first-come first-serve, so that data delay is reduced, and system performance is improved; the hardware design architecture of the controller can be compatible with the design architecture of the current mainstream dynamic random access memory, is suitable for any type of dynamic random access memory and has wide application range.

Fig. 6 is a schematic flowchart of a control method for a dynamic random access memory according to at least one embodiment of the present disclosure. For example, the control method may be used to control a controller for a dynamic random access memory according to at least one embodiment of the present disclosure.

As shown in fig. 6, a control method for a dynamic random access memory according to at least one embodiment of the present disclosure includes steps S10 to S30.

In step S10, a read command is received from the bus and buffered in the command queue.

For example, each entry of a read command has an identifier, which is the identity of the corresponding transaction to which the read command belongs. For the detailed description of the identifier, reference may be made to the related contents of the aforementioned controller for the dynamic random access memory, and the detailed description is omitted here.

For example, in some examples, step S10 may include: aiming at a received current read command, a unique corresponding token is distributed for the current read command, wherein the token is used for distributing a reordering virtual channel and a storage address in a read data memory for the current read command, the read data memory is used for storing read data from a dynamic random access memory, and the reordering virtual channel and an identifier of the current read command have a one-to-one mapping relation; determining reading information related to the current reading command according to the token information of the token, and storing the reading information into a reordering virtual channel; and storing the token information and the current read command into a command queue.

As mentioned above, the controller includes a plurality of reordering virtual channels, each reordering virtual channel has a unique corresponding channel identifier, the channel identifier and the identifier of the read command have a dynamic mapping relationship, i.e. a one-to-one mapping relationship, the read information stored in one reordering virtual channel belongs to the read command with the same identifier, and the read information related to the read command with the same identifier is stored in the same reordering virtual channel for storage and management.

For example, the controller includes a read data memory, which may be a static random access memory, e.g., the read data memory having write addresses from the scheduling token queue and read addresses from the arbitration unit.

For example, if a read transaction may not be split, it is assigned a token as a read command; for a read transaction, such as a large-scale transmission, the read transaction is split into a plurality of read commands, and then a token is allocated to each read command.

For example, in some examples, assigning a unique corresponding token to a current read command may include: selecting an unused storage address from the read data memory as a storage address of the current read command in the read data memory; and distributing a reordering virtual channel for the current read command according to the identifier of the current read command.

For example, the data format of the token information of the token is shown in fig. 4, and the related contents may refer to the related description of the aforementioned controller, which is not described herein again.

For example, when a token is allocated each time, whether an already allocated reordering virtual channel exists is searched according to an identifier of a read command, and if so, a channel identifier of the allocated reordering virtual channel is directly used as a channel identifier in token information of the token; otherwise, an unoccupied reordering virtual channel is selected to be allocated to the current read command. For example, an unused memory address is selected from the read data memory as the memory address of the current read command in the read data memory.

The end flag is determined based on whether the read command corresponding to the token is the last read command sent in the corresponding transaction to which the token belongs. For example, for a plurality of split read commands, the end flag of the last sent read command is valid (e.g., 1), and the end flags of the remaining read commands are invalid (e.g., 0); for read commands that do not require splitting, the end flag is valid (e.g., 1).

The entry identifier is returned from the re-order virtual channel assigned by the current read command. For example, each reorder virtual channel may include multiple cache entries, one for storing read information associated with a read command, and each entry identifier may correspond to a cache entry. For example, a unique reordering virtual channel may be determined according to a channel identifier in the token information, an entry identifier is obtained by reordering a current position of a pointer in the virtual channel, the entry identifier indicates a cache entry into which read information related to a current read command is stored, and the entry identifier is returned to fill the token information.

After the distributed token is prepared, the token information is sent to the reordering virtual channel, so that the read information is generated according to the token information and stored in the reordering virtual channel; at the same time, token information is sent to the command scheduler and stored in a command queue in the command scheduler along with the read command.

For example, determining read information associated with the current read command according to the token information of the token and storing the read information in the reordering virtual channel may include: determining a reordering virtual channel according to the token information of the token; determining a cache entry used for storing read information in the reordering virtual channel; taking the storage address and the end mark in the token information as the storage address and the end mark in the reading information and storing the storage address and the end mark in a cache entry; and setting a data ready bit in the read information to be in a non-ready state.

For example, after obtaining the channel identifier, the storage address, and the end flag in the token information, sending these information to the reordering virtual channel, locating a reordering virtual channel through the channel identifier, writing the storage address and the end flag into the cache entry currently pointed to by the pointer in the reordering virtual channel, and setting the data ready bit in the read information stored in the cache entry to be in an unready state; meanwhile, the position of the pointer is returned as an entry identifier in the token information, and then the pointer points to the next cache entry to be written with the read information.

For the data format and the data field meaning of the read information, reference may be made to the aforementioned controller and the related description of fig. 5, and repeated descriptions are omitted.

In step S20, the read commands cached in the command queue are dispatched out of order and sequentially sent to the dynamic random access memory according to the dispatching order.

For example, step S20 may include: sequentially sending the scheduled read commands to the dynamic random access memory according to the scheduling sequence so as to read data; and according to the scheduling sequence, sending the token information of the token corresponding to the scheduled read command to a scheduling token queue.

For example, the scheduling token queue is configured to store token information of tokens corresponding to read commands that have been scheduled and have not returned read data in a scheduled order.

Here, the scheduling order may be any feasible scheduling order generated by the rule for maximizing the performance of the dynamic random access memory, for example, the scheduling order includes a mode of increasing the proportion of consecutive accesses to the same row of the same block, or an access mode of opening multiple blocks in parallel, and may also include other rules for optimizing the access efficiency of the dynamic random access memory.

For example, in the present disclosure, all read commands in the command queue, whether the identifiers are the same or different, may be scheduled out of order according to the performance maximization principle of the dynamic random access memory, so as to greatly improve the read data performance of the dynamic random access memory.

The scheduled read commands are sent to the dynamic random access memory, and corresponding token information is also sent to the scheduling token queue according to a scheduling order, for example, after the N read commands are scheduled, the command queue is empty, and the token information of the N read commands is sequentially stored in the scheduling token queue from the front end (head) to the rear end (tail) according to the scheduling order.

In step S30, the read data corresponding to the out-of-order scheduled read command returned from the dynamic random access memory according to the scheduling order is received, the read data corresponding to the read command with the same identifier is reordered according to the order of the read command with the same identifier entering the command scheduler, and returned to the bus.

For example, in some examples, step S30 may include: in response to receiving the read data returned according to the scheduling sequence, storing the current read data into a read data memory aiming at the received current read data, and updating a data ready bit of read information related to the current read data in a reordering virtual channel corresponding to the current read data to be in a ready state; selecting a target valid data channel, wherein the target valid data channel 5 channels comprise N cache entries, the N cache entries starting from the foremost end of the target valid data channel

The ending mark of the last cache entry in the N cache entries is valid, the ending marks of the rest N-1 cache entries are invalid, the data ready bits in the N cache entries are ready states, and N is a positive integer; according to the storage address in the read information in N cache entries included in the target effective data channel, according to N

And reading the read information of the cache entries into the sequence of the target effective data channel, reading N pieces of read data from the read data memory according to 0 time, and sequentially returning the read data to the bus.

For example, in some examples, in response to receiving read data returned in a scheduled order, for the received current read data, the current read data is stored in the read data memory, and a data ready bit of read information related to the current read data in a reordered virtual lane corresponding to the current read data is updated to ready

The states may include: reading token information positioned at the forefront end of the scheduling token queue, and writing current read data into a read data memory according to a memory address in the token information 5; determining a cache entry for storing read information related to a read command corresponding to current read data according to a channel identifier and an entry identifier in the token information; the data ready bit of the read information in the cache entry is updated to a ready state.

For example, the dynamic random access memory processes scheduled read commands in sequence and then returns read data in sequence, so the return sequence of read data is the same as the scheduling sequence.

0, every time one piece of read data is returned, firstly extracting token information from the Head of a scheduling token queue, and updating a data ready bit in a cache entry indicated by a channel identifier and an entry identifier in the token information into a ready state according to the channel identifier and the entry identifier in the token information; and simultaneously, taking the storage address in the token information as a write address, and writing the returned read data into the position indicated by the write address in the read data memory. Thereby, the returned respective read data are processed in order.

For example, in some examples, selecting a target valid data channel may include: selecting a target effective data channel from all effective data channels in a round-robin mode, wherein one reordering virtual channel at most comprises one effective data channel, one effective data channel comprises an ending cache entry in the reordering virtual channel and all cache entries positioned before the ending cache entry, and one effective data channel

The data ready bits of all the cache entries included in the data channel are in a ready state, and the end cache 0 entry is a cache entry in which a first end flag from the foremost end of a reordered virtual channel is valid.

For example, multiple reordering virtual lanes may have multiple target valid data lanes at the same time, which may be arbitration candidates.

The concept of the valid data channel can refer to the related contents in the aforementioned controller, and is not described herein again.

For the process of selecting the target valid data channel in the round-robin manner, reference may be made to the related contents in the foregoing controller, and details are not repeated here.

For example, during the round-robin process, if there is no valid data channel, the data is not read out in the round.

For example, after the target valid data channel is determined, the read information in the cache entries is sequentially read from the head (head) of the target valid data channel, the storage address in the read information is used as the read address, the data at the position indicated by the read address is sequentially read from the read data memory, and is sent to the read data cache module (e.g., FIFO queue), and finally is sequentially returned to the system bus.

For example, in some embodiments, the method further comprises returning read data corresponding to read commands with different identifiers to the bus in a scheduled order.

Therefore, in this embodiment, the read data of multiple read commands with the same identifier can be returned to the system bus strictly according to the sequence of the received read commands, and the read commands can be scheduled out of order in the command scheduler to achieve the maximum performance of the access of the dynamic random access memory, thereby improving the performance of the system read data, reducing the number of times of line closing and line opening caused by line collision, and reducing the power consumption of the access of the dynamic random access memory; for the read commands with different identifiers, data return is carried out according to the principle of first-come first-serve, so that data delay is reduced, and system performance is improved.

For example, the total number of tokens is limited, consistent with the storage depth of the read data memory, indicating the number of read data that can accommodate reordering.

For example, the control method provided in at least one embodiment of the present disclosure further includes: in response to read data being read from the read data memory, the token of the read command corresponding to the read data being read is reclaimed.

For example, in response to read data being read from the read data memory, reclaiming tokens of read commands corresponding to the read data read may include: receiving the storage address of the read data in the read data memory, matching the read storage address of the read data with the distributed token, and recovering the token with the matched storage address; and determining a reordering virtual channel corresponding to the matched token according to the channel identifier of the matched token, and recovering the reordering virtual channel corresponding to the matched token in response to that cache entries in the reordering virtual channel corresponding to the matched token are all empty.

For example, the memory address of the read data is from the selected target valid data channel, the read information of the cache entry in the target valid data channel is sequentially read, and the read data is read from the read data memory by using the memory address of the read information in the cache entry as the read address. Meanwhile, the read address is simultaneously sent into a token management module to serve as an identifier to match the distributed tokens, and the matched tokens are recycled to be distributed to subsequent read commands; if the cache entries in the re-ordered virtual channel indicated by the channel identifier are all empty in the token information of the matching token, the re-ordered virtual channel is recycled (marked as unoccupied).

Fig. 7 is a schematic control flow diagram for a dynamic random access memory according to at least one embodiment of the present disclosure. The entire control flow is described below with reference to fig. 7.

As shown in fig. 7, first, after receiving a read command from the bus, it is determined whether the token allocation has reached the upper limit. In response to the number of tokens that have been allocated reaching a maximum threshold, waiting for tokens to be recycled and sending a pause instruction to the command scheduler; in response to the suspend instruction, suspending entry of the received read command into the command queue.

For example, if the token assignment does not reach the upper limit, the bus interface controller splits the read transaction into one or more read commands, and then assigns a token to each read command.

For example, when a token is allocated, first determining whether an identifier of a read command has an already allocated reordering virtual channel, and if so, selecting the identifier of the already allocated reordering virtual channel to fill in the channel identifier in the token information; if not, a free reordering virtual channel is allocated for the read command, and the identifier of the free reordering virtual channel is filled in the channel identifier in the token information.

For example, when the token is distributed, an unused memory address is selected from the read data memory as the memory address of the current read command in the read data memory, and the memory address in the token information is filled.

For example, when the token is allocated, the end flag is determined according to whether the read command corresponding to the token is the last read command sent in the corresponding transaction to which the token belongs, and the specific process may refer to the relevant content in step S10, which is not described herein again.

For example, when the token is allocated, the entry identifier is obtained from the re-ordered virtual channel allocated by the current read command, and the specific process may refer to the relevant content in step S10, which is not described herein again.

Then, after the distributed token is prepared, the token information is sent to the reordering virtual channel, so that the read information is generated according to the token information and stored in the reordering virtual channel; at the same time, the token information is sent to the command scheduler and stored in a command queue in the command scheduler along with the read command. For a specific process, reference may be made to relevant contents in step S10, which is not described herein again.

And then, the read commands in the command queue are dispatched out of order, the dispatched read commands are sent to the DRAM interface controller, and the token information corresponding to the read commands is sent to the dispatching token queue. For a specific process, reference may be made to relevant contents in step S20, which is not described herein again.

And then, the waiting read data are sequentially returned from the dynamic random access memory according to the scheduling sequence. When read data are returned, extracting token information at the forefront end of the scheduling token queue, taking a storage address in the token information as a write address, and writing the read data into a position indicated by the write address in a read data memory; and updating the data ready bit in the cache entry indicated by the channel identifier and the entry identifier to a ready state according to the channel identifier and the entry identifier in the token information.

Then, judging whether an effective data channel exists or not, and if so, selecting a target effective data channel in a round robin mode; if not, the method continues to return to wait for new read data to return. For a specific process of selecting the target valid data channel, reference may be made to the related description in step S30, and details are not described here.

If the target effective data channel is selected, reading information of the cache entries in the target effective data channel in sequence, taking the storage address in the read information as a read address, and reading the read data from the read data memory; and meanwhile, recovering the token of the read data corresponding to the read command for the subsequent read command.

In the control method for the dynamic random access memory provided in the above embodiment, through the distribution of the token distribution and the distribution of the reordering virtual channels, the read data of multiple read commands with the same identifier can be strictly returned to the system bus according to the sequence of the received read commands, and the read commands can be scheduled out of order in the command scheduler to achieve the maximum access performance of the dynamic random access memory, thereby improving the performance of the system for reading data, reducing the number of times of closing and opening rows caused by row collision, and reducing the access power consumption of the dynamic random access memory; the read data returned out of order is reordered according to the identifier of the read command, so that the correctness of the data is ensured; and for the read commands of different identifiers, data return is carried out according to the principle of first-come first-serve, so that data delay is reduced, and system performance is improved.

In order to better understand at least one embodiment of the present disclosure, a controller and a control method for a dynamic random access memory are provided, and two embodiments are respectively provided in the present disclosure to describe a row collision problem and a block parallel problem of solving a read command of the same identifier by using the controller and the control method provided in the present disclosure.

Fig. 8A-8B are schematic diagrams illustrating a work flow of a controller for a dynamic random access memory according to an embodiment of the present disclosure. The controller described in the embodiments of fig. 8A to 8B and fig. 3 below describes the workflow of the controller and the control method provided by the present disclosure with respect to the row conflict problem caused by the same identifier.

It should be noted that the specific values shown in fig. 8A-8B are illustrative and do not limit the disclosure in any way. Also, steps between various read commands in the present disclosure may be performed in parallel, such as out-of-order scheduling, assigning tokens, token reclamation, and so forth.

Suppose the sequence of read commands entering the controller from the system bus is RD0 RD4, where RD0 is 1, RD1 RD3 are all 0, and RD4 is 2.RD 0-RD 4 all access DRAM block Bx, but the access rows are Ri, rj, and Ri, respectively. Because the identifiers of RD1 RD3 are the same, the current controller will generally schedule the three commands in the transmission order (RD 1, RD2, RD 3), and two RD0 RD4 will cause the row conflict of DRAM access, resulting in very low DRAM access efficiency.

In the controller and the control method provided in at least one embodiment of the present disclosure, there is no limitation to scheduling read commands according to a transmission sequence, and all read commands can be scheduled out of order according to the efficiency maximization of the DRAM, so as to avoid commands in row collision. The specific working process is as follows:

first, as shown in FIG. 8A, when read transactions RD0 RD4 from the system bus are received in order, each read transaction can be split into only one read command, and thus will be described as read commands RD0 RD4 hereinafter. And the token manager module in the rearrangement controller allocates one token for each read command and allocates the same rearrangement virtual channel for the read commands with the same identifier. For example, the read command RD0 is assigned the token 0, the read command RD1 is assigned the token 1, the read command RD2 is assigned the token 2, the read command RD3 is assigned the token 3, and the read command RD4 is assigned the token 4.

Since each read transaction can only be split into one read command, the end flag in the token information of 5 tokens is 1 (representing valid), and other data fields in the token, such as a storage address, a channel identifier, and an entry identifier, are obtained according to the related description of step S10 in the related process or control method in the controller, and are not described in detail here. For example, the token information of 5 tokens allocated is shown in the token queue of the token management module in fig. 8A. For example, read command RD0 is assigned a re-ordering virtual channel RVC0 having a channel identifier of 0, read commands RD1-RD3 have the same identifier, a re-ordering virtual channel RVC1 having a channel identifier of 1 is assigned, read command RD4 is assigned a re-ordering virtual channel RVC3 having a channel identifier of 3, and a re-ordering virtual channel RVC2 having a channel identifier of 2 is grayed out in FIG. 8A to indicate that it has been assigned to other read command identifiers.

After the token is allocated, as described in the foregoing step S10 and the read information part in the controller, the token information is sent to the reordering virtual channel, and read information is generated according to the token information and stored in the reordering virtual channel, for example, a storage address and an end indication in the token information are stored in a corresponding domain of the read information in a corresponding cache entry, and a data ready bit in the read information is updated to be 0 (not ready state), and the specific process may refer to the foregoing related contents, which is not described herein again.

For example, the status of the reordered vcls after writing the read information is shown in the reordered vcls module in fig. 8A, and RVC0 to RVC3 represent reordered virtual lanes with lane identifiers 0-3, respectively; each reordering virtual lane shows 3 cache entries with

entry identifiers

0, 1, 2, separated by black bold lines; each cache entry includes 3 data fields, namely a data ready bit, an end flag, and a memory address. For example, for the first cache entry (entry identifier 0) in the reordered virtual lane (RVC 1 in fig. 8A) with lane identifier 1, the data ready bit is 0, indicating that read data has not been returned, the end flag is 1, the token information from token 1, the storage address is 0x6, and the token information from token 1.

Meanwhile, the token information is sent to the command scheduler and stored in the command queue of the command scheduler together with the corresponding read command, and the token information is stored in the command queue of the command scheduler together with the corresponding read command, as shown in the command queue of the command scheduler in fig. 8A, the tokens 0 to 4 respectively represent the token information of the tokens 0 to 4, and the specific content is shown in the token queue of the token management module. At this point, no commands in the command queue have been scheduled yet, and thus there is no data in the scheduling token queue and the read data memory.

At this point, there are 5 read commands in the command queue, which would be first scheduled by the command scheduler, assuming read command RD4 has a high priority. After the read command RD4 is scheduled, the command scheduler schedules the remaining read commands in the command queue according to the performance maximization of the dynamic random access memory, and the read command RD4 accesses BxRi, so the read command RD2 (BxRi) hit by a row is selected; after the read command RD2 is scheduled, the remaining three read commands are all read commands that access BxRj. The read command RD0, the read command RD1 and the read command RD3 are scheduled in sequence on a first-come-first-served basis, assuming that the priorities are the same. Therefore, as shown in fig. 8B, the command queue in the command scheduler is empty, and 5 read commands are sequentially transmitted to the dynamic random access memory in the order of read command RD4, read command RD2, read command RD0, read command RD1, and read command RD3.

When a read command in one command queue is scheduled, the token information of the scheduled read command is simultaneously taken out and sent to the scheduling token queue of the rearrangement controller. After 5 read commands are scheduled, as shown in FIG. 8B, the command queue becomes empty and the data in the token queue is scheduled as shown in FIG. 8B.

After that, the dynamic random access memory processes the scheduled read commands in sequence, and then returns the read DATA in sequence, so the return sequence of the read DATA is the read DATA4 of the read command RD4, read DATA2 of the read command RD2, read DATA0 of the read command RD0, read DATA1 of the read command RD1, and read DATA3 of the read command RD3.

When a piece of read data is returned, firstly, a piece of token information is extracted from the Head of the dispatching token queue, and according to a channel identifier and an entry identifier in the token information, a data ready bit of the read information stored in a cache entry indicated by the channel identifier and the entry identifier is updated to be 1 (ready state).

For example, when the read DATA4 of the read command RD4 returns, the token information of the token 4 is fetched from the forefront of the scheduling token queue, and the channel identifier is 3 and the entry identifier is 0, so that the DATA ready bit of the cache entry with the entry identifier of 0 in the reordering virtual channel RVC3 with the channel identifier of 3 is updated to 1, as shown in fig. 8B; then, the read DATA is written into the read DATA memory according to the memory address in the token information, for example, the memory address is 9 in the token information of the token 4, and thus the read DATA4 is written into the memory area of the address 0x9 in the read DATA memory. This sequentially processes the read DATA2, the read DATA0, the read DATA1, and the read DATA3, which will not be described in detail herein, and the read DATA memory and the reorder dummy channel become the states as shown in fig. 8B, in which the order of read DATA writing is marked with circled numbers.

Then, each cycle of the arbitration unit in the reordering virtual channel module tries to select the target valid data channel for data reading and returning, and after the read data is returned, the reordering controller also recycles the token corresponding to the read data. The specific process is as follows.

For example, after the read DATA4 is returned, the DATA ready bit of the read information in the cache entry with entry identifier 0 in the reordering virtual channel RVC3 (hereinafter referred to as cache entry 3-0) becomes 1, and because the end flag of the read information in the cache entry is 1, the cache entry 3-0 constitutes a valid DATA channel as an arbitration alternative. At this time, since no other reordering virtual channel includes a valid data channel, the valid data channel is selected as the target valid data channel, and all cache entries in the target valid data channel are read until a cache entry with an end flag of 1 is encountered, i.e., read information in cache entry 3-0 in reordering virtual channel RVC3 is read. The memory address of the read information stored in the cache entry 3-0 is 0x9, so the DATA4 with the address of 0x9 in the read DATA memory is sent to the read DATA cache module and finally to the system bus. Meanwhile, the storage address in the cache entry 3-0 is sent to a token management module, and a token matched with the storage address 0x9 is found for recycling, namely a recycling token 4; in addition, the reordering virtual channel RVC3 corresponding to the channel identifier in the token information of token 4 is checked at the same time, and all cache entries in the reordering virtual channel are empty, so that the reordering virtual channel RVC3 is marked as not occupied.

Thereafter, when the read DATA2 is returned, the DATA ready bit of the read information in the cache entry (hereinafter referred to as cache entry 1-1) having the entry identifier 1 in the reordering virtual channel RVC1 becomes 1, and the read DATA2 is written to the memory address 0x7 in the read DATA memory. Since the data ready bit in the cache entry of entry identifier 0 in reordering virtual channel RVC1 is 0, and there is no valid data channel in reordering virtual channel RVC1, the target valid data channel is not selected in this round, and thus subsequent reading of the read data memory and recovery token is not performed.

Thereafter, when the read DATA0 is returned, the DATA ready bit of the read information in the cache entry (hereinafter referred to as cache entry 0-0) with entry identifier 0 in the reordering virtual lane RVC0 becomes 1, because the end flag of the read information in the cache entry is 1, so that the cache entry 0-0 constitutes a valid DATA lane as an arbitration candidate. At this time, since no other reordering virtual lanes include a valid data lane, the valid data lane is selected as the target valid data lane, and all cache entries in the target valid data lane are read until a cache entry with an end flag of 1 is encountered, i.e., read information in cache entries 0-0 in reordering virtual lane RVC0 is read. The memory address of the read information stored in the cache entry 0-0 is 0x5, so the DATA0 with the address of 0x5 in the read DATA memory is sent to the read DATA cache module and finally to the system bus. Meanwhile, the storage addresses in the cache entries 0-0 are sent to a token management module, and tokens matched with the storage addresses 0x5 are found for recycling, namely, the tokens 0 are recycled; in addition, the reordering virtual channel RVC0 corresponding to the channel identifier in the token information of token 0 is checked at the same time, and all cache entries in the reordering virtual channel are empty, so that the reordering virtual channel RVC0 is marked as unoccupied.

Thereafter, when the read DATA1 is returned, the DATA ready bit of the read information in the cache entry (hereinafter referred to as cache entry 1-0) having the entry identifier 0 in the reordering virtual channel RVC1 becomes 1, and the read DATA1 is written to the memory address 0x6 in the read DATA memory. Because the end of read information in the cache entry is marked as 1, cache entries 1-0 constitute a valid data channel as an arbitration candidate. At this time, since no other reordering virtual channel includes a valid data channel, the valid data channel is selected as the target valid data channel, and all cache entries in the target valid data channel are read until a cache entry with an end flag of 1 is encountered, i.e., read information in cache entries 1-0 in reordering virtual channel RVC1 is read. The memory address of the read information stored in the cache entry 1-0 is 0x6, so the DATA1 with the address of 0x6 in the read DATA memory is sent to the read DATA cache module and finally to the system bus. Meanwhile, the storage address in the cache entry 1-0 is sent to the token management module, and a token matched with the storage address 0x6 is found for recycling, namely, a token 1 is recycled. In addition, the reordering virtual channel RVC1 corresponding to the channel identifier in the token information of token 1 is also checked, and at this time, not all cache entries in the reordering virtual channel RVC1 are empty, so that the reordering virtual channel RVC1 is not recycled.

Thereafter, cache entry 1-0 is read out, and cache entry 1-1 is referred to as the front-most cache entry in reordering virtual channel RVC1, because the end flag of the read information in cache entry 1-1 is 1 and the data ready bit is 1, so that cache entry 1-1 constitutes an effective data channel as an arbitration alternative. In the next round-robin cycle, since no other reordering virtual channel includes a valid DATA channel, the valid DATA channel is selected as the target valid DATA channel, the read information in the cache entry 1-1 in the reordering virtual channel RVC1 is read, and the DATA2 with the address of 0x7 in the read DATA memory is sent to the read DATA cache module and finally sent to the system bus. Meanwhile, the storage address in the cache entry 1-1 is sent to a token management module, and a token matched with the storage address 0x7 is found for recycling, namely a token 2 is recycled. In addition, the reordering virtual channel RVC1 corresponding to the channel identifier in the token information of token 2 is also checked, and at this time, not all cache entries in the reordering virtual channel RVC1 are empty, so that the reordering virtual channel RVC1 is not recycled. It should be noted that, here, the round robin is executed once per cycle, and is executed in parallel with the relevant processing of the read data return.

Thereafter, when the read DATA3 is returned, the DATA ready bit of the read information in the cache entry having the entry identifier 2 (hereinafter referred to as cache entry 1-2) in the reordering virtual channel RVC1 becomes 1, and the read DATA3 is written to the memory address 0x8 in the read DATA memory. Because the end of read information in the cache entry is marked 1, cache entries 1-3 constitute a valid data channel as an arbitration candidate. Then, similarly to the above process, the DATA3 with the address of 0x8 in the read DATA memory is sent to the read DATA buffer module and finally sent to the system bus; and meanwhile, the token 3 and the reordering virtual channel RVC1 are recycled, and the detailed process is not repeated.

As can be seen from the above process and fig. 8B, the order of the read DATA returned to the system bus is DATA4, DATA0, DATA1, DATA2, and DATA3, which is different from the order in which the read DATA is returned by the DRAM (DATA 4, DATA2, DATA0, DATA1, and DATA 3), i.e., different from the scheduling order of the read commands. Therefore, the out-of-order scheduling of the read commands with the same identifier is realized, the read data bus sequence requires to return, for example, the read data corresponding to the read commands with the same identifier returns according to the sequence of sending the read commands, and the read data corresponding to the read commands with different identifiers returns according to the scheduling sequence. In addition, the scheduling sequence of the read commands is RD4, RD2, RD0, RD1, RD3, so that the row conflict is reduced from 3 times to 1 time, the performance of reading data is greatly improved, and the efficiency of reading data is improved.

Fig. 9A-9B are schematic diagrams illustrating a working flow of a controller for a dynamic random access memory according to another embodiment of the disclosure. The controller described in conjunction with the embodiments of fig. 9A to 9B and fig. 3 describes the workflow of the controller and the control method provided by the present disclosure with respect to the block parallel problem generated by the same identifier.

It should be noted that the specific values shown in fig. 9A-9B are illustrative and do not limit the disclosure in any way. Also, steps between various read commands in the present disclosure may be performed in parallel, such as out-of-order scheduling, assigning tokens, token reclamation, and so forth.

Assume that the sequence of read transactions from the system bus into the DRAM controller is RD0 RD2, with some time interval between read transaction RD1 and read transaction RD2 (assuming that read transaction RD2 comes after read transaction RD1 starts scheduling). The identifiers of the read transactions RD0 RD2 are 1,0 and 2, respectively, wherein the read transaction RD0 accesses BxRi of the DRAM, the read transaction RD2 accesses ByRj of the DRAM, and the read transaction RD1 can be split into two read commands (read command RD1-0 and read command RD 1-1) accessing BxRj and ByRj of the dynamic random access memory, respectively. Since read command RD1-0 and read command RD1-1 are split from the same read transaction, their identifiers are the same. Since read commands of the same identifier need to be executed in the order of transmission, the sequential scheduling of read transaction RD0 and read commands RD1-0 may result in row conflicts, resulting in very low DRAM access efficiency.

In the controller and the control method provided in at least one embodiment of the present disclosure, there is no limitation to scheduling read commands according to the sending order, and all read commands may be scheduled out of order according to the efficiency maximization of the DRAM, so as to avoid row conflict commands, for example, two different blocks (banks) accessed by the read transaction RD0 and the read command RD1-1, and the efficiency may be improved by fully utilizing the block parallelism through out-of-order scheduling. The specific working process is as follows:

first, as shown in FIG. 9A, when read transactions RD 0-RD 2 from the system bus are received in order, both read transactions RD0 and RD2 can be split into only one read command, and read transaction RD1 can be split into two read commands, and thus are described as read command RD0, read commands RD1-0, read command RD1-1, and read command RD4 hereinafter.

And the token manager module in the rearrangement controller allocates one token for each read command and allocates the same rearrangement virtual channel for the read commands with the same identifier. For example, token 0 is assigned to read command RD0, token 1 is assigned to read command RD1-0, token 2 is assigned to read command RD1-1, and token 3 is assigned to read command RD 2.

Because the read transaction RD1 can be split into two read commands RD1-0 and RD1-1, the read transaction RD1 can be completed only after the read command RD1-1 is completed, the end flag bit in the token 1 corresponding to the read command RD1-0 is 0, and the end flag bit in the token 2 corresponding to the read command RD1-1 is 1. The ending flag bits of

tokens

0 and 3 corresponding to the read command RD0 are both 1.

Other data fields in the token, such as the storage address, the channel identifier and the entry identifier, are obtained according to the related description of step S10 in the related flow or control method in the controller, and are not described in detail here. For example, the 4 cards allocated are as shown in the token queue of the token management module in fig. 9A. For example, read command RD0 assigns a reorder virtual channel with channel ID 1, read commands RD1-0 and RD1-1 have the same ID, a reorder virtual channel with channel ID 3 is assigned, read command RD2 assigns a reorder virtual channel with channel ID 4, and the reorder virtual channel with channel ID 2 is grayed out in FIG. 9A to indicate that it has been assigned to other read commands.

After the token is allocated, as described in step S10 and the controller with respect to the read information part, the token information is sent to the reordering virtual channel, so as to generate read information according to the token information and store the read information in the reordering virtual channel, for example, the storage address and the end indication in the token information are stored in the corresponding domain of the read information in the corresponding cache entry, and the data ready bit in the read information is updated to 0 (not ready state), and the specific process may refer to the above related contents, which is not described herein again.

For example, the status of the reordered vcfs after writing the read information is shown in the reordered virtual channel module in fig. 9A, where RVC1 to RVC4 respectively represent reordered virtual channels with channel identifiers 1-4; each reordering virtual lane shows 3 cache entries with

entry identifiers

0, 1, 2, separated by black bold lines; each cache entry includes 3 data fields, namely a data ready bit, an end flag, and a memory address. For example, for the first cache entry (entry identifier 0) in the reordered virtual lane (RVC 3 in fig. 9A) with lane identifier 3, the data ready bit is 0, indicating that read data has not been returned, the end flag is 0, it is from token information of token 1, the memory address is 10, and also from token information of token 1.

Meanwhile, the token information is sent to the command scheduler and stored in the command queue of the command scheduler together with the corresponding read command, and the token information is stored in the command queue of the command scheduler together with the corresponding read command, as shown in the command queue of the command scheduler in fig. 9A, the tokens 0 to 3 respectively represent the token information of the tokens 0 to 3, and specifically, as shown in the token queue of the token management module. At this point, no commands in the command queue have been scheduled yet, and thus there is no data in the scheduling token queue and the read data memory.

There are 4 read commands in the command queue, and first the read command RD0 is scheduled to access BxRi of the dynamic random access memory. After the read command RD0 is scheduled, the command scheduler schedules the remaining commands in the command queue according to the performance maximization principle of the dynamic random access memory; since directly scheduling read command RD1-0 may result in a row conflict, and read command RD1-1 may hide the latency of the row conflict with block parallelism, then read command RD1-1 is selected for scheduling (ByRj). After the read command RD1-1 is scheduled, the read command RD2 is scheduled in the same row of the same block as the read command RD1-1, and thus the read command RD2 is selected for scheduling. The read command RD1-0 is finally scheduled because it has a line collision with the read command RD0 but is a different block from the read command RD1-1 and the read command RD2, so that the read command RD1-0 is scheduled at the time of transferring the data of the read command RD1-1 and the read command RD2 using block parallel, hiding the delay of the line collision. Therefore, as shown in FIG. 9B, the command scheduler is empty, and 4 read commands are sequentially issued to the DRAM in the order of read command RD0, read command RD1-1, read command RD2, and read command RD 1-0.

When the read command in one command queue is scheduled, the token information of the scheduled read command is simultaneously taken out and sent to the scheduling token queue of the rearrangement controller. After 4 read commands are scheduled, as shown in FIG. 9B, the command queue becomes empty and the data in the token queue is scheduled as shown in FIG. 9B.

Thereafter, the DRAM sequentially processes the scheduled read commands and then sequentially returns the read DATA, so the read DATA is returned in the order of read DATA DATA0 of read command RD0, read DATA DATA1-1 of read command RD1-1, read DATA DATA2 of read command RD2, and read DATA DATA1-0 of read command RD 1-0.

When a piece of read data is returned, firstly, a piece of token information is extracted from the Head end (Head) of the dispatching token queue, and according to a channel identifier and an entry identifier in the token information, a data ready bit of the read information stored in a cache entry indicated by the channel identifier and the entry identifier is updated to be 1 (ready state).

For example, when the read DATA0 of the read command RD0 returns, the token information of the token 0 is fetched from the Head of the scheduling token queue, and the channel identifier is 1 and the entry identifier is 0, so that the DATA ready bit of the cache entry with the entry identifier 0 in the reordering virtual channel RVC1 with the channel identifier 1 is updated to 1, as shown in fig. 9B; then, the read DATA is written into the read DATA memory according to the memory address in the token information, for example, the memory address is 4 in the token information of the token 0, and thus the read DATA0 is written into the memory area of the address 0x4 in the read DATA memory. This sequentially processes the read DATA DATA1-1, the read DATA DATA2, and the read DATA DATA1-0, which will not be described in detail herein, and the read DATA memory and the reorder dummy channel become states as shown in FIG. 9B, in which the order of read DATA writing is marked with circled numbers.

Then, each cycle, the arbitration unit in the reorder virtual channel module tries to select the target valid data channel for data read and return, and recovers the token corresponding to the read data after the read data return. The specific process is as follows.

For example, after the read DATA0 is returned, the DATA ready bit of the read information in the cache entry (hereinafter referred to as cache entry 1-0 ') with entry identifier 0 in the reordering virtual channel RVC1 becomes 1, because the end flag of the read information in the cache entry is 1, so that the cache entry 1-0' constitutes a valid DATA channel as an arbitration alternative. At this time, since no other reordering virtual lane includes a valid data lane, the valid data lane is selected as the target valid data lane, and all cache entries in the target valid data lane are read until a cache entry with an end flag of 1 is encountered, i.e., read information in cache entries 1-0' in reordering virtual lane RVC1 is read. The memory address of the read information stored in the cache entry 1-0' is 4, so the DATA0 with the address 0x4 in the read DATA memory is sent to the read DATA cache module and finally to the system bus. Meanwhile, the storage address in the cache entry 1-0' is sent to a token management module, and a token matched with the storage address 0x4 is found for recycling, namely a recycling token 0; in addition, the reordering virtual channel RVC1 corresponding to the channel identifier in the token information of token 0 is checked at the same time, and all cache entries in the reordering virtual channel are empty, so that the reordering virtual channel RVC1 is marked as unoccupied.

Thereafter, when the read DATA1-1 is returned, the DATA ready bit of the read information in the cache entry having the entry identifier of 1 (hereinafter referred to as cache entry 3-1') in the reordering virtual channel RVC3 becomes 1, and the read DATA1-1 is written to the memory address 0xA in the read DATA memory. Since the data ready bit in the cache entry of entry identifier 0 in reordering virtual channel RVC3 is 0, and there is no valid data channel in reordering virtual channel RVC3 at this time, the target valid data channel is not selected in this round, and thus subsequent reading of the read data memory and recovery token are not performed.

Thereafter, when the read DATA2 is returned, the DATA ready bit of the read information in the cache entry (hereinafter referred to as cache entry 4-0') having the entry identifier 0 in the reordering virtual channel RVC4 becomes 1, and the read DATA2 is written to the memory address 0xD in the read DATA memory. Since the end of read information in the cache entry is marked 1, the cache entry 4-0' constitutes a valid data channel as an arbitration candidate. At this time, since no other reordering virtual channel includes a valid data channel, the valid data channel is selected as the target valid data channel, and all cache entries in the target valid data channel are read until a cache entry with an end flag of 1 is encountered, i.e., read information in cache entry 4-0' in reordering virtual channel RVC4 is read. The read information stored in the cache entry 4-0' has a storage address of 14, so that the DATA2 with an address of 0xD in the read DATA memory is sent to the read DATA cache module and finally to the system bus. Meanwhile, the storage address in the cache entry 4-0' is sent to a token management module, and a token matched with the storage address 0xD is found for recycling, namely a token 3 is recycled; in addition, the reordering virtual channel RVC4 corresponding to the channel identifier in the token information of token 3 is checked at the same time, and all cache entries in the reordering virtual channel are empty, so that the reordering virtual channel RVC4 is marked as unoccupied.

Thereafter, when the read DATA DATA1-0 is returned, the DATA ready bit of the read information in the cache entry having the entry identifier 0 (hereinafter referred to as cache entry 3-0') in the reordering virtual channel RVC3 becomes 1, and the read DATA DATA1-0 is written to the memory address 0xC in the read DATA memory. At this time, the re-ordered virtual channel RVC3 comprises a valid data channel comprising cache entry 3-0' and cache entry 3-1', wherein cache entry 3-1' is an ending cache entry, and the data ready bits of the read information stored in cache entry 3-0' and cache entry 3-1' are both 1, so that cache entry 3-0' and cache entry 3-1' form a valid data channel as an arbitration alternative. At this time, since no other reorder virtual channel includes a valid data channel, the valid data channel is selected as the target valid data channel, and all cache entries in the target valid data channel are read until a cache entry with an end flag of 1 is encountered, i.e., read information in cache entry 3-0 'and cache entry 3-1' in reorder virtual channel RVC3 is read. The memory address of the read information stored in the cache entry 3-0 'is 10, so the DATA DATA1-0 with address 0xA in the read DATA memory is sent to the read DATA cache module, and the memory address of the read information stored in the cache entry 3-1' is 13, so the DATA DATA1-1 with address 0xC in the read DATA memory is sent to the read DATA cache module, and finally sent to the system bus according to the sequence of the read DATA DATA1-0 and the read DATA DATA 1-1. Meanwhile, the storage address in the cache entry 3-0' is sent to a token management module, and a token matched with the storage address 0xA is found for recycling, namely a token 1 is recycled; the storage address in the cache entry 3-1' is sent to the token management module, and a token with a matching storage address of 0xC is found for recycling, that is, a recycling token 2. In addition, the reordering virtual channels RVC3 corresponding to the channel identifiers in the token information of token 1 and token 2 are checked at the same time, and all cache entries in the reordering virtual channels RVC3 are empty, so that the reordering virtual channels RVC3 are marked as unoccupied.

As can be seen from the above process and FIG. 9B, the order of the read DATA returned to the system bus is DATA0, DATA2, DATA1-0 and DATA1-1, which is different from the order in which the DRAM returns the read DATA (DATA 0, DATA1-1, DATA2 and DATA 1-0), i.e., the order in which the read commands are scheduled is different. Therefore, the read commands with the same identifier are dispatched out of order, and the read data bus is required to return in order, for example, the read data corresponding to the read commands with the same identifier are returned according to the order of sending the read commands, and the read data corresponding to the read commands with different identifiers are returned according to the dispatching order. The scheduling sequence of the read commands is read command RD0, read command RD1-1, read command RD2 and read command RD1-0, so that the line conflict of the read command RD0 and the read command RD1-0 is delayed and hidden in the block parallel access of the read command RD1-1/RD2, the performance of reading data is improved, and the efficiency of reading data is improved.

At least one embodiment of the present disclosure further provides an electronic device, and fig. 10 is a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 10, the electronic device 200 includes a controller 201 for a dynamic random access memory, and the controller 201 for the dynamic random access memory may adopt the structure of the controller 100 provided in at least one of the foregoing embodiments, and specific contents may refer to related contents of the controller 100 provided in the foregoing embodiments, and are not described herein again.

The controller 201 can achieve similar technical effects as the controller 100 for the dynamic random access memory described above, and will not be described in detail herein.

It should be noted that in the embodiment of the present disclosure, the electronic device 200 may include more or less circuits or units, and the connection relationship between the respective circuits or units is not limited and may be determined according to the actual requirements 5. The specific configuration of each circuit or unit is not limited, and may be in accordance with the circuit

The principle is constituted by an analog device, and may be constituted by a digital chip, or by another suitable method.

At least one embodiment of the present disclosure further provides an electronic device, and fig. 11 is a schematic diagram of another electronic device provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 11, the electronic device includes a processor 301, a communication interface 302, a memory 0303, and a communication bus 304. The processor 301, the communication interface 302, and the memory 303 communicate with each other via a communication bus 304, and the processor 301, the communication interface 302, and the memory 303 may communicate with each other via a network connection. The present disclosure is not limited herein as to the type and function of the network. It should be noted that the components of the electronic device shown in fig. 11 are only exemplary and not limiting, and the electronic device may have other components according to the actual application.

5 for example, the memory 303 is used to store computer readable instructions non-transiently. For processor 301

The control method for the dynamic random access memory according to any one of the above embodiments is implemented when the computer readable instructions are executed. For specific implementation and related explanation of each step of the control method for the dynamic random access memory, reference may be made to the above-mentioned embodiment of the control method for the dynamic random access memory, which is not described herein again.

0 for example, other implementation manners of the control method for the dynamic random access memory, which are implemented by the processor 301 executing the computer readable instructions stored in the memory 303, are the same as the implementation manners mentioned in the foregoing method embodiment portions, and are not described herein again.

For example, communication bus 304 may be a peripheral component interconnect standard (PCI) bus or the expansion industry

Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control 5 bus, etc. For convenience of illustration, only one thick line is shown, but not to indicate only one bus or

A type of bus.

For example, the communication interface 302 is used to enable communication between an electronic device and other devices.

For example, the processor 301 may control other components in the electronic device to perform desired functions.

The processor 301 may be a device having data processing capability and/or program execution capability, such as a Central Processing Unit (CPU), a Network Processor (NP), a Tensor Processor (TPU) 0, or a Graphics Processing Unit (GPU); and also

May be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The Central Processing Unit (CPU) may be an X86 or ARM architecture, etc.

For example, memory 303 may comprise any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer readable instructions may be stored on the computer readable storage medium and executed by processor 301 to implement various functions of the electronic device. Various application programs and various data and the like can also be stored in the storage medium.

For example, the detailed description of the process of executing data processing by the electronic device may refer to the related description in the embodiment of the control method for the dynamic random access memory, and repeated descriptions are omitted.

Fig. 12 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the disclosure. For example, as shown in fig. 12, the storage medium 400 may be a non-transitory computer-readable storage medium, on which one or more computer-readable instructions 301 may be non-temporarily stored on the storage medium 400. For example, the computer readable instructions 401, when executed by a processor, may perform one or more steps in a control method for a dynamic random access memory according to the above.

For example, the storage medium 400 may be applied to the above-described electronic device, and for example, the storage medium 400 may include a memory in the electronic device.

For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above, as well as other suitable storage media.

For example, the description of the storage medium 400 may refer to the description of the memory in the embodiment of the electronic device, and repeated descriptions are omitted.

Those skilled in the art will appreciate that the disclosure of the present disclosure is susceptible to numerous variations and modifications. For example, the various devices or components described above may be implemented in hardware, or may be implemented in software, firmware, or a combination of some or all of the three.

Further, while the present disclosure makes various references to certain elements of a system according to embodiments of the present disclosure, any number of different elements may be used and run on a client and/or server. The units are merely illustrative and different aspects of the systems and methods may use different units.

Flowcharts are used in this disclosure to illustrate the steps of methods according to embodiments of the disclosure. It should be understood that the preceding and following steps are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Also, other operations may be added to these processes.

It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by instructing the relevant hardware through a computer program, and the program may be stored in a computer readable storage medium, such as a read-only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiments may be implemented in the form of hardware, and may also be implemented in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The foregoing is illustrative of the present disclosure and is not to be construed as limiting thereof. Although a few exemplary embodiments of this disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present disclosure and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A controller for a dynamic random access memory, comprising:

the command scheduler comprises a command queue, is configured to receive a read command from a bus, cache the read command in the command queue 5, perform out-of-order scheduling on the read command cached in the command queue, and sequentially send the read command to the dynamic random access memory according to a scheduling order, wherein each item of the read command has an identifier, and the identifier is an identity of a corresponding transaction to which the read command belongs;

and the rearrangement controller is configured to receive the read data which is returned from the dynamic random access memory according to the scheduling sequence and corresponds to the read command out of the sequence scheduling, reorder the read data which corresponds to the read command with the same identifier and 0 according to the sequence of the read command with the same identifier entering the command scheduler, and return the read data to the bus.

2. The controller of claim 1, wherein the reorder controller comprises a token management module, a reorder virtual channel module, a schedule token queue, and a read data memory,

the token management module is configured to allocate a unique corresponding token for each received read command, and 5 the token is used to allocate a reordering virtual channel and a storage address in the read data memory for the corresponding read command;

the reordering virtual channel module comprises a plurality of reordering virtual channels and is configured to manage and store read information related to the received read commands, so as to reorder 0 rows of read data corresponding to the read commands with the same identifier according to the order of the read commands with the same identifier entering the command scheduler, wherein each reordering virtual channel has a unique corresponding channel identifier, the channel identifier has a dynamic mapping relation with the identifier of the read command, and the read information stored in one reordering virtual channel belongs to the read commands with the same identifier;

the scheduling token queue is configured to store token information of tokens corresponding to read commands which are scheduled and do not return read data according to the scheduling sequence;

5 the read data memory is configured to store read data from the dynamic random access memory.

3. The controller of claim 2, wherein the token management module, when executing assigning a unique corresponding token to each received read command, comprises:

selecting an unused storage address from the read data memory as a storage address of the current read command in the read data memory for the received current read command;

and 0, distributing a reordering virtual channel for the current read command according to the identifier of the current read command.

4. The controller of claim 3, wherein the token management module, when executing the assignment of the reordering virtual channel to the current read command according to the identifier of the current read command, comprises:

in response to the identifier of the current read command not being assigned a reordering virtual channel, selecting an unoccupied reordering virtual channel as the reordering virtual channel corresponding to the current read command;

in response to the identifier of the current read command having been assigned a re-ordered virtual channel, treating the assigned re-ordered virtual channel as a re-ordered virtual channel corresponding to the current read command.

5. The controller of claim 2, wherein each reordering virtual lane comprises a plurality of cache entries, one cache entry for storing read information associated with one read command,

the token information of the token includes a storage address, an end flag, a channel identifier and an entry identifier,

the storage address is used for indicating the address of the read data of the read command corresponding to the token stored in the read data memory;

the end mark is used for indicating whether the read command corresponding to the token is the read command sent last in the corresponding transaction to which the token belongs;

the channel identifier is used for indicating a reordering virtual channel for storing read information related to a read command corresponding to the token;

the entry identifier is used for indicating the position of a cache entry storing the read information related to the read command corresponding to the token in a reordering virtual channel allocated for the read command corresponding to the token.

6. The controller of claim 5, wherein each reordering virtual lane is a first-in-first-out storage queue and each cache entry is a queue element in the first-in-first-out storage queue.

7. The controller of claim 5, wherein the read information associated with each read command includes a data ready bit, an end flag, and a memory address,

the data ready bit is used to indicate whether read data of the read command is ready in the read data memory and can be read,

when the reordering virtual channel module executes management and storage of read information related to the received read command, the reordering virtual channel module executes the following operations:

receiving token information of a token distributed for the current read command by a token management module aiming at the received current read command;

determining a reordering virtual channel allocated to the current read command according to the token information of the current read command;

determining a cache entry in the allocated reordering virtual channel, which is used for storing read information related to the current read command, and sending an entry identifier of the cache entry to the token management module, so as to serve as an entry identifier in the token information of the current read command;

taking the storage address and the end mark in the token information of the current read command as the storage address and the end mark in the reading information of the current read command, and storing the storage address and the end mark in the cache entry;

and responding to the read data of the current read command, returning from the dynamic random access memory and storing the read data to the storage address in the read data memory, and setting a data ready bit in the read information of the current read command to be in a ready state.

8. The controller of claim 7, wherein the reorder virtual channel module further comprises an arbitration unit,

the data ready bit is a ready state indicating that the data of the read command is ready in the read data memory and can be read,

the arbitration unit is configured to select a target effective data channel from all effective data channels in a round robin manner, wherein one reordered virtual channel at most comprises one effective data channel, the one effective data channel comprises an ending cache entry in the one reordered virtual channel and all cache entries before the ending cache entry, data ready bits of all cache entries in the one effective data channel are in a ready state, and the ending cache entry is a cache entry with a first ending mark from the foremost end of the one reordered virtual channel in the one reordered virtual channel as effective;

the rearrangement controller is further configured to, according to a storage address in N cache entries included in the target valid data channel, sequentially read N read data from the read data memory in an order in which the N cache entries are stored in the target valid data channel, and sequentially return the read data to the bus, where N is a positive integer.

9. The controller of claim 2, wherein the command scheduler is further configured to:

receiving token information of a token corresponding to each read command from the token management module, and storing the read command and the corresponding token information into the command queue correspondingly; and

and sending token information of the token corresponding to the scheduled read command to the scheduling token queue.

10. The controller according to claim 9, wherein the reordering controller is further configured to, in response to receiving read data returned from the dynamic random access memory, retrieve token information located at a forefront of the scheduling token queue, and write the received read data into the read data memory according to a memory address in the read token information.

11. The controller of claim 2, wherein the token management module is further configured to recycle tokens of read commands corresponding to read data read in response to read data being read from the read data memory.

12. The controller of claim 11, wherein the token management module, when executing the token recycling of the read command corresponding to the read data, comprises:

receiving the storage address of the read data in the read data memory, matching the read data storage address with the distributed token, and recycling the token with the matched storage address;

and determining a reordering virtual channel corresponding to the matched token according to the channel identifier of the matched token, and recovering the reordering virtual channel corresponding to the matched token in response to that cache entries in the reordering virtual channel corresponding to the matched token are all empty.

13. The controller of claim 1, wherein the reorder controller is further configured to return read data corresponding to read commands having different identifiers to the bus in the scheduled order.

14. The controller of claim 2, wherein the reorder controller is further configured to, in response to the number of tokens that have been allocated reaching a maximum threshold, wait for a recycle token and send a pause instruction to the command scheduler;

the command scheduler is further configured to, in response to receiving the pause instruction, pause entry of the received read command into the command queue.

15. The controller according to claim 1, wherein the reordering controller further comprises a selection module configured to turn on or off a reordering function according to a control command,

when the reordering function is started, all the read commands cached in the command queue are dispatched out of order, and the read data corresponding to the read commands with the same identifier are reordered according to the sequence of the read commands with the same identifier entering the command dispatcher and returned to the bus;

and responding to the closing of the reordering function, performing out-of-order scheduling on the read commands with different identifiers cached in the command queue, and returning read data corresponding to the read commands with different identifiers to the bus according to the scheduling sequence.

16. The controller of claim 1, further comprising a bus interface controller,

wherein the bus interface controller is configured to:

receiving a read transaction from the bus, converting the read transaction into at least one read command and sending the at least one read command to the command scheduler and the rearrangement controller, wherein the identifier of the at least one read command is the identifier of the read transaction.

17. A control method for a dynamic random access memory, comprising:

receiving a read command from a bus and caching the read command in a command queue, wherein each item of the read command has an identifier which is the identity of a corresponding transaction to which the read command belongs;

out-of-order scheduling is carried out on the read commands cached in the command queue and the read commands are sequentially sent to the dynamic random access memory according to a scheduling order;

and receiving read data which are returned from the dynamic random access memory according to the scheduling sequence and correspond to the read commands scheduled out of order, reordering the read data corresponding to the read commands with the same identifier according to the sequence of the read commands with the same identifier entering the command scheduler, and returning the read data to the bus.

18. The control method of claim 17, wherein receiving a read command from a bus and buffering the read command in a command queue comprises:

for a received current read command, allocating a unique corresponding token for the current read command, wherein the token is used for allocating a reordering virtual channel and a storage address in a read data memory for the current read command, the read data memory is used for storing read data from the dynamic random access memory, and the reordering virtual channel has a one-to-one mapping relation with an identifier of the current read command;

according to the token information of the token, determining reading information related to the current reading command, and storing the reading information into the reordering virtual channel;

and storing the token information and the current read command into the command queue.

19. The method of claim 18, wherein assigning the current read command a unique corresponding token comprises:

selecting an unused storage address from the read data storage as the storage address of the current read command in the read data storage;

and distributing a reordering virtual channel for the current read command according to the identifier of the current read command.

20. The control method of claim 18, wherein the read information includes a data ready bit, an end flag, and a storage address,

the data ready bit is used to indicate whether the data of the current read command is ready in the read data memory and can be read,

the end flag is used to indicate whether the current read command is the last read command sent in the corresponding transaction to which the current read command belongs,

the storage address is used for indicating the address of the read data of the current read command stored in the read data memory,

determining the reading information related to the current reading command according to the token information of the token, and storing the reading information into the reordering virtual channel, wherein the reading information comprises:

determining a reordering virtual channel according to the token information of the token;

determining a cache entry used for storing the read information in the reordering virtual channel;

taking the storage address and the end mark in the token information as the storage address and the end mark in the reading information and storing the storage address and the end mark in the cache entry;

and setting a data ready bit in the read information to be in an un-ready state.

21. The control method according to claim 17, wherein the out-of-order scheduling of the read commands buffered in the command queue and the sequential sending to the dynamic random access memory according to the scheduling order comprises:

sequentially sending the scheduled read commands to the dynamic random access memory according to the scheduling sequence so as to read data;

and sending token information of tokens corresponding to the scheduled read commands to a scheduling token queue according to the scheduling sequence, wherein the scheduling token queue is configured to store the token information of tokens corresponding to the read commands which are scheduled and do not return read data according to the scheduling sequence.

22. The control method according to claim 17, wherein receiving read data corresponding to the out-of-order scheduled read commands returned from the dynamic random access memory in the scheduling order, reordering the read data corresponding to the read commands having the same identifier in the order in which the read commands having the same identifier entered the command scheduler, and returning the read data to the bus comprises:

in response to receiving the read data returned according to the scheduling sequence, storing the current read data into the read data memory for the received current read data, and updating a data ready bit of read information related to the current read data in a reordering virtual channel corresponding to the current read data to be in a ready state;

selecting a target valid data channel, wherein the target valid data channel comprises N cache entries, and starting from the foremost end of the target valid data channel, an end mark of the last cache entry in the N cache entries is valid, end marks of the rest N-1 cache entries are invalid, data ready bits in the N cache entries are ready states, and N is a positive integer;

and sequentially reading N pieces of read data from the read data memory according to the storage addresses in the read information in the N cache entries included in the target effective data channel and the sequence of storing the read information of the N cache entries into the target effective data channel, and sequentially returning the N pieces of read data to the bus.

23. The control method of claim 22, wherein in response to receiving read data returned in the scheduling order, for the received current read data, storing the current read data in the read data memory, and updating a data ready bit of read information related to the current read data in a re-ordered virtual channel corresponding to the current read data to a ready state, comprises:

reading token information positioned at the forefront end of the scheduling token queue, and writing the current read data into the read data memory according to a storage address 5 in the token information;

determining a cache entry for storing read information related to a read command corresponding to the current read data according to a channel identifier and an entry identifier in the token information;

and updating the data ready bit of the read information in the cache entry to be in a ready state.

24. The control method of claim 21, wherein selecting a target valid data channel, 0, comprises:

selecting the target effective data channel from all effective data channels in a round-robin manner, wherein one reordered virtual channel at most comprises one effective data channel, the one effective data channel comprises an ending cache entry in the one reordered virtual channel and all cache entries positioned before the ending cache entry, data ready bits of all cache entries 5 included in the one effective data channel are in a ready state, and the ending cache entry is a cache entry in which a first ending mark from the foremost end of the one reordered virtual channel in the one reordered virtual channel is effective.

25. The control method according to claim 17, further comprising:

and returning read data corresponding to the read commands with different identifiers to the bus 0 according to the scheduling sequence.

26. The control method according to claim 17, further comprising:

in response to read data being read from the read data memory, a token of a read command corresponding to the read data being read is recovered.

27. An electronic device comprising a controller for a dynamic random access memory 5 as claimed in claims 1-16.

28. An electronic device, comprising:

a memory non-transiently storing computer-executable instructions;

a processor configured to execute the computer-executable instructions,

wherein the computer executable instructions, when executed by the processor, implement the control method of any one of claims 017-26.

29. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the control method of any one of claims 17-26.