CN115935890A - Circuit identification method and device, electronic equipment and computer readable storage medium - Google Patents
Circuit identification method and device, electronic equipment and computer readable storage medium Download PDFInfo
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Abstract
The application relates to a circuit identification method, a circuit identification device, electronic equipment and a computer readable storage medium, and belongs to the field of electronic circuits. The circuit identification method comprises the following steps: acquiring a circuit to be identified; searching whether a preset model circuit exists in the circuit to be identified, wherein the model circuit is extracted from a specified combined circuit in advance; and if all the model circuits exist in the circuit to be identified, determining that the circuit to be identified comprises the specified combined circuit. The circuit identification method provided by the application can accurately and efficiently identify whether the circuit to be identified comprises the appointed combined circuit or not so as to make up for the defect of the existing circuit identification method in the aspect of identifying the user-defined combined ESD protection circuit, and thus, a comprehensive and reliable ESD protection circuit identification method is provided for designers.
Description
Technical Field
The present application relates to the field of electronic circuits, and in particular, to a circuit identification method and apparatus, an electronic device, and a computer-readable storage medium.
Background
Static electricity is generated in various environments such as production, testing, application, etc., which can cause sudden and potential damage to integrated circuits. Sudden damage can result in loss of circuit function, and potential damage can destabilize circuit function and may even cause greater loss. Therefore, electrostatic protection and damage prevention are well achieved, and the method has very important practical significance for integrated circuits.
At present, a typical ESD (Electro Static Discharge) protection circuit is mostly formed by a single-stage device, which also results in that the identification method of the protection circuit is also based on the single-stage device as the identification unit. The circuit identification method can quickly identify whether a typical ESD protection device exists in a target circuit according to the type and the connection characteristics of the specified single-stage device. Taking fig. 1 as an example, for an NMOS device located between a Power line VDD and a ground line VSS, a drain terminal of the NMOS device is connected to VDD, a source terminal is connected to VSS, and a gate terminal is connected to non-VDD and non-VSS, which belongs to the connection characteristics of a typical Clamp NMOS, and can be accurately and quickly identified as Power Clamp (a voltage Clamp circuit, which is one of ESD protection circuits) by the identification method.
In actual circuit design, however, custom ESD protection circuits are often designed and used to provide protection capability that matches the design. However, the current circuit identification method has a better effect for identifying a single-stage device with typical connection characteristics, and has a poor effect for identifying an atypical or complex combined circuit, so that additional labor and time are required for verifying a customized ESD protection circuit.
Disclosure of Invention
In view of the above, an object of the present application is to provide a circuit identification method, an apparatus, an electronic device and a computer readable storage medium, so as to improve the problem that the identification effect of the existing circuit identification method on the combinational circuit is not ideal.
The embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a circuit identification method, including: acquiring a circuit to be identified; searching whether a preset model circuit exists in the circuit to be identified, wherein the model circuit is extracted from a specified combined circuit in advance; and if all the model circuits exist in the circuit to be identified, determining that the circuit to be identified comprises the specified combined circuit.
In the embodiment of the application, the model circuit is extracted from the designated combined circuit in advance, and then when the circuit to be identified is identified, whether the preset model circuit exists or not is searched in the circuit to be identified, if all the model circuits exist in the circuit to be identified, the circuit to be identified can be determined to contain the designated combined circuit, so that whether the circuit to be identified contains the designated combined circuit or not can be accurately and efficiently identified, the defect of the existing circuit identification method in the aspect of identifying the customized combined ESD protection circuit is overcome, and a comprehensive and reliable ESD protection circuit identification method is provided for a designer.
With reference to one possible implementation manner of the embodiment of the first aspect, the model circuit includes a MOS transistor circuit; whether a preset model circuit exists in the circuit to be identified or not is searched, and the method comprises the following steps: extracting the device type and the connection characteristics of key devices in the MOS transistor circuit; searching a target device matched with the device type and the connection characteristics of the key device in the circuit to be identified; checking whether the connection condition of the periphery of the target device is matched with the model circuit or not by taking the target device as a base point; and if the connection condition of the periphery of the target device is matched with the model circuit, representing that the model circuit exists in the circuit to be identified.
In the embodiment of the application, when the model circuit comprises the MOS transistor circuit, the device type and the connection characteristics of key devices in the MOS transistor circuit are extracted firstly, so that a target device matched with the device is searched, and whether the connection condition of the periphery of the target device is matched with the model circuit is checked by taking the target device as a base point, so that whether the MOS transistor circuit exists in the circuit to be identified can be quickly determined.
With reference to one possible implementation manner of the embodiment of the first aspect, before determining that the circuit to be identified includes the specified combinational circuit, the method further includes: recording the success times of matching the model circuit; determining that the number of successes is not less than the number of occurrences of the model circuit in the designated combinatorial circuit.
In the embodiment of the application, considering that the same model circuit may appear in the designated combinational circuit for multiple times, in order to improve the identification accuracy, before determining that the circuit to be identified contains the designated combinational circuit, the success frequency of the matching of the model circuit is recorded, and when determining that the success frequency is not less than the frequency of the model circuit appearing in the designated combinational circuit, the identification accuracy is improved.
With reference to one possible implementation manner of the embodiment of the first aspect, the critical device is a device with the smallest connection feature among all devices included in the MOS transistor circuit.
In the embodiment of the application, because the connection features of the key devices are less than those of other devices in the MOS transistor circuit, the speed of matching the target device can be increased, and if the corresponding target device is not matched, it is not necessary to continue the backward matching (i.e., check whether the connection condition around the target device matches the model circuit), thereby increasing the search efficiency.
With reference to one possible implementation manner of the embodiment of the first aspect, the model circuit is a MOS transistor circuit, and the step of extracting the MOS transistor circuit from the designated combination circuit includes: and extracting a first combined circuit which is only composed of MOS transistors and has a unique circuit structure from the specified combined circuit to obtain the MOS transistor circuit, and recording the occurrence frequency of the MOS transistor circuit in the specified combined circuit.
In the embodiment of the application, a first combined circuit which is only composed of MOS transistors and has a unique circuit structure is extracted to form a model circuit, so that poor matching effect is avoided during matching; meanwhile, the occurrence frequency of the MOS transistor circuit in the appointed combined circuit is recorded, so that whether the successful frequency of the matched MOS transistor circuit is not less than the occurrence frequency of the MOS transistor circuit in the appointed combined circuit is judged after the MOS transistor circuit is found in the circuit to be identified subsequently, and the identification accuracy is improved.
In combination with a possible implementation manner of the embodiment of the first aspect, the model circuit includes a circuit of a specific device, and the specific device includes a resistor, a capacitor, or a diode; whether a preset model circuit exists in the circuit to be identified or not is searched, and the method comprises the following steps: extracting the external connection characteristics of the specified device circuit pair; searching whether a target circuit matched with the connection characteristics of the specified device circuit exists in the circuit to be identified; and if the target circuit exists, representing that the model circuit exists in the circuit to be identified.
In the embodiment of the application, when the model circuit comprises a specified device circuit such as a resistor, a capacitor or a diode, the external connection characteristic of the specified device circuit is extracted to find whether a target circuit matched with the connection characteristic exists in the circuit to be identified, so that the model circuit existing in the circuit to be identified can be quickly determined.
With reference to a possible implementation manner of the embodiment of the first aspect, before determining that the circuit to be identified includes the designated combination circuit, the method further includes: acquiring the cascade stage number of the designated device in the target circuit; and determining that the cascade number of the specified device in the target circuit is not less than the cascade number of the specified device circuit.
In the embodiment of the application, when the designated combinational circuit is extracted, the combinational circuit which is formed by only interconnection of designated devices and has a unique circuit structure is abstracted into one designated device, so that before the matched target circuit is determined to contain the designated combinational circuit, the cascade stage number of the designated devices in the target circuit is further determined to be not less than the cascade frequency of the designated device circuit before the circuit to be identified is determined to contain the designated combinational circuit, and the identification accuracy is improved.
With reference to one possible implementation manner of the embodiment of the first aspect, the step of extracting the specified device circuit from the specified combination circuit includes: a second combined circuit which is extracted from the appointed combined circuit, is only formed by interconnection of the appointed devices and has a unique circuit structure; abstracting the second combined circuit into the designated device, taking the external connection feature of the second combined circuit as the connection feature of the designated device to obtain the designated device circuit, and recording the cascade stage number of the designated device circuit, wherein the cascade stage number of the designated device circuit is consistent with the cascade stage number of the designated device in the second combined circuit.
In the embodiment of the application, a second combined circuit which is only formed by interconnection of specified devices and has a unique circuit structure is abstracted into one specified device, so that matching efficiency can be improved, and meanwhile, the cascade stage number of the specified device circuit is recorded, so that whether the cascade stage number of the specified device in the target circuit is not less than the cascade frequency of the specified device circuit is determined after a target circuit which is consistent with the external connection characteristics of the specified device circuit is matched, and identification accuracy is guaranteed.
In a second aspect, an embodiment of the present application further provides a circuit identification apparatus, including: the device comprises an acquisition module and a processing module; the acquisition module is used for acquiring a circuit to be identified; the processing module is used for searching whether a preset model circuit exists in the circuit to be identified, and the model circuit is extracted from a specified combined circuit in advance; and if all the model circuits exist in the circuit to be identified, determining that the circuit to be identified comprises the specified combined circuit.
In combination with one possible implementation manner of the embodiment of the second aspect, the model circuit includes a MOS transistor circuit; the processing module is configured to: extracting the device type and the connection characteristics of key devices in the MOS transistor circuit; searching a target device matched with the device type and the connection characteristics of the key device in the circuit to be identified; checking whether the connection condition of the periphery of the target device is matched with the model circuit or not by taking the target device as a base point; and if the connection condition of the periphery of the target device is matched with the model circuit, representing that the model circuit exists in the circuit to be identified.
In combination with one possible implementation of the embodiment of the second aspect, the model circuit includes a specific device circuit, where the specific device includes a resistor, a capacitor, or a diode; the processing module is configured to: extracting the external connection characteristics of the specified device circuit pair; searching whether a target circuit matched with the connection characteristics of the specified device circuit exists in the circuit to be identified; and if the target circuit exists, representing that the model circuit exists in the circuit to be identified.
With reference to a possible implementation manner of the embodiment of the second aspect, the processing module is further configured to extract, from the designated combination circuit, a first combination circuit which is only composed of MOS transistors and has a unique circuit structure, obtain the MOS transistor circuit, and record the occurrence number of the MOS transistor circuit in the designated combination circuit.
With reference to a possible implementation manner of the embodiment of the second aspect, the processing module is further configured to extract, from the designated combinational circuit, a second combinational circuit, which is formed by only interconnection of the designated devices and has a unique circuit structure; abstracting the second combined circuit into the designated device, taking the external connection feature of the second combined circuit as the connection feature of the designated device to obtain the designated device circuit, and recording the cascade stage number of the designated device circuit, wherein the cascade stage number of the designated device circuit is consistent with the cascade stage number of the designated device in the second combined circuit.
In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory and a processor, the processor coupled to the memory; the memory is used for storing programs; the processor is configured to invoke a program stored in the memory to perform the method according to the first aspect embodiment and/or any possible implementation manner of the first aspect embodiment.
In a fourth aspect, this application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the method in the foregoing first aspect and/or any possible implementation manner of the first aspect.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.
Fig. 1 is a schematic diagram of a conventional protection circuit composed of a single-stage device.
Fig. 2 is a schematic flowchart illustrating a circuit identification method according to an embodiment of the present application.
Fig. 3 is a schematic diagram illustrating a circuit for extracting a model from a custom combination according to an embodiment of the present application.
FIG. 4 is a schematic diagram illustrating a circuit for extracting a model from another custom combination according to an embodiment of the present application.
Fig. 5 shows a schematic diagram of a customized ESD protection circuit provided in an embodiment of the present application.
Fig. 6 shows a block diagram of a circuit identification device according to an embodiment of the present application.
Fig. 7 shows a block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.
In view of the problem that the effect is not ideal when the existing circuit identification method is used for identifying atypical or custom combination circuits with complex structures, and extra labor and time are required to be invested when the custom ESD protection circuits are verified, the embodiment of the application provides a circuit identification method which can accurately and efficiently identify whether the circuits to be identified contain the appointed combination circuits, so as to make up the defect of the existing circuit identification method in the aspect of identifying the custom combination ESD protection circuits, and provide a comprehensive and reliable ESD protection circuit identification method for designers.
The circuit identification method provided by the embodiment of the present application will be described below with reference to fig. 2.
S1: and acquiring a circuit to be identified.
And when a certain circuit needs to be identified, acquiring a corresponding circuit to be identified. The circuit to be identified can be some custom combination circuit with a relatively complex structure.
In one embodiment, the circuit to be identified may be obtained in a form of a picture, and the circuit to be identified may be obtained from the picture, or may be obtained in another form.
S2: and searching whether a preset model circuit exists in the circuit to be identified.
It should be noted that, the model circuit in the present application is extracted from the designated combinational circuit (for example, the designated combinational circuit a) in advance, after the model circuit is extracted from the designated combinational circuit, when the circuit to be identified is identified, whether a preset model circuit exists in the circuit to be identified is searched, and if all the model circuits exist in the circuit to be identified, it can be determined that the circuit to be identified includes the designated combinational circuit.
If the circuit to be identified does not have all model circuits, the model circuit may be replaced, for example, the model circuit is replaced with a model circuit extracted from another specified combination circuit (e.g., specified combination circuit B), and then whether the circuit to be identified has a model circuit after replacement is searched, wherein the principle of searching whether the circuit to be identified has the model circuit after replacement is the same as the principle of searching whether the circuit to be identified has the model circuit before replacement. The model circuit after replacement is extracted from the designated combination circuit in advance, similarly to the model circuit before replacement, but the model circuit after replacement is extracted from the designated combination circuit B.
For example, suppose that N (an integer greater than or equal to 1) model circuits corresponding to different designated combination circuits are extracted in advance, when a circuit to be identified is identified, whether a preset model circuit (from the designated combination circuit 1) exists in the circuit to be identified is checked, if not, whether a preset model circuit (from the designated combination circuit 2) exists in the circuit to be identified is checked, and so on until it is determined that the circuit to be identified includes the designated combination circuit (assuming that the designated combination circuit M is a positive integer and is less than or equal to N), or until model circuits corresponding to all the designated combination circuits are searched.
For different specific combination circuits, different model circuits are corresponded, and taking an ESD protection combination circuit as an example, the ESD protection combination circuit can be generally decomposed to include a MOS transistor circuit and other circuits, and the other circuits can be at least one of a resistor circuit, a capacitor circuit, a diode circuit, and the like. It is to be understood that the circuit identification methods shown herein are not limited to identifying ESD protected combinational circuits.
Therefore, when the model circuit is extracted from the ESD protection combined circuit, a MOS transistor circuit and a specific device circuit can be extracted from the model circuit, wherein the specific device includes a resistor (R), a capacitor (C), a diode (D), or the like. It will be appreciated that multiple types of the same model circuit, but with different connection characteristics, may be extracted from a given combinatorial circuit. For example, there may be a plurality of not identical MOS transistor circuits, also MOS transistor circuits.
In one embodiment, the step of extracting the MOS transistor circuit from the specified combinational circuit includes: and extracting a first combined circuit which is only composed of MOS transistors and has a unique circuit structure from the appointed combined circuit, and recording the occurrence times of the first combined circuit in the appointed combined circuit, wherein the first combined circuit is the extracted MOS transistor circuit.
The first combined circuit should include as many MOS transistors as possible, but the first combined circuit cannot include two or more identical structures inside, that is, the circuit structures in the first combined circuit are not repeated and have uniqueness, for example, for the circuit shown in fig. 3, since this circuit can be split into two groups of circuits with the same internal structure and the same external connection characteristics, half of the structures form the required model circuit.
In one embodiment, the step of extracting the designated device circuit from the designated combinational circuit comprises: the method comprises the steps of extracting a second combined circuit which is only formed by interconnection (series connection, parallel connection or series-parallel connection) of specified devices and has a unique circuit structure from the specified combined circuit, abstracting the second combined circuit into the specified devices, taking the external connection characteristics of the second combined circuit as the connection characteristics of the specified devices to obtain the specified device circuit, recording the cascade series number of the specified device circuit, and recording the occurrence frequency of the specified device circuit in the specified combined circuit, wherein the cascade series number of the specified device circuit is consistent with the cascade series number of the specified devices in the second combined circuit. The principles of extracting the resistance model circuit, the capacitance model circuit, and the diode model circuit from the specified combinational circuit are consistent.
It will be appreciated that two devices in series cannot be considered a series configuration if the wiring between the two devices is connected to other types of devices and/or to a cell pin.
For ease of understanding, the circuit shown IN fig. 4 is taken as an example, although D1 and D2 are connected IN series, D1 and D2 cannot be regarded as a series structure because the connection between these two devices is connected to the cell pin IN and the resistor. Similarly, D4 and D5 cannot be considered as a series configuration. IN addition, the 4 diodes (diode) shown by the dashed line IN fig. 4 cannot be regarded as a single Model, and for the two diodes connected IN series on the left side, the negative electrode is connected to IN, and the positive electrode is grounded, which is generally regarded as a primary protection circuit according to the typical recognition of the integrated circuit industry, and is called HBM (Human Body Model) pull-down diode. For two diodes connected IN series on the right side, the cathode is connected to IN through a resistor, and is connected with the gate terminal of the MOS transistor, and the anode is grounded, so the diode is generally regarded as a secondary protection circuit IN the industry, and is known as a CDM (Charged Device Model) pull-down diode. Thus, the 4 diodes shown in the dashed box of fig. 4 should be divided into two model circuits according to typical knowledge in the integrated circuit industry.
For ease of understanding, the specific combinational circuit shown in fig. 5 is taken as an example. The specific combination circuit shown in fig. 5 is a self-defined ESD protection circuit. From the designated combination circuit, 5 kinds of model circuits, which are respectively a first C circuit, a second C circuit, a first MOS transistor circuit, a second MOS transistor circuit, and an R circuit obtained from the second combination circuit, may be extracted, and the number of each kind of model circuit is one. The first MOS transistor circuit and the second MOS transistor circuit are not considered to be the same model circuit because the connection characteristic of the gate terminal of P1 and the connection characteristic of the gate terminal of P3 are different.
2 kinds of C circuits (i.e., a first C circuit and a second C circuit) can be extracted therefrom. Although C1 and C2 are connected in series, C1 and C2 cannot be considered as a series configuration because of the connection between these two devices to cell pin a. Therefore, when extracting the model circuit, it should be considered as 2 independent C circuits.
For the second combined circuit in fig. 5, it may be equivalent to a resistor, one end of the circuit is connected to the power supply VDD, and the other end of the resistor is connected to the capacitor C1, the input end of the inverter (P1 and N1 constitute an inverter), and the drain end of the feedback PMOS transistor (i.e., P0). The cascade stage number of the second combined circuit is 2.
When the model circuit is extracted, the devices with the same device type are divided into a group, and then a single device with clear and unique connection characteristics is found in the group, or the external connection characteristics of the combined devices are clear and unique, so that the combined devices can be regarded as the model circuit.
In one embodiment, when the model circuit includes a MOS transistor circuit, the process of searching whether a preset model circuit exists in the circuit to be identified includes: extracting the device type and the connection characteristic of a key device in the MOS transistor circuit, searching for a target device (which can be a plurality of devices) matched with the device type and the connection characteristic of the key device in the circuit to be recognized, and checking whether the connection condition of the periphery of the target device is matched with the model circuit or not by taking each target device as a base point, wherein if the connection condition of the periphery of the target device is matched with the model circuit, the MOS transistor circuit exists in the circuit to be recognized.
The critical device may be a device with the least connection features among all devices included in the MOS transistor circuit. Optionally, the connection feature of the critical device needs to be unique, and in an alternative embodiment, the connection feature of the critical device is unique and is less compared with the connection features of other devices, that is, the principle of screening the critical device is: the connection features of the device are unique, or closest to unique, and the simpler the connection features the better.
For the convenience of understanding, it is assumed that the circuit to be identified is the designated combination circuit shown in fig. 5, that is, the circuit to be identified and the designated combination circuit for extracting the model circuit are the same circuit, and in practical applications, the circuit to be identified and the designated combination circuit may not be the same circuit.
The description is made in conjunction with the second MOS transistor circuit shown in fig. 5 described above. Firstly, the device type and the connection characteristics of a key device are extracted from a second MOS transistor circuit, according to the principle of screening the key device, N2 can be determined to be the key device in the second MOS transistor circuit, the type of the key device is an NMOS tube, the drain electrode of the NMOS tube is connected with a power supply VDD, the source electrode of the NMOS tube is grounded VSS, and the grid electrode of the NMOS tube is connected with the output end of an inverter (P3 and N3 form an inverter) and the grid electrode of a feedback PMOS tube (P2). And searching a target device matched with the device type and the connection characteristic of the key device in the circuit to be identified, and if the matched target device is searched, searching whether the connection condition around the target device is matched with the model circuit by taking the target device as a base point, namely, judging whether the connection characteristic of a feedback PMOS (P-channel metal oxide semiconductor) tube connected with the target device and the connection characteristic of the phase inverter are matched with the corresponding connection characteristic in the model circuit.
Similarly, for the first MOS transistor circuit, the process of searching whether the preset model circuit (first MOS transistor circuit) exists in the circuit to be identified is consistent with the principle of searching whether the preset second MOS transistor circuit exists.
If the model circuit comprises a specified device circuit, the process of searching whether the preset model circuit exists in the circuit to be identified comprises the following steps: the external connection characteristics of the circuit of the specified device are extracted, whether a target circuit (a plurality of target circuits) matched with the connection characteristics of the circuit of the specified device exists in the circuit to be identified is searched, and if the target circuit exists, a model circuit (the circuit of the specified device) exists in the circuit to be identified is represented.
For ease of understanding, the description is made in conjunction with the second combinatorial circuit shown in fig. 5 described above. The model circuit corresponding to the second combination circuit is a resistor (which is counted as a resistor R0), one end of the resistor R0 is connected with a power supply VDD, and the other end of the resistor R0 is connected with a capacitor C1, an input end (P1 and N1 of the inverter form the inverter) and a drain end of a feedback PMOS (P0). When searching whether a target circuit matched with the connection characteristics of the circuit of the specified device exists in the circuit to be identified, firstly, a target resistor with one end connection characteristics (such as power connection) identical to those of one end of the resistor R0 (such as power connection) is found, if the target resistor can be found, the target resistor is a first-stage resistor, and in combination with fig. 5, the target resistor is R1 or R2, then, whether the connection characteristics of the other end of the first-stage resistor are identical to those of the other end of the resistor R0 (the other end of the first-stage resistor is connected with the capacitor, the input end of the inverter and the drain end of the feedback PMOS tube) is checked, and if the connection characteristics of the other end of the first-stage resistor and the connection characteristics of the other end of the resistor R0 are identical, the method is finished. Otherwise, whether the other end of the first-stage resistor is connected to the same device (in this case, the second-stage resistor is R3 in fig. 5) is continuously checked, if the connection characteristic of the other end of the second-stage resistor is found, whether the connection characteristic of the other end of the second-stage resistor is the same as the connection characteristic of the other end of the resistor R0 is continuously checked, and if the connection characteristics of the other end of the second-stage resistor and the connection characteristic of the other end of the resistor R0 are the same, the process is ended. Otherwise, whether the other end of the second-stage resistor is connected with the same device or not is continuously checked (at this time, the third-stage resistor is found, if the third-stage resistor can be found, whether the connection characteristic of the other end of the third-stage resistor is the same as that of the other end of the resistor R0 is continuously checked, and the process is repeated until the resistor which meets the connection characteristic is found, or the connection characteristic of the last-stage resistor at one end is different from that of the other end of the resistor R0, and the other end of the last-stage resistor is not connected with the same device.
S3: determining that the circuit to be identified includes the designated combinational circuit.
If all the model circuits exist in the circuit to be identified, the circuit to be identified can be determined to contain the specified combined circuit. That is, each model circuit in the designated combinational circuit can be matched with the circuit to be identified, it indicates that the circuit to be identified includes the designated combinational circuit.
In one embodiment, considering that the same model circuit may appear in the designated combination circuit multiple times, after determining that all the model circuits exist in the circuit to be identified, before determining that the circuit to be identified includes the designated combination circuit, the circuit identification method further includes: the success times of matching the model circuit (such as the model circuit A) are recorded, namely, the times of searching the model circuit in the circuit to be identified are recorded, and the success times are determined to be not less than the times of the model circuit appearing in the specified combined circuit. Taking the model circuit as an MOS transistor circuit as an example, the number of successful times of matching the MOS transistor circuit is recorded, and the number of successful times is determined to be not less than the number of times that the MOS transistor circuit appears in the designated combinational circuit.
In this embodiment, even if all the model circuits exist in the circuit to be identified, it is necessary to ensure that the number of times of success of matching of each model circuit is not less than the number of times that the model circuit appears in the specified combinational circuit. Taking the model circuit shown in fig. 5 as an example, assuming that the circuit to be identified is the circuit itself shown in fig. 5, each model circuit can be matched in the circuit to be identified, at this time, the number of times each circuit is successfully matched needs to be observed, and if the number of times meets the requirement, the circuit to be identified is determined
The identification circuit includes a designated combining circuit. For another example, for FIG. 3, which contains 2 identical structures, 5, in matching, if the number of times of success of matching the model circuit is 1, it is smaller than the number of times of success of the model circuit in the designated combination
The number of times that the way appears (in this case 2) is not considered that the circuit to be identified contains the designated combinational circuit.
In one embodiment, when extracting a model circuit, a second combinatorial circuit, which is composed of only specified device interconnections and has a circuit structure with uniqueness, can be abstracted as a specified device, and thus, the model circuit can be used for extracting a model circuit
In the case of a specified device circuit, after determining that the specified device circuit exists in the circuit to be identified, before determining 0 that the circuit to be identified includes a specified combinational circuit, the circuit identification method further includes: obtaining a target
And determining the cascade stage number of the designated device in the target circuit to be not less than the cascade frequency of the designated device circuit. Taking the model circuit shown in fig. 5 as an example, taking the resistance model circuit corresponding to the second combinational circuit as an example, the cascade stage number of the internal circuit of the model circuit is 2, if
And if the cascade stage number of the specified devices in the target circuit is not more than 2, the circuit to be identified is not considered to comprise the specified 5 combined circuit.
By adopting the circuit identification method disclosed by the application, whether the circuit to be identified comprises the appointed combined circuit or not can be quickly identified.
Based on the same inventive concept, the embodiment of the present application further provides a circuit identification device 100,
as shown in fig. 6, the circuit identifying apparatus 100 includes: an acquisition module 110 and a processing module 120.
And a 0 obtaining module 110, configured to obtain a circuit to be identified.
The processing module 120 is configured to find whether a preset model circuit exists in the circuit to be identified, where the model circuit is extracted from a designated combinational circuit in advance; and if all the model circuits exist in the circuit to be identified, determining that the circuit to be identified comprises the specified combined circuit.
In one embodiment, the model circuit includes a MOS transistor circuit; the processing module 120,5 is used for extracting the device type and the connection characteristics of the key device in the MOS transistor circuit; finding
The target device is matched with the device type and the connection characteristics of the key device in the circuit to be identified; checking whether the connection condition of the periphery of the target device is matched with the model circuit or not by taking the target device as a base point; and if the connection condition of the periphery of the target device is matched with the model circuit, representing that the model circuit exists in the circuit to be identified.
Optionally, the processing module 120 is further configured to record the number of successful times of matching the model circuit before determining that the circuit to be identified includes the specified combinational circuit; determining that the number of successes is not less than the number of occurrences of the model circuit in the designated combinational circuit.
The model circuit is an MOS transistor circuit, and the specified device comprises a resistor, a capacitor or a diode; a processing module 120, configured to extract connection features outside the designated device circuit pair; searching whether a target circuit matched with the connection characteristics of the specified device circuit exists in the circuit to be identified; and if the target circuit exists, representing that the model circuit exists in the circuit to be identified.
Optionally, the processing module 120 is further configured to obtain a cascade order of the designated device in the target circuit before determining that the circuit to be identified includes the designated combinational circuit; and determining that the cascade number of the specified device in the target circuit is not less than the cascade number of the specified device circuit.
Optionally, the processing module 120 is further configured to, before searching whether a preset model circuit exists in the circuit to be identified, extract a first combination circuit, which is only composed of MOS transistors and has a unique circuit structure, from the specified combination circuit to obtain the MOS transistor circuit, and record the occurrence number of the MOS transistor circuit in the specified combination circuit.
Optionally, the processing module 120 is further configured to extract a second combined circuit, which is formed by only interconnection of the specified devices and has a unique circuit structure, from the specified combined circuit before searching whether a preset model circuit exists in the circuit to be identified; abstracting the second combined circuit into the designated device, taking the external connection feature of the second combined circuit as the connection feature of the designated device to obtain the designated device circuit, and recording the cascade stage number of the designated device circuit, wherein the cascade stage number of the designated device circuit is consistent with the cascade stage number of the designated device in the second combined circuit.
The circuit identification apparatus 100 according to the embodiment of the present application has the same implementation principle and the same technical effect as the foregoing method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the foregoing method embodiments for the parts of the apparatus embodiments that are not mentioned.
As shown in fig. 7, fig. 7 is a block diagram illustrating a structure of an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.
The elements of the transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. The transceiver 210 is used for transceiving data. The memory 220 is used for storing a computer program, such as a software functional module shown in fig. 6, that is, the circuit identifying apparatus 100. The circuit identification apparatus 100 includes at least one software functional module, which may be stored in the memory 220 in the form of software or Firmware (Firmware) or solidified in an Operating System (OS) of the electronic device 200. The processor 240 is configured to execute an executable module stored in the memory 220, such as a software functional module or a computer program included in the circuit identifying apparatus 100. For example, a processor 240 for obtaining a circuit to be identified; searching whether a preset model circuit exists in the circuit to be identified, wherein the model circuit is extracted from a specified combined circuit in advance; and if all the model circuits exist in the circuit to be identified, determining that the circuit to be identified comprises the specified combined circuit.
The Memory 220 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Read Only Memory (EPROM), an electrically Erasable Read Only Memory (EEPROM), and the like.
The processor 240 may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor 240 may be any conventional processor or the like.
The electronic device 200 includes, but is not limited to, a tablet, a computer, a server, and the like.
The present embodiment also provides a non-volatile computer-readable storage medium (hereinafter, referred to as a storage medium), where the storage medium stores a computer program, and when the computer program is executed by the electronic device 200 as described above, the computer program performs the circuit identification method described above.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product stored in a computer-readable storage medium, which includes several instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned computer-readable storage media comprise: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (15)
1. A circuit identification method, comprising:
acquiring a circuit to be identified;
searching whether a preset model circuit exists in the circuit to be identified, wherein the 5 model circuits are extracted from a specified combined circuit in advance;
and if all the model circuits exist in the circuit to be identified, determining that the circuit to be identified comprises the specified combined circuit.
2. The method of claim 1, wherein the model circuit comprises a MOS transistor circuit; whether a preset model circuit exists in the circuit to be identified or not is searched, and the method comprises the following steps: 0 extracting the device type and the connection characteristics of key devices in the MOS transistor circuit;
searching a target device matched with the device type and the connection characteristics of the key device in the circuit to be identified;
checking whether the connection condition of the periphery of the target device is matched with the model circuit or not by taking the target device as a base point;
and 5, if the connection condition of the periphery of the target device is matched with the model circuit, representing that the model circuit exists in the circuit to be identified.
3. The method of claim 2, wherein prior to determining that the circuit to be identified includes the designated combinational circuit, the method further comprises:
recording the success times of matching the model circuit;
0 determines that the number of successes is not less than the number of occurrences of the model circuit in the designated combinational circuit.
4. The method of claim 2, wherein the critical device is a device with the least connection feature of all devices included in the MOS transistor circuit.
5. The method according to any of claims 1-4, wherein the model circuit 5 is a MOS transistor circuit, and the step of extracting the MOS transistor circuit from the specified combinational circuit comprises:
and extracting a first combined circuit which is only composed of MOS transistors and has a unique circuit structure from the specified combined circuit to obtain the MOS transistor circuit, and recording the occurrence frequency of the MOS transistor circuit in the specified combined circuit.
6. The method of claim 1, wherein the model circuit comprises a designated device circuit, the designated device comprising a resistor, a capacitor, or a diode; whether a preset model circuit exists in the circuit to be identified or not is searched, and the method comprises the following steps:
extracting the connection characteristics of the circuit pair of the specified device;
searching whether a target circuit matched with the connection characteristics of the specified device circuit exists in the circuit to be identified;
and if the target circuit exists, representing that the model circuit exists in the circuit to be identified.
7. The method of claim 6, wherein prior to determining that the circuit to be identified includes the designated combinational circuit, the method further comprises:
acquiring the cascade stage number of the designated device in the target circuit;
and determining that the cascade number of the specified device in the target circuit is not less than the cascade number of the specified device circuit.
8. The method of claim 6 or 7, wherein the step of extracting the designated device circuit from the designated combinational circuit comprises:
a second combined circuit which is extracted from the appointed combined circuit, is only formed by interconnection of the appointed devices and has a unique circuit structure;
abstracting the second combined circuit into the designated device, taking the external connection feature of the second combined circuit as the connection feature of the designated device to obtain the designated device circuit, and recording the cascade stage number of the designated device circuit, wherein the cascade stage number of the designated device circuit is consistent with the cascade stage number of the designated device in the second combined circuit.
9. A circuit identification device, comprising:
the acquisition module is used for acquiring a circuit to be identified;
the processing module is used for searching whether a preset model circuit exists in the circuit to be identified, wherein the model circuit is extracted from a specified combined circuit in advance; and if all the model circuits exist in the circuit to be identified, determining that the circuit to be identified comprises the specified combined circuit.
10. The circuit identifying device of claim 9, wherein the model circuit comprises a MOS transistor circuit; the processing module is configured to:
extracting the device type and the connection characteristics of key devices in the MOS transistor circuit; searching a target device matched with the device type and the connection characteristics of the key device in the circuit to be identified; checking whether the connection condition of the periphery of the target device is matched with the model circuit or not by taking the target device as a base point; and if the connection condition of the periphery of the target device is matched with the model circuit, representing that the model circuit exists in the circuit to be identified.
11. The circuit identification device of claim 9, wherein the model circuit comprises a designated device circuit, the designated device comprising a resistor, a capacitor, or a diode; the processing module is configured to:
extracting the external connection characteristics of the specified device circuit pair; searching whether a target circuit matched with the connection characteristics of the specified device circuit exists in the circuit to be identified; and if the target circuit exists, representing that the model circuit exists in the circuit to be identified.
12. The circuit identification device according to claim 9, wherein the processing module is further configured to extract a first combination circuit, which is composed of only MOS transistors and has a unique circuit structure, from the designated combination circuit, obtain the MOS transistor circuit, and record the number of occurrences of the MOS transistor circuit in the designated combination circuit.
13. The circuit identification device of claim 9, wherein the processing module is further configured to extract from the designated combinational circuit a second combinational circuit having a circuit structure unique and composed only of the designated device interconnections; abstracting the second combined circuit into the designated device, taking the external connection feature of the second combined circuit as the connection feature of the designated device to obtain the designated device circuit, and recording the cascade stage number of the designated device circuit, wherein the cascade stage number of the designated device circuit is consistent with the cascade stage number of the designated device in the second combined circuit.
14. An electronic device, comprising:
a memory and a processor, the processor coupled to the memory;
the memory is used for storing programs;
the processor to invoke a program stored in the memory to perform the method of any of claims 1-8.
15. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-8.
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050216873A1 (en) * | 2004-03-23 | 2005-09-29 | Raminderpal Singh | Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction |
CN102054110A (en) * | 2011-01-27 | 2011-05-11 | 复旦大学 | General packing method for FPGA (field programmable gate array) configurable logical block (CLB) |
CN105092994A (en) * | 2014-04-30 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | ESD detection method and device and ESD debugging method and device |
CN106682331A (en) * | 2016-12-30 | 2017-05-17 | 北京厚德微电技术有限公司 | Extraction of static protection structure of integrated circuit layout and intelligent design verifying method |
CN110187260A (en) * | 2019-06-11 | 2019-08-30 | 珠海市一微半导体有限公司 | A kind of automatic testing method based on ESD circuit integrality |
CN112036113A (en) * | 2020-08-06 | 2020-12-04 | 互升科技(深圳)有限公司 | ESD protection method and system |
CN112528845A (en) * | 2020-12-11 | 2021-03-19 | 华中师范大学 | Physical circuit diagram identification method based on deep learning and application thereof |
CN115408984A (en) * | 2022-09-01 | 2022-11-29 | 长鑫存储技术有限公司 | Verification method and device of circuit layout structure, storage medium and equipment |
-
2022
- 2022-12-19 CN CN202211635248.6A patent/CN115935890B/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050216873A1 (en) * | 2004-03-23 | 2005-09-29 | Raminderpal Singh | Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction |
CN102054110A (en) * | 2011-01-27 | 2011-05-11 | 复旦大学 | General packing method for FPGA (field programmable gate array) configurable logical block (CLB) |
CN105092994A (en) * | 2014-04-30 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | ESD detection method and device and ESD debugging method and device |
CN106682331A (en) * | 2016-12-30 | 2017-05-17 | 北京厚德微电技术有限公司 | Extraction of static protection structure of integrated circuit layout and intelligent design verifying method |
CN110187260A (en) * | 2019-06-11 | 2019-08-30 | 珠海市一微半导体有限公司 | A kind of automatic testing method based on ESD circuit integrality |
CN112036113A (en) * | 2020-08-06 | 2020-12-04 | 互升科技(深圳)有限公司 | ESD protection method and system |
CN112528845A (en) * | 2020-12-11 | 2021-03-19 | 华中师范大学 | Physical circuit diagram identification method based on deep learning and application thereof |
CN115408984A (en) * | 2022-09-01 | 2022-11-29 | 长鑫存储技术有限公司 | Verification method and device of circuit layout structure, storage medium and equipment |
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