CN115934441A - PSRAM timing calibration system, method, electronic device and storage medium - Google Patents
PSRAM timing calibration system, method, electronic device and storage medium Download PDFInfo
- Publication number
- CN115934441A CN115934441A CN202211613787.XA CN202211613787A CN115934441A CN 115934441 A CN115934441 A CN 115934441A CN 202211613787 A CN202211613787 A CN 202211613787A CN 115934441 A CN115934441 A CN 115934441A
- Authority
- CN
- China
- Prior art keywords
- psram
- calibration
- time sequence
- module
- eye width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a PSRAM (programmable system random access memory) timing sequence calibration system, a method, electronic equipment and a storage medium, wherein the PSRAM timing sequence calibration system comprises a PSRAM timing sequence calibration operation module, a PSRAM control module, a PSRAM storage entity, a PSRAM timing sequence calibration module and an EFUSE storage control entity; the PSRAM time sequence calibration operation module is used for carrying out PSRAM time sequence calibration operation; the PSRAM control module is used for completing the access and storage of application programs or various data in a PSRAM storage entity; the PSRAM storage entity is used for storing various application programs or data; the PSRAM time sequence calibration module is used for writing a specific test data set into a PSRAM storage entity, reading the test data set out for verification, detecting the eye width of the current PSRAM communication time sequence and judging whether the current eye width can meet the requirement of stable communication of the PSRAM; the EFUSE storage control entity is used for storing the calibration result of the PSRAM communication time sequence and providing a read-write protection mechanism of the calibration result. The invention can improve the compatibility, reliability and stability of the chip.
Description
Technical Field
The invention belongs to the technical field of time sequence calibration, relates to time sequence calibration, and particularly relates to a PSRAM time sequence calibration system, a PSRAM time sequence calibration method, electronic equipment and a storage medium.
Background
A PSRAM (pseudo random access memory) is a static random access memory that consists of a DRAM body in combination with various on-chip refresh and control circuits, and has operating characteristics very similar to those of an SRAM. Because the SRAM space in the chip is limited, the PSRAM can be used as the RAM space available for the chip after being enabled by using the PSRAMC controller peripheral in the chip, and the PSRAM has small package, low cost and large capacity, so that the memory space available for the chip can be expanded in a large scale at lower cost, the data throughput of the chip is greatly improved, and the performance of the chip is fully exerted.
Therefore, the PSRAM and the PSRAMcontroller play an important role in a chip, the PSRAMcontroller is an important component of a chip peripheral, timing compatibility of PSRAMs of different manufacturers and capacities needs to be considered during chip design, and the PSRAM and the PSRAMcontroller cannot be modified after chip production. If the PSRAMcontroller cannot meet the requirements due to design defects, process defects or the influence of temperature change and IO driving capability when communicating with the PSRAM, the correctness of data reading and writing in the PSRAM is affected, and finally, the accessed data is abnormal, and the application program cannot run normally. The chip cost and the labor cost can be greatly increased by checking and confirming related problems, the application scene can not be covered, the client is lost, the time for the mass production and the marketing of the chip can be delayed, and the great loss can be caused to a chip design company.
In view of the above, there is an urgent need to design a new PSRAM to overcome at least some of the above-mentioned disadvantages of the existing PSRAM.
Disclosure of Invention
The invention provides a PSRAM timing calibration system, a method, an electronic device and a storage medium, which can improve the compatibility, reliability and stability of a PSRAM controller and a PSRAM of a chip, thereby helping the chip to smoothly enter a function development and mass production promotion stage, effectively reducing the chip cost and improving the factory yield of the chip.
In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:
a PSRAM timing calibration system, the PSRAM timing calibration system comprising:
the PSRAM time sequence calibration operation module is used for carrying out PSRAM time sequence calibration operation;
the PSRAM control module is used for completing the access of application programs or various data in a PSRAM storage entity according to the access request;
the PSRAM storage entity is used for storing various application programs or data;
the PSRAM time sequence calibration module is used for writing a specific test data set into a PSRAM storage entity, reading the test data set out for verification, detecting the eye width of the current PSRAM communication time sequence and judging whether the current eye width can meet the requirement of stable communication of the PSRAM;
the storage control entity is used for storing the calibration result of the PSRAM communication time sequence and providing a read-write protection mechanism of the calibration result; when the system is started, the PSRAM timing calibration module can be used for judging whether calibration needs to be carried out again.
As an embodiment of the present invention, the PSRAM timing calibration system further includes a temperature detection module, configured to perform temperature compensation correction on the PSRAM communication timing under different temperature conditions; the calibration results are correlated with temperature to ensure stability of the system over a wide temperature range.
As an embodiment of the present invention, the storage control entity further stores a calibration parameter related to temperature, so that the system can dynamically adjust the calibration parameter according to the corresponding temperature, thereby ensuring the stability of the system operation.
As an embodiment of the present invention, the PSRAM timing calibration operation module is a CPU, and the PSRAM timing calibration system includes one or more CPUs; the PSRAM storage entity is a DRAM; the temperature detection module is a temperature detection sensor inside the chip.
As an embodiment of the present invention, the storage control entity is a power-down nonvolatile storage unit.
According to another aspect of the invention, the following technical scheme is adopted: a PSRAM timing calibration method, comprising:
checking whether a PSRAM communication time sequence calibration result exists in the storage control entity, namely checking whether eye width information exists; if the communication time sequence exists, the communication time sequence is adjusted to be optimal by directly using the calibration result stored in the current storage control entity, and the communication time sequence is configured to be used in a PSRAM control module; if the corresponding communication time sequence calibration result does not exist, namely correct eye width information exists, a PSRAM time sequence calibration module is normally started to carry out calibration;
the PSRAM time sequence calibration module writes a specific test data set into a PSRAM storage entity, reads the test data set out and verifies the test data set so as to detect the eye width of the current PSRAM communication time sequence and judge whether the current eye width can meet the requirement of stable communication of the PSRAM.
As an embodiment of the present invention, the PSRAM timing calibration method specifically includes:
after the system is powered on and operated, checking whether a PSRAM communication time sequence calibration result exists in an EFUSE storage control entity, namely checking whether eye width information exists; if the current EFUSE time sequence exists, directly using the calibration result stored in the current EFUSE storage control entity to adjust the communication time sequence to be optimal, and configuring the communication time sequence to a PSRAM control module for use; if no corresponding calibration result exists, namely correct eye width information exists, normally starting a PSRAM time sequence calibration module to carry out calibration;
configuring a PSRAM control module by using the minimum gear, and reading and writing an ID related register of the PSRAM; if the PSRAMID information is correct, continuously writing in a specific test data set; after the writing is finished, reading out the data to check; if the verification is correct, recording the current eye width information, if the verification is incorrect, continuously adjusting the time sequence configuration gear to the next gear, and testing again;
repeating the steps for multiple times to finally obtain eye width information; judging whether the eye width information meets the minimum communication requirement again, if the calibrated result meets the minimum communication requirement of the communication time sequence, writing the calibrated result into the EFUSE, and simultaneously recording the current temperature parameter so as to accelerate the next system starting speed; and adjusts the communication timing to be optimal for subsequent normal use based on the current eye width information.
As an embodiment of the present invention, the storage control entity is a power-down nonvolatile storage unit.
According to another aspect of the invention, the following technical scheme is adopted: an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method when executing the computer program.
According to another aspect of the invention, the following technical scheme is adopted: a storage medium having stored thereon computer program instructions which, when executed by a processor, implement the steps of the above-described method.
The invention has the beneficial effects that: the PSRAM time sequence calibration system, the PSRAMcontroller and the PSRAM of the chip can improve the compatibility, reliability and stability of the PSRAMcontroller and the PSRAM, so that the chip can smoothly enter the stages of function development and mass production popularization, the chip cost is effectively reduced, and the factory yield of the chip is improved.
Drawings
Fig. 1 is a schematic diagram illustrating a PSRAM timing calibration system according to an embodiment of the invention.
FIG. 2 is a flowchart illustrating a PSRAM timing calibration method according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of an electronic device according to an embodiment of the invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only and the invention is not to be limited in scope by the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.
The steps in the embodiments in the specification are only expressed for convenience of description, and the implementation manner of the present application is not limited by the order of implementation of the steps.
"coupled" in this specification includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; and may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are well known to those skilled in the art for performing the same or similar functional purposes. In the specification, "a plurality" means two or more.
The invention discloses a PSRAM timing calibration system, and FIG. 1 is a schematic diagram of the PSRAM timing calibration system according to an embodiment of the invention; referring to fig. 1, the PSRAM timing calibration system includes: the PSRAM timing calibration system comprises a PSRAM timing calibration operation module 1, a PSRAM control module 2, a PSRAM storage entity 3, a PSRAM timing calibration module 4 and an EFUSE storage control entity 5.
The PSRAM time sequence calibration operation module 1 is used for carrying out PSRAM time sequence calibration operation. In an embodiment of the present invention, the PSRAM timing calibration operation module is a CPU, and the PSRAM timing calibration system may include one or more CPUs.
The PSRAM control module 2 is used for completing the access of application programs or various data in a PSRAM storage entity according to an access request;
the PSRAM storage entity 3 is used for storing various application programs or data; the PSRAM storage entity may be a DRAM.
The PSRAM timing calibration module 4 is configured to write a specific test data set into a PSRAM storage entity, read the test data set out for verification, detect an eye width of a current PSRAM communication timing, and determine whether the current eye width can meet a PSRAM stable communication requirement (e.g., a minimum requirement may be set);
the EFUSE storage control entity 5 is used for storing a calibration result of a PSRAM communication time sequence, providing a read-write protection mechanism of the calibration result and ensuring the reliability and the safety of the calibration result; when the system is started, the PSRAM timing calibration module can be used for judging whether the calibration needs to be carried out again.
Of course, the storage control entity included in the PSRAM timing calibration system of the present invention may also be other types of storage units other than the EFUSE storage control entity, such as a flash; but is preferably a power-down nonvolatile memory cell. Meanwhile, in order to ensure the safety, the memory unit which only can be written once, such as EFUSE, is better in effect, and the flash can be modified, but the technical purpose of the invention can also be basically realized.
In an embodiment of the present invention, the PSRAM timing calibration system further includes a temperature detection module 6, where the temperature detection module 6 is configured to perform temperature compensation correction on the PSRAM communication timing under different temperature conditions; the calibration results are correlated with temperature to ensure stability of the system over a wide temperature range. The temperature detection module may be a temperature detection sensor inside the chip.
In an embodiment of the present invention, the EFUSE storage control entity 5 may further store a calibration parameter related to a temperature, so that the system dynamically adjusts the calibration parameter according to the corresponding temperature, so as to ensure the stability of the system operation.
The invention also discloses a PSRAM time sequence calibration method, which comprises the following steps:
checking whether the EFUSE storage control entity has a PSRAM communication time sequence calibration result, namely checking whether eye width information exists; if the current EFUSE time sequence exists, directly using the calibration result stored in the current EFUSE storage control entity to adjust the communication time sequence to be optimal, and configuring the communication time sequence to a PSRAM control module for use; if no corresponding communication time sequence calibration result exists, namely correct eye width information exists, normally starting a PSRAM time sequence calibration module for calibration;
the PSRAM time sequence calibration module writes a specific test data set into a PSRAM storage entity, reads the test data set out and verifies the test data set so as to detect the eye width of the current PSRAM communication time sequence and judge whether the current eye width can meet the requirements (such as the minimum requirement) of PSRAM stable communication.
FIG. 2 is a flowchart illustrating a PSRAM timing calibration method according to an embodiment of the present invention; referring to fig. 2, in an embodiment of the present invention, the PSRAM timing calibration method specifically includes:
after the system is powered on and operated, checking whether a PSRAM communication time sequence calibration result exists in an EFUSE storage control entity, namely checking whether eye width information exists; if the communication time sequence exists, the calibration result stored in the current EFUSE storage control entity is directly used, the communication time sequence is adjusted to be optimal, and the communication time sequence is configured to be used in a PSRAM control module; if no corresponding calibration result exists, namely correct eye width information exists, normally starting a PSRAM time sequence calibration module to carry out calibration;
configuring a PSRAM control module by using the minimum gear, and reading and writing an ID related register of the PSRAM; if the PSRAMID information is correct, continuously writing in a specific test data set; after the writing is finished, reading out the data to check; if the verification is correct, recording the current eye width information, if the verification is incorrect, continuously adjusting the time sequence configuration gear to the next gear, and testing again;
repeating the steps for multiple times to finally obtain eye width information; judging whether the eye width information meets the minimum communication requirement again, if the calibrated result meets the minimum communication requirement of the communication time sequence, writing the calibrated result into the EFUSE, and simultaneously recording the current temperature parameter so as to accelerate the next system starting speed; and adjusts the communication timing to be optimal for subsequent normal use based on the current eye width information.
Fig. 3 is a schematic diagram illustrating an electronic device according to an embodiment of the present invention; referring to fig. 3, the electronic device includes a memory, a processor and at least one network interface at a hardware level; the processor may be a microprocessor, and the memory may include a memory, such as a Random Access Memory (RAM), a non-volatile memory (non-volatile memory), and the like. Of course, the electronic device may also be provided with other hardware as required.
The processor, the network interface and the memory may be connected to each other through an internal bus, which may be an ISA (industry standard architecture) bus, a PCI (peripheral component interconnect standard) bus, an EISA (extended industry standard architecture) bus, or the like; the bus may include an address bus, a data bus, a control bus, and the like. The memory is used for storing programs (which can comprise an operating system program and an application program); the program may include program code, which may include computer operating instructions. The memory may include both memory and non-volatile storage and provides instructions and data to the processor.
In one embodiment, the processor may read a corresponding program from the nonvolatile memory into the memory and then operate the program; the processor is capable of executing programs stored in the memory and is specifically configured to perform the following operations (as shown in fig. 2):
after the system is powered on and operated, checking whether a PSRAM communication time sequence calibration result exists in an EFUSE storage control entity, namely checking whether eye width information exists; if the communication time sequence exists, the calibration result stored in the current EFUSE storage control entity is directly used, the communication time sequence is adjusted to be optimal, and the communication time sequence is configured to be used in a PSRAM control module; if no corresponding calibration result exists, namely correct eye width information exists, normally starting a PSRAM time sequence calibration module to carry out calibration;
configuring a PSRAM control module by using the minimum gear, and reading and writing an ID related register of the PSRAM; if the PSRAMID information is correct, continuously writing in a specific test data set; after the writing is finished, reading out the data to check; if the verification is correct, recording the current eye width information, if the verification is incorrect, continuously adjusting the time sequence configuration gear to the next gear, and testing again;
repeating the steps for multiple times to finally obtain eye width information; judging whether the eye width information meets the minimum communication requirement again, if the calibrated result meets the minimum communication requirement of the communication time sequence, writing the calibrated result into the EFUSE, and simultaneously recording the current temperature parameter so as to accelerate the next system starting speed; and adjusts the communication timing to be optimal for subsequent normal use based on the current eye width information.
The invention further discloses a storage medium having stored thereon computer program instructions which, when executed by a processor, implement the following steps of the inventive method (as shown in fig. 2):
after the system is powered on and operated, checking whether a PSRAM communication time sequence calibration result exists in an EFUSE storage control entity, namely checking whether eye width information exists; if the communication time sequence exists, the calibration result stored in the current EFUSE storage control entity is directly used, the communication time sequence is adjusted to be optimal, and the communication time sequence is configured to be used in a PSRAM control module; if no corresponding calibration result exists, namely correct eye width information exists, normally starting a PSRAM time sequence calibration module to carry out calibration;
configuring a PSRAM control module by using the minimum gear, and reading and writing an ID related register of the PSRAM; if the PSRAMID information is correct, continuously writing in a specific test data set; after the writing is finished, reading out the data to check; if the verification is correct, recording the current eye width information, if the verification is incorrect, continuously adjusting the time sequence configuration gear to the next gear, and testing again;
repeating the steps for multiple times to finally obtain eye width information; judging whether the eye width information meets the minimum communication requirement again, if the calibrated result meets the minimum communication requirement of the communication time sequence, writing the calibrated result into the EFUSE, and simultaneously recording the current temperature parameter so as to accelerate the next system starting speed; and adjusts the communication timing to an optimum for subsequent normal use based on the current eye width information.
In summary, the PSRAM timing calibration system, method, electronic device and storage medium provided by the present invention can improve the compatibility, reliability and stability of the PSRAM and PSRAM of the chip, thereby helping the chip enter the stages of function development and mass production promotion smoothly, effectively reducing the chip cost and improving the yield of the chip when the chip leaves the factory.
It should be noted that the present application may be implemented in software and/or a combination of software and hardware; for example, it may be implemented using Application Specific Integrated Circuits (ASICs), general purpose computers, or any other similar hardware devices. In some embodiments, the software programs of the present application may be executed by a processor to implement the above steps or functions. As such, the software programs (including associated data structures) of the present application can be stored in a computer-readable recording medium; such as RAM memory, magnetic or optical drives or diskettes, and the like. In addition, some steps or functions of the present application may be implemented using hardware; for example, as circuitry that cooperates with the processor to perform various steps or functions.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those of ordinary skill in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.
Claims (10)
1. A PSRAM timing calibration system, comprising:
the PSRAM time sequence calibration operation module is used for carrying out PSRAM time sequence calibration operation;
the PSRAM control module is used for completing the access of application programs or various data in a PSRAM storage entity according to the access request;
the PSRAM storage entity is used for storing various application programs or data;
the PSRAM time sequence calibration module is used for writing a specific test data set into a PSRAM storage entity, reading the test data set out for verification, detecting the eye width of the current PSRAM communication time sequence and judging whether the current eye width can meet the requirement of stable communication of the PSRAM;
the storage control entity is used for storing the calibration result of the PSRAM communication time sequence and providing a read-write protection mechanism of the calibration result; when the system is started, the PSRAM timing calibration module can be used for judging whether calibration needs to be carried out again.
2. The PSRAM timing calibration system of claim 1, wherein:
the PSRAM timing calibration system further comprises a temperature detection module, wherein the temperature detection module is used for carrying out temperature compensation correction on the PSRAM communication timing under different temperature conditions; the calibration results are correlated with temperature to ensure stability of the system over a wide temperature range.
3. The PSRAM timing calibration system of claim 2, wherein:
the storage control entity also stores calibration parameters related to temperature, so that the system can dynamically adjust the calibration parameters according to the corresponding temperature, and the running stability of the system is ensured.
4. The PSRAM timing calibration system of claim 2, wherein:
the PSRAM time sequence calibration operation module is a CPU, and the PSRAM time sequence calibration system comprises one or more CPUs; the PSRAM storage entity is a DRAM; the temperature detection module is a temperature detection sensor inside the chip.
5. The PSRAM timing calibration system of claim 1, wherein:
the storage control entity is a power-down nonvolatile storage unit.
6. A PSRAM timing calibration method is characterized by comprising the following steps:
checking whether a PSRAM communication time sequence calibration result exists in the storage control entity, namely checking whether eye width information exists; if the communication time sequence exists, the communication time sequence is adjusted to be optimal by directly using the calibration result stored in the current storage control entity and is configured to be used in a PSRAM control module; if the corresponding communication time sequence calibration result does not exist, namely correct eye width information exists, a PSRAM time sequence calibration module is normally started to carry out calibration;
the PSRAM time sequence calibration module writes a specific test data set into a PSRAM storage entity, reads the test data set out and verifies the test data set so as to detect the eye width of the current PSRAM communication time sequence and judge whether the current eye width can meet the requirement
PSRAM stabilizes the communication requirements.
7. The PSRAM timing calibration method of claim 6, wherein:
the PSRAM time sequence calibration method specifically comprises the following steps:
after the system is powered on and operated, checking whether a PSRAM communication time sequence calibration result exists in an EFUSE storage control entity, namely checking whether eye width information exists; if the communication time sequence exists, the calibration result stored in the current EFUSE storage control entity is directly used, the communication time sequence is adjusted to be optimal, and the communication time sequence is configured to be used in a PSRAM control module; if no corresponding calibration result exists, namely correct eye width information exists, normally starting a PSRAM time sequence calibration module to carry out calibration;
configuring a PSRAM control module by using a minimum file, and reading and writing an ID related register of the PSRAM; if the PSRAMID information is correct, continuously writing in a specific test data set; after the writing is finished, reading out the data to check; if the verification is correct, recording the current eye width information, if the verification is incorrect, continuously adjusting the time sequence configuration gear to the next gear, and testing again;
repeating the steps for multiple times to finally obtain eye width information; judging whether the eye width information meets the minimum communication requirement again, if the calibrated result meets the minimum requirement of the communication time sequence, writing the calibrated result into the EFUSE, and simultaneously recording the current temperature parameter so as to accelerate the next system starting speed; and adjusts the communication timing to be optimal for subsequent normal use based on the current eye width information.
8. The PSRAM timing calibration method of claim 6, wherein:
the storage control entity is a power-down nonvolatile storage unit.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to any of claims 6 to 8 are implemented when the computer program is executed by the processor.
10. A storage medium having stored thereon computer program instructions, characterized in that the computer program instructions, when executed by a processor, implement the steps of the method of any of claims 6 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211613787.XA CN115934441A (en) | 2022-12-15 | 2022-12-15 | PSRAM timing calibration system, method, electronic device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211613787.XA CN115934441A (en) | 2022-12-15 | 2022-12-15 | PSRAM timing calibration system, method, electronic device and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115934441A true CN115934441A (en) | 2023-04-07 |
Family
ID=86550114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211613787.XA Pending CN115934441A (en) | 2022-12-15 | 2022-12-15 | PSRAM timing calibration system, method, electronic device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115934441A (en) |
-
2022
- 2022-12-15 CN CN202211613787.XA patent/CN115934441A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9870293B2 (en) | Memory device performing post package repair (PPR) operation | |
| CN101960532B (en) | Systems, methods, and apparatuses to save memory self-refresh power | |
| US10204698B2 (en) | Method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic | |
| US7937631B2 (en) | Method for self-test and self-repair in a multi-chip package environment | |
| US6336176B1 (en) | Memory configuration data protection | |
| US9336906B2 (en) | Semiconductor memory devices including redundancy memory cells | |
| CN112667445B (en) | Method and device for repairing packaged memory, storage medium and electronic equipment | |
| KR20030043658A (en) | Memory circuit having parity cell array | |
| US7487413B2 (en) | Memory module testing apparatus and method of testing memory modules | |
| US7719914B2 (en) | Semiconductor memory and test system | |
| US10957414B1 (en) | Method of test and repair of memory cells during power-up sequence of memory device | |
| CN113626264A (en) | Memory module, computing system and starting method of computing system | |
| CN111459557B (en) | Method and system for shortening starting time of server | |
| US7197675B2 (en) | Method and apparatus for determining the write delay time of a memory utilizing the north bridge chipset as in charge of the works for checking the write delay time of the memory | |
| CN115756984A (en) | Memory test method, device, equipment and storage medium | |
| JP4373615B2 (en) | Initial bad block marking method | |
| CN111627475B (en) | Memory, electronic device thereof, test system, test method and application method thereof | |
| US20170103797A1 (en) | Calibration method and device for dynamic random access memory | |
| CN115934441A (en) | PSRAM timing calibration system, method, electronic device and storage medium | |
| CN115015741A (en) | Chip testing method, device, equipment and medium | |
| KR20150006167A (en) | Semiconductor system and repair memthod of the same | |
| KR100909411B1 (en) | Semiconductor storage device | |
| TWI841987B (en) | Method for simulating circuit, test apparatus, electronic device and medium | |
| US11354255B2 (en) | Processing chip having different modes and corresponding chip system and operation method of the same | |
| EP4312219A2 (en) | Memory system, operating method of the same, and controller of memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |