CN115915770A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN115915770A CN115915770A CN202211731309.9A CN202211731309A CN115915770A CN 115915770 A CN115915770 A CN 115915770A CN 202211731309 A CN202211731309 A CN 202211731309A CN 115915770 A CN115915770 A CN 115915770A
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Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, at least one stack layer, a first metal layer, a second metal layer, a via structure, and a barrier layer. The stack layer is arranged on the substrate, and the first metal layer and the second metal layer are arranged on the substrate and are respectively positioned below and above the stack layer. The channel structure is disposed on the substrate, partially overlapping the second metal layer, the stack of layers, and a portion of the first metal layer. The barrier layer is arranged in the second metal layer, wherein the barrier layer is clamped between the second metal layer and the channel structure, and the maximum width in the horizontal direction is larger than that of the channel structure. Therefore, the barrier layer can effectively prevent the metal ions contained in the second metal layer from diffusing to pollute the channel structure. Therefore, the structure reliability and the performance of the semiconductor device can be improved.
Description
Technical Field
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device having a vertical channel structure and a method for fabricating the same.
Background
Planar semiconductor devices can be scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and fabrication methods. However, as the feature size of semiconductor devices gradually approaches the lower limit, the fabrication methods of the related devices become extremely challenging and costly. Nowadays, the development of planar semiconductor devices has reached a bottleneck, and in order to solve the above-mentioned density limit problem of planar semiconductor devices, semiconductor devices with three-dimensional structures have become the mainstream development trend at present, and semiconductor memory devices such as three-dimensional NAND and related manufacturing processes are continuously improved to maintain good device performance under the premise of simplified manufacturing process.
Disclosure of Invention
The present invention provides a semiconductor device, which additionally has a barrier layer between the channel structure and the metal layer to prevent the channel structure from directly contacting the metal layer. Therefore, the barrier layer can effectively prevent metal ions in the metal layer from diffusing to the channel structure and further polluting the channel structure. Therefore, the structure reliability and the performance of the semiconductor device can be improved.
The present invention provides a method for manufacturing a semiconductor device, which additionally provides a barrier layer between a via structure and a metal layer to prevent the via structure from directly contacting the metal layer. The barrier layer can effectively prevent metal ions in the metal layer from diffusing and polluting the channel structure. Therefore, the manufactured semiconductor device can have optimized structural reliability and performance.
The present invention provides a semiconductor device, which includes a substrate, at least one stack layer, a first metal layer, a second metal layer, a channel structure, and a barrier layer. The at least one stack layer is disposed on the substrate. The first metal layer and the second metal layer are disposed on the substrate below and above the at least one stack layer, respectively. The via structure is disposed on the substrate, partially overlapping the second metal layer, the at least one stack layer, and a portion of the first metal layer. The barrier layer is arranged in the second metal layer, wherein the barrier layer is clamped between the second metal layer and the channel structure, and the maximum width of the barrier layer in the horizontal direction is larger than that of the channel structure.
The invention aims to provide a manufacturing method of a semiconductor device, which comprises the following steps. Firstly, a substrate is provided, at least one stacking layer is formed on the substrate, and a first metal layer and a second metal layer are formed on the substrate, wherein the first metal layer and the second metal layer are respectively positioned below and above the at least one stacking layer. Then, a channel structure is formed on the substrate, partially overlapping the second metal layer, the at least one stack layer, and a portion of the first metal layer. Then, a barrier layer is formed on the substrate, the barrier layer is formed in the second metal layer, wherein the barrier layer is clamped between the second metal layer and the channel structure, and the maximum width of the barrier layer in the horizontal direction is larger than that of the channel structure.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These drawings and description are included to explain the principles of some embodiments. It should be noted that all the drawings are schematic drawings, and the relative sizes and proportions are adjusted for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.
Fig. 1 to 8 are schematic views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention, wherein:
FIG. 1 is a schematic cross-sectional view of a semiconductor device after formation of a via;
FIG. 2 is a schematic cross-sectional view of a semiconductor device after forming a barrier material layer;
FIG. 3 is a schematic cross-sectional view of a semiconductor device after a planarization process;
FIG. 4 is a schematic cross-sectional view of the semiconductor device after another via is formed;
FIG. 5 is a cross-sectional view of the semiconductor device after another barrier material layer is formed;
FIG. 6 is a schematic cross-sectional view of a semiconductor device after another planarization process;
FIG. 7 is a schematic cross-sectional view of a semiconductor device after forming a via hole; and
fig. 8 is a schematic cross-sectional view of a semiconductor device after forming a channel structure.
Fig. 9 is a schematic view illustrating a method of fabricating a semiconductor device according to a second embodiment of the present invention.
Fig. 10 is a schematic view illustrating a method of fabricating a semiconductor device according to a third embodiment of the present invention.
Fig. 11 is a schematic view illustrating a method of fabricating a semiconductor device according to a fourth embodiment of the present invention.
Fig. 12 is a schematic view showing a semiconductor device according to a preferred embodiment of the present invention.
Wherein the reference numerals are as follows:
100. substrate
110. A first metal layer
112. 142 through hole
114. 144 mask layer
116. 146 photo resist layer
118. 148 layer of barrier material
120. Barrier material layer
122. 222 another barrier layer
130. Stacked layers
140. Second metal layer
150. Barrier material layer
152. 252 barrier layer
160. 260 passage hole
162. Channel layer
164. Insulating layer
166. Conductive layer
170. 170a, 370 channel structure
180. Insulating layer
200. 200a, 201 semiconductor device
300. Three-dimensional NAND memory device
310. Word line contact plug
332. Conductive layer
334. Dielectric layer
362. Insulating layer
364. Channel layer
366. Insulating layer
P1 surface treatment manufacturing process
Maximum width of W1, W2, W3
Detailed Description
In order to provide those skilled in the art with a better understanding of the present invention, the following detailed description of the preferred embodiments of the present invention is provided to illustrate the present invention and the accompanying drawings. Those skilled in the art to which the invention relates will appreciate that the features of the various embodiments can be interchanged, recombined, mixed and modified to achieve other embodiments without departing from the spirit of the invention as defined by the appended claims.
Fig. 1 to 8 are schematic views illustrating a method for manufacturing a semiconductor device 200 according to a first embodiment of the present invention. First, referring to fig. 1, a substrate 100 is provided, and the substrate 100 is, for example, a silicon substrate (silicon substrate), a silicon-containing substrate (silicon-on substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate) or a substrate made of other suitable materials. It should be readily understood that various required semiconductor devices, such as transistors of the same or different conductivity type, for example, P-type transistors (PMOS), N-type transistors (NMOS), memories, or interconnect structures (interconnects), may be further formed on or in the substrate 100 according to actual device requirements.
Next, a first metal layer 110 is formed on the substrate 100, and a via hole 112 penetrating the first metal layer 110 is formed in the first metal layer 110 through a mask structure formed on the first metal layer 110. In detail, the mask structure includes a mask layer 114 and a photoresist layer 116 sequentially stacked on the first metal layer 110, and a patterning process is performed through the mask structure to sequentially transfer the pattern of the photoresist layer 116 onto the underlying mask layer 114 and the first metal layer 110, so as to form a via 112 in the first metal layer 110 and expose a portion of the substrate 100. In one embodiment, the first metal layer 110 includes a metal conductive material such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), etc., the mask layer 114 includes a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, etc., and the photoresist layer 116 includes a suitable photoresist material, but not limited thereto.
After removing the photoresist layer 116, a barrier material layer 118 is formed on the substrate 100 by a deposition process, filling the via 112 and further covering the mask layer 114, as shown in fig. 2. It should be noted that the barrier material layer 118 includes, for example, a conductive material, preferably selected from a group consisting of indium aluminum zinc oxide (InAlZnO), indium TiN Oxide (ITO), doped Indium Gallium Zinc Oxide (IGZO), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), in the embodiment, the barrier material layer 118 may selectively have a single-layer structure or a composite-layer structure, but not limited thereto.
As shown in fig. 3, a planarization process is performed to remove the barrier material layer 118 covering the mask layer 114 and further remove the mask layer 114, thereby forming a barrier material layer 120 in the first metal layer 110. Wherein the top surface of the barrier material layer 120 is flush with the top surface of the first metal layer 110.
Then, as shown in fig. 4, at least one stack layer 130, a second metal layer 140 and another mask structure are sequentially formed on the barrier material layer 120 and the first metal layer 110, and a via 142 penetrating the second metal layer 140 is formed in the second metal layer 140 through the another mask structure. In detail, the another mask structure includes a mask layer 144 and a photoresist layer 146 sequentially stacked on the second metal layer 140, and a patterning process is performed through the another mask structure to sequentially transfer the pattern of the photoresist layer 146 onto the underlying mask layer 144 and the second metal layer 140, so that a via 142 is formed in the second metal layer 140 and a portion of the stacked layer 130 is exposed. The via 142 is formed at a position aligned with the underlying barrier material layer 120, for example, as shown in fig. 4.
It should be noted that the stacked layer 130 may include any suitable material and thickness, and in the embodiment, although the stacked layer 130 includes a single layer as an implementation aspect, the stacked layer 130 may include a plurality of stacked layers according to actual device requirements, and is not limited to the one shown in fig. 4. In addition, the second metal layer 140 may also include a metal conductive material such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, etc., the mask layer 144 may include a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, etc., and the photoresist layer 146 may include a suitable photoresist material, but is not limited thereto.
After removing the photoresist layer 146, a barrier material layer 148 is formed on the substrate 100 by a deposition process, filling the via 142 and further covering the mask layer 144, as shown in fig. 5. It is noted that the barrier material layer 148 also comprises a conductive material, preferably selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride. In one embodiment, the barrier material layer 148 and the barrier material layer 120 may comprise the same conductive material, but not limited thereto. In addition, the barrier material layer 148 may also have a single-layer structure or a multi-layer structure, but not limited thereto.
As shown in fig. 6, another planarization process is performed to remove the barrier material layer 148 covering the mask layer 144, and further remove the mask layer 144 to form a barrier material layer 150 in the second metal layer 140. Wherein the top surface of the barrier material layer 150 is flush with the top surface of the second metal layer 140.
As shown in fig. 7, a via hole 160 is formed on the substrate 100 to sequentially penetrate the second metal layer 140, the stack layer 130, and a portion of the first metal layer 110. Note that the via hole 160 is formed just through the barrier material layer 150 (shown in fig. 6) in the second metal layer 140 and the barrier material layer 120 (shown in fig. 6) in the first metal layer 110, so that the barrier layer 152 and the barrier layer 122 can be formed simultaneously. Note that barrier layer 152 and barrier layer 122 are located at the top and bottom of via hole 160, respectively, and directly contact the top and bottom surfaces of stack 130. It should be easily understood by those skilled in the art that although the cross-sectional view shown in fig. 7 shows the barrier layer 152 on two opposite sidewalls of the top of the via 160 and the other barrier layer 122 on two opposite sidewalls and the bottom of the via 160, from a top view (not shown), the barrier layer 152 surrounds the sidewalls of the via 160, and the other barrier layer 122 integrally covers the bottom of the via 160, but not limited thereto.
Then, as shown in fig. 8, a via structure 170 is formed to fill the via hole 160, and the via structure 170 includes a functional layer sequentially formed on an inner sidewall of the via hole 160 and a filling layer to fill a remaining space of the via hole 160. In the present embodiment, the functional layers include a channel layer 162 and an insulating layer 164 sequentially stacked on the inner sidewall of the channel hole 160, and the filling layer includes a conductive layer 166, wherein the channel layer 162 includes, for example, indium aluminum zinc oxide (izo), indium tin oxide (ito) or other suitable conductive materials, and the insulating layer 164 includes, for example, hafnium oxide (HfO) 2 ) Hafnium silicon oxide (HfSiO) 4 ) Hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO) 2 ) Or titanium oxide (TiO) 2 ) The conductive layer 166 may comprise a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, but not limited thereto.
With this configuration, the channel structure 170 may form a vertically disposed gate structure, sequentially pass through the second metal layer 140, the stack layer 130 and partially pass through the first metal layer 110, and the channel structure 170, the first metal layer 110 and the second metal layer 140 together form a transistor (transistor). Thus, the conductive layer 166 can be used as a gate (gate), and the vertical pillar-shaped insulating layer 164 and the channel layer 162 sequentially surround the outer sidewall of the conductive layer 166 to be used as a gate dielectric layer (gate dielectric layer) and a gate channel (gate channel) of the gate, respectively, so that the gate can achieve the effect similar to a gate-all-around (GAA). In addition, the second metal layer 140 penetrated by the via structure 170 and the first metal layer 110 penetrated by part of the via structure may be used as a source/drain (S/D) of the gate, respectively, wherein a barrier layer 152 is interposed between the second metal layer 140 and the via structure 170, and another barrier layer 122 is interposed between the first metal layer 110 and the via structure 170, so as to block metal ions diffused from the second metal layer 140 and/or the first metal layer 110 to the via layer 162, thereby preventing the via layer 162 of the via structure 170 from being contaminated.
Thereby, the semiconductor device 200 of the present embodiment is completed. According to the manufacturing method of the embodiment, another barrier layer 122 and another barrier layer 152 are additionally disposed between the first metal layer 110, the second metal layer 140 and the via structure 170, so as to prevent the via layer 162 in the via structure 170 from directly contacting the first metal layer 110 or the second metal layer 140, and prevent the metal ions from the second metal layer 140 and/or the first metal layer 110 from diffusing and contaminating the via layer 162, thereby improving the problems of the transistor threshold voltage drop and the like derived from the metal ions diffusion. It is noted that the material of the barrier layer 122 and/or the barrier layer 152 is selected from the group consisting of ito, doped izo, tin nitride, tan, and w, and is used as a contact layer between the gate and the gate dielectric layer or as a buffer layer (RC reduce layer) for reducing RC delay, and is sandwiched between the first metal layer 110 or the second metal layer 140 and the channel structure 170, wherein the first metal layer 110 may further surround the bottom of the channel structure 170. Thus, the semiconductor device 200 of the present embodiment can have optimized structural reliability and achieve good device performance.
In addition, it should be readily apparent to those skilled in the art that other aspects of the semiconductor device and the method for fabricating the same may be formed without limitation to the above embodiments. Further embodiments or variations of the method of the semiconductor device of the present invention are described below. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.
Referring to fig. 9, a step diagram of a method for fabricating a semiconductor device according to a second embodiment of the invention is shown. The overall structure of the semiconductor device in this embodiment is substantially the same as the overall structure of the semiconductor device 200 in the first embodiment, and the description of the same parts is omitted here. The main difference between this embodiment and the first embodiment is that the barrier layer 252 and the other barrier layer 222 are formed directly by the surface treatment process P1 without depositing a barrier material layer.
In detail, in the present embodiment, the steps shown in fig. 1 to fig. 5 in the previous embodiments are omitted, the first metal layer 110, the stacked layer 130 and the second metal layer 140 stacked on the substrate 100 are directly formed, and the via hole 260 penetrating through the second metal layer 140, the stacked layer 130 and a portion of the first metal layer 110 is formed to partially expose the surfaces of the second metal layer 140, the stacked layer 130 and the first metal layer 110, as shown in fig. 9. Then, a surface treatment process P1, such as a nitridation process, is performed to nitride the exposed surfaces of the second metal layer 140 and the first metal layer 110 to form a barrier layer 252 and another barrier layer 222, which are also located at the top and bottom of the via 260 and can directly contact the top and bottom surfaces of the stack 130. It should be noted that the barrier layer 252 and the another barrier layer 222 respectively include nitrides of the materials of the second metal layer 140 and the first metal layer 110, for example, if the second metal layer 140 and the first metal layer 110 include metallic materials such as titanium, tantalum, or tungsten, the barrier layer 252 and the another barrier layer 222 include materials such as titanium nitride, tantalum nitride, or tungsten nitride, but not limited thereto.
Thus, in the subsequent manufacturing process, the via structure shown in fig. 7 in the previous embodiment can also be formed in the via hole 260, so that the barrier layer 252 and the another barrier layer 222 can be respectively sandwiched between the first metal layer 110 or the second metal layer 140 and the via structure, thereby preventing the metal ions from the second metal layer 140 and/or the first metal layer 110 from diffusing and contaminating the via structure. Therefore, the semiconductor device manufactured by the manufacturing method of the embodiment also has optimized structural reliability and can achieve good device performance.
Referring to fig. 10, a schematic step diagram of a method for manufacturing a semiconductor device according to a third embodiment of the invention is shown. The overall structure of the semiconductor device 200a in this embodiment is substantially the same as the overall structure of the semiconductor device 200 in the first embodiment, and the description of the same parts is omitted here. The main difference between the present embodiment and the first embodiment is that an isolation layer 180 is additionally disposed between the barrier layer 152 and the channel structure 170.
In detail, in the present embodiment, after the barrier material layer 150 shown in fig. 6 is formed in the second metal layer 140, an isolating material layer (not shown) is additionally formed on the second metal layer 140 and the barrier material layer 150, for example, a conductive material selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride, preferably the same conductive material as the barrier material layer 150.
Thus, when the via hole 160 shown in fig. 7 is formed subsequently, the isolation material layer is partially removed to form the isolation layer 180, and the isolation layer 180 is sandwiched between the subsequently formed via structure 170 and the barrier layer 152. Thus, the isolation layer 180 is disposed to further prevent metal ions from the second metal layer 140 from diffusing and contaminating the channel structure 170, and the maximum width W1 of the channel structure 170 in the horizontal direction may be greater than the maximum width W2 of the barrier layer 152 in the horizontal direction, so that the top of the channel structure 170 may partially overlap the second metal layer 140 in the vertical direction. It is noted that in the embodiment where the isolation layer 180 and the barrier layer 152 comprise the same conductive material, the isolation layer 180 can be regarded as an extension of the barrier layer 152, such that the maximum width W1 of the barrier layer (including the barrier layer 152 and the isolation layer 180 shown in fig. 10) is larger than the maximum width W2 of the other barrier layer 122 as a whole. Therefore, the semiconductor device 200a manufactured by the manufacturing method of the embodiment also has optimized structural reliability and can achieve good device performance.
Referring to fig. 11, a step diagram of a method for fabricating a semiconductor device according to a fourth embodiment of the invention is shown. The overall structure of the semiconductor device 201 in this embodiment is substantially the same as the overall structure of the semiconductor device 200 in the first embodiment, and the description of the same parts is omitted here. The main difference between this embodiment and the first embodiment is that the vertical sidewall at the top of the via structure 170a falls within the range of the barrier layer 152.
In detail, in the present embodiment, when the via structure 170a is formed, the top of the via structure 170a is intentionally not contacted with the second metal layer 140, so that the maximum width W3 of the via structure 170a in the horizontal direction is smaller than the maximum width W2 of the barrier layer 152 in the horizontal direction, and the metal ions from the second metal layer 140 can be further prevented from diffusing and contaminating the via structure 170a. Therefore, the semiconductor device 201 manufactured by the manufacturing method of the embodiment also has optimized structural reliability and can achieve good device performance.
In general, the present invention utilizes a deposition process or a surface treatment process to additionally provide a barrier layer between a channel layer and a metal layer including a metal material, and the barrier layer prevents the channel layer from directly contacting the metal layer to block metal ions from diffusing from the metal layer to the channel layer, thereby effectively preventing the channel layer from being contaminated by the metal ions and improving the problems of the transistor starting voltage drop and the like derived from the diffusion of the metal ions. In addition, the barrier layer can be selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride and tungsten nitride, and can be further used as a contact layer between a gate and a gate dielectric layer or a buffer layer for reducing resistance-capacitance delay, so that the semiconductor device can have optimized structural reliability and can achieve good device performance.
Therefore, the manufacturing method and/or the semiconductor device of the invention can be applied to forming a semiconductor structure with a vertical columnar channel layer, such as a conductive column, a plug and the like, so as to improve the structure reliability and the performance of the channel layer. Referring to fig. 12, a cross-sectional view of a semiconductor device according to a preferred embodiment of the invention is shown. In the present embodiment, the semiconductor device is, for example, a three-dimensional NAND memory device 300, and includes a substrate 100, at least one stacked layer 130 disposed on the substrate 100, and a plurality of channel structures 370 penetrating the stacked layer structure 130.
In detail, the stacked layer 130 of the present embodiment includes a plurality of conductive layers 332 and a plurality of dielectric layers 334 stacked alternately, each of the dielectric layers 334 includes, for example, the same dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, and each of the conductive layers 332 includes, for example, the same conductive material, such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, but is not limited thereto. It is noted that any one of the conductive layers 332 and the dielectric layer 334 thereon together form a set of conductive-dielectric layer pairs, and each of the conductive-dielectric layer pairs is stacked to form a ladder structure (memory stack structure) as shown in fig. 12. Thus, the three-dimensional NAND memory device 300 can be electrically connected to the word line contact plugs 310 through the word lines (i.e., the conductive layers 332) of the layers with the fan-out (fan-out) structure on both sides.
In the present embodiment, the channel structure 370 also includes a functional layer and a filling layer sequentially formed on the inner sidewall of the channel hole (not shown), wherein the functional layer includes an insulating layer 362 and a channel layer 364 sequentially stacked on the inner sidewall of the channel hole, the insulating layer 362 includes, for example, a dielectric material, such as a composite layer structure including an oxide-nitride-oxide (ONO, not shown), and the channel layer 364 includes, for example, a semiconductor material, such as silicon or polysilicon, but not limited thereto. The filling layer includes an insulating layer 366, which includes a dielectric material such as silicon oxide, but not limited thereto.
Under this configuration, the channel structures 370, the stacked layer 130, the first metal layer 110 and the second metal layer 140 (respectively serving as source/drain electrodes) may form transistors together, and the intersection of each channel structure 370 and each conductive layer 332 may serve as a memory cell (memory cell), and each conductive layer 332 may serve as a word line (word line) for controlling data writing and reading of each memory cell. It should be noted that, by additionally disposing the barrier layer 152 and the another barrier layer 122 between the via structure 370 and the first metal layer 110 and the second metal layer 140, the via structure 370 can be prevented from directly contacting the first metal layer 110 or the second metal layer 140, so as to prevent the metal ions from the second metal layer 140 and/or the first metal layer 110 from diffusing and contaminating the via layer 364. Thus, the three-dimensional NAND memory device 300 of the present embodiment can also have a more reliable channel structure 370 and performance.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (20)
1. A semiconductor device, comprising:
a substrate;
at least one stack layer disposed on the substrate;
a first metal layer and a second metal layer disposed on the substrate and respectively located below and above the at least one stacking layer;
a via structure disposed on the substrate partially overlapping the second metal layer, the at least one stack layer, and a portion of the first metal layer; and
and the barrier layer is arranged in the second metal layer, wherein the barrier layer is clamped between the second metal layer and the channel structure, and the maximum width of the barrier layer in the horizontal direction is greater than that of the channel structure.
2. The semiconductor device according to claim 1, further comprising:
an isolation layer disposed between the barrier layer and the channel structure.
3. The semiconductor device of claim 2, wherein the barrier layer and the isolation layer comprise the same material.
4. The semiconductor device according to claim 1, further comprising:
another barrier layer is disposed within the first metal layer and overlaps a bottom portion of the channel structure.
5. The semiconductor device of claim 4, wherein the barrier layer and the further barrier layer have different maximum widths in a horizontal direction.
6. The semiconductor device of claim 4, wherein the barrier layer, the further barrier layer, directly contact the at least one stack layer.
7. The semiconductor device of claim 1, wherein the barrier layer and the further barrier layer are selected from the group consisting of indium aluminum zinc oxide, indium tin oxide, doped indium gallium zinc oxide, titanium nitride, tantalum nitride, and tungsten nitride.
8. The semiconductor device of claim 1, wherein the via structure comprises a functional layer and a fill layer, wherein the fill layer comprises a metallic material or an insulating material.
9. The semiconductor device of claim 8, wherein the functional layer comprises a channel layer comprising indium gallium zinc oxide or indium tin oxide, and an insulating layer comprising a high dielectric constant dielectric material between the channel layer and the fill layer.
10. The semiconductor device according to claim 8, wherein the functional layer comprises an insulating layer, and a channel layer interposed between the insulating layer and the filling layer, the channel layer comprising silicon or polysilicon, and the insulating layer comprising an oxide layer-nitride layer-oxide layer.
11. A method for manufacturing a semiconductor device, comprising:
providing a substrate;
forming at least one stack layer on the substrate;
forming a first metal layer and a second metal layer on the substrate, wherein the first metal layer and the second metal layer are respectively positioned below and above the at least one stacking layer; and
forming a via structure on the substrate partially overlapping the second metal layer, the at least one stack layer, and a portion of the first metal layer; and
and forming a barrier layer on the substrate, wherein the barrier layer is positioned in the second metal layer, the barrier layer is clamped between the second metal layer and the channel structure, and the maximum width of the barrier layer in the horizontal direction is greater than that of the channel structure.
12. The method for manufacturing a semiconductor device according to claim 11, further comprising:
forming a via hole in the substrate, penetrating through the second metal layer, the at least one stack layer, and a portion of the first metal layer.
13. The method for manufacturing a semiconductor device according to claim 12, further comprising, before the forming of the via hole:
forming a first barrier material layer within the second metal layer; and
partially removing the first barrier material layer when the via hole is formed, forming the barrier layer.
14. The method for manufacturing a semiconductor device according to claim 13, further comprising, before the forming of the via hole:
forming an isolation material layer on the second metal layer and the first barrier material layer; and
partially removing the insulating material layer when the via hole is formed, and forming an isolation layer between the first barrier layer and the via structure.
15. The method for manufacturing a semiconductor device according to claim 13, further comprising, before the forming of the via hole:
forming a second barrier material layer within the first metal layer, wherein the second barrier material layer is partially removed when the via is formed, and forming another barrier layer within the first metal layer, wherein the another barrier layer overlaps a bottom portion of the via structure.
16. The method of claim 15, wherein the forming of the second barrier material layer and the first barrier material layer further comprises:
forming a through hole in the second metal layer and the first metal layer through a mask structure; and
carrying out a deposition manufacturing process on the substrate; and
and carrying out a planarization process to form the first barrier material layer filling the through holes in the second metal layer and the second barrier material layer filling the through holes in the first metal layer.
17. The method for manufacturing a semiconductor device according to claim 12, further comprising, after the forming of the via hole:
and performing a nitridation process in the via hole to partially nitridize the second metal layer and the first metal layer to form the barrier layer and another barrier layer.
18. The method of claim 17, wherein the barrier layer and the another barrier layer comprise nitrides of the materials of the second metal layer and the first metal layer.
19. The method of manufacturing a semiconductor device according to claim 12, wherein the via structure is formed after the via hole is formed, and comprises a functional layer and a filling layer sequentially disposed in the via hole, wherein the filling layer comprises a metal material or an insulating material.
20. The method of claim 19, wherein the functional layer comprises a channel layer and an insulating layer between the channel layer and the filling layer, the channel layer comprises indium gallium zinc oxide or indium tin oxide, and the insulating layer comprises a high dielectric constant dielectric material.
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| CN202211731309.9A CN115915770A (en) | 2022-12-30 | 2022-12-30 | Semiconductor device and method for manufacturing the same |
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| CN202211731309.9A CN115915770A (en) | 2022-12-30 | 2022-12-30 | Semiconductor device and method for manufacturing the same |
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