CN115915766A

CN115915766A - Memory module and method for manufacturing the same

Info

Publication number: CN115915766A
Application number: CN202111152203.9A
Authority: CN
Inventors: 蔡文杰; 杨政达; 林宗玮
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2023-04-04

Abstract

The present invention provides a memory assembly comprising: a substrate; a plurality of word lines extending in a first direction, arranged in a second direction, and located on the substrate; a dummy structure located on the substrate adjacent to ends of the plurality of word lines, wherein the dummy structure comprises: a main body portion extending in the second direction; and a plurality of extension portions extending in the first direction, connected to the main body portion, and interposed between the main body portion and the plurality of word lines.

Description

Memory module and method for manufacturing the same

Technical Field

The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to memory devices and methods of fabricating the same.

Background

With the progress of technology, various electronic products are being developed towards light, thin, short and small trend, and the critical dimension of the memory device is also gradually reduced, so that the photolithography process is more and more difficult. In existing lithographic processes, methods to shrink critical dimensions include the use of larger Numerical Aperture (NA) optics, shorter exposure wavelengths (e.g., EUV), or interface media other than air (e.g., water immersion). As the resolution of the conventional photolithography process approaches the theoretical limit, manufacturers have turned to double-patterning (DP) methods to overcome the optical limit and further improve the integration of the memory device.

However, in the current patterning method, due to the different pattern density at the center and the end of the array region, the etching process is subject to loading effect (loading effect), which causes the profile of the memory cells at the center and the end of the array region to be inconsistent, thereby causing electrical problems.

Disclosure of Invention

The present invention is directed to a memory assembly comprising: a substrate; a plurality of word lines extending in a first direction, arranged in a second direction, and located on the substrate; a dummy structure located on the substrate adjacent to ends of the plurality of word lines, wherein the dummy structure includes: a main body portion extending in the second direction; and a plurality of extension portions extending in the first direction, connected to the main body portion, and interposed between the main body portion and the plurality of word lines.

The present invention is directed to a method of manufacturing a memory assembly, comprising: providing a substrate; forming a target layer and a hard mask layer on the substrate; patterning the hard mask layer to form a patterned hard mask layer, the patterned hard mask layer comprising: a plurality of first patterns, a plurality of second patterns and a plurality of third patterns, wherein the plurality of first patterns extend in a first direction and are arranged in a second direction, the second patterns are comb-shaped and are located between the plurality of first patterns and the third patterns, and the plurality of third patterns extend in the second direction and are arranged in the first direction; and transferring the plurality of first patterns, the plurality of second patterns and the plurality of third patterns to the target layer by using the patterned hard mask layer to form a plurality of word lines, a comb-shaped dummy structure and a plurality of landing pads.

Based on the above, the embodiment of the invention adds the dummy pattern in the array region and the routing region to reduce the loading effect between the end and the center of the array region during the etching process.

Drawings

FIG. 1A is a top view of a storage assembly according to one embodiment of the invention;

FIG. 1B is an enlarged partial view of the area 50 of FIG. 1A;

FIGS. 2A-2H are top views of a method of fabricating a memory device according to one embodiment of the present invention;

FIGS. 3A to 3H are cross-sectional views taken along line III-III of FIGS. 2A to 2H;

FIGS. 4A-4H are cross-sectional views taken along line IV-IV of FIGS. 2A-2H;

fig. 5A to 5H are cross-sectional views of the line V-V of fig. 2A to 2H.

Detailed Description

Referring to fig. 1A and 1B, a memory device 100 is formed on a substrate 10. In the direction D2, the substrate 10 may be divided into a plurality of blocks A0, A1, A2, A3, …, and the like. Each block, illustrated as block A1, may include an array region R1, a transition region R2 and a winding region R3, wherein the transition region R2 is located between the array region R1 and the winding region R3.

The memory device 100 includes a plurality of word lines WL and a plurality of select gates SG. One end of each word line WL is located in the array region, and the other end extends to the routing region. In some embodiments, the word lines WL are aligned in an "I" shape with one end aligned with one another; the other ends of the word lines WL are not cut and arranged in a horizontal V shape.

For example, the plurality of word lines WL includes a plurality of word lines WL ₀ 、WL ₁ 、WL ₂ . Multiple word lines WL ₀ /WL ₂ Disposed in the array region R1 of the block A0/A2 and having an end E ₀₀ /E ₂₀ And also extends to the winding region R3 and is arranged in a transverse V shape, respectively. Multiple word lines WL ₀ /WL ₂ And the other end (not shown) thereof is located in the array region R1 without extending to the other winding region (not shown), and is aligned in an "I" shape, respectively. Multiple word lines WL ₁ /WL ₃ Disposed in the array region R1 of the block A1/A3 and at the end thereofTerminal E ₁₀ /E ₃₀ Do not extend to the winding region R3, and are cut and arranged into an I shape. Multiple word lines WL ₁ /WL ₃ And the other end (not shown) thereof is located in the array region R1 and extends to the other winding region (not shown), and is arranged in a transverse "V" shape, respectively.

The memory device 100 further includes a plurality of select gates SG disposed at both sides of the plurality of word lines WL, respectively. A plurality of select gates SG are disposed in the array region R1.

Multiple select gates SG arranged on multiple word lines WL ₀ Two-sided selection gate SG ₀₀ (not shown) with SG ₀₁ Arranged on a plurality of word lines WL ₁ Multiple selection gates SG on both sides ₁₀ And SG ₁₁ Arranged on a plurality of word lines WL ₂ Multiple selection gates SG on both sides ₂₀ And SG ₂₁ And arranged on multiple word lines WL ₃ Multiple selection gates SG on both sides ₃₀ And SG ₃₁ (not shown).

The memory device 100 further includes a plurality of landing pads LP disposed in the routing region R3 as contacts (pick up) for the word lines WL. The landing pad LP comprises a landing pad LP ₀₁ 、LP ₂₀ 、LP ₂₁ (shown on the left side of FIG. 1A). Landing pad LP ₀₁ 、LP ₂₀ 、LP ₂₁ Respectively extending in a direction D2 and aligned in a direction D1. In addition, the landing pad LP ₀₁ 、LP ₂₀ 、LP ₂₁ Aligned with each other in the direction D2. Landing pad LP ₀₁ And LP ₂₀ Separated from each other and arranged on multiple word lines WL ₁ End E of ₁₀ And are aligned with each other along the direction D2. Landing pad LP ₀₁ A plurality of word lines WL extending from the block A1 to the block A0 ₀ End E of ₀₀ And (4) connecting. Landing pad LP ₂₀ A plurality of word lines WL extending from the block A1 to the block A2 ₂ End E of ₂₀ And (4) connecting. Landing pad LP ₂₁ Arranged at a plurality of word lines WL ₃ End E of ₃₀ And extending from the block A3 to the block A2 and connecting with another part of the plurality of word lines WL ₂ End E of ₂₀ And (4) connecting. The landing pad LP further includes other landing pads respectively disposed on the plurality of word lines WL ₀ And WL ₂ Relative to E ₀₀ And E ₂₀ And (2) the other end (right side of FIG. 1A, not shown), and is connected with WL ₁ And WL ₃ And (4) connecting.

In an embodiment of the present invention, the memory component 100 further includes a dummy structure DS disposed between the winding region R3 and the array region R1. The dummy structure DS is disposed beside a plurality of word lines WL whose ends are arranged flush. In FIG. 1A, the dummy structures DS may include the dummy structures DS ₁ And DS ₃ . Dummy Structure DS ₁ Arranged in the block A1 and located at a plurality of word lines WL ₁ End E of ₁₀ Side by side; dummy Structure DS ₃ Arranged in block A3 and located at multiple word lines WL ₃ End E of ₃₀ And (4) side. The dummy structure DS may also include other dummy structures respectively disposed in the blocks A0 and A2 and located on the word lines WL ₀ And WL ₂ By the other end (not shown). The dummy structure DS may be floating without being connected to an external circuit.

The dummy structure DS is comb-shaped, for example. The dummy structure DS includes a main body MP and a plurality of extensions EP. The main portion MP is located in the transition region R2, and the main portion MP is adjacent to the landing pad LP by a non-zero distance. The shape and arrangement direction of the main body portion MP are more similar to those of the landing pad LP than the plurality of extension portions EP. The main body MP and the landing pad LP are both solid blocks. The main body MP extends in the same direction as the landing pad LP, and extends in the direction D2.

A plurality of extension portions EP are located in the array region R1. The shape and arrangement direction of the plurality of extension portions EP are more similar to those of the word lines WL than the main body portion MP. The extending directions of the plurality of extending portions EP are the same as the extending direction of the word lines WL, and all extend along the direction D1. The plurality of extension portions EP are also arranged in the same direction as the arrangement direction of the word lines WL, and are all arranged along the direction D2. The extension portions EP are connected to the main body portion MP and adjacent to the word lines WL at a non-zero distance. The distance d1 between the extension EP and the plurality of word lines WL is less than 114 nanometers (nm), for example, between 30nm and 114 nm. Selection gate SG ₁₀ And SG ₁₁ Extending and protruding the word line WL ₁ The length L of the main portion MP is smaller than the word line WL ₁ Two sidesIs selected gate SG ₁₀ And SG ₁₁ The distance d3 therebetween.

Width W of extension EP ₂ Width W of multiple word lines WL greater than 2 times ₁ E.g. the width W of a plurality of word lines WL ₁ 2.5 times to 3.5 times. Width W of main body MP ₃ Greater than the width W of the extension EP ₂ E.g. the width W of a plurality of word lines WL ₁ 6 times to 9 times.

The dummy structure DS is formed by pattern transfer of a hard mask pattern (also referred to as a dummy pattern). The dummy structure DS may be disposed to improve a loading effect during the etching process for forming the word lines WL and the landing pads LP, so that the center and the end of the array region have similar profiles. The process of the memory device 100 can be described with reference to the following embodiments, but is not limited thereto.

An embodiment of the invention provides a method for manufacturing a memory device, which includes the following steps. First, referring to fig. 2A to 5A, a substrate 10 is provided. The substrate 10 may include an array region R1, a transition region R2, and a routing region R3. In this embodiment, the array region R1 may be a memory array region having one or more memory cells, and the routing region R3 may be a routing region having one or more word line contacts. The transition region R2 is between the array region R1 and the winding region R3. In one embodiment, the substrate 10 may be a semiconductor substrate, a semiconductor compound substrate, or a semiconductor-on-insulator (SOI) substrate. In the present embodiment, the substrate 10 is a silicon substrate.

Next, a target layer 12 is formed on the substrate 10. The target layer 12 may be a stacked layer 110 stacked in the direction D3. Specifically, as shown in the enlarged view of fig. 5A, the stack layer 110 may include a tunneling dielectric layer 102, a patterned floating gate layer 104, an inter-gate dielectric layer 106, a control gate layer 108, a metal layer 112, and a cap layer 114 from bottom to top.

The material of the tunneling dielectric layer 102 may be, for example, silicon oxide. Patterned floating gate layer 104 may extend along direction D2 and may comprise a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. The inter-gate dielectric layer 106 may be a composite layer of Nitride/Oxide/Nitride (NONON), for example, but the invention is not limited thereto, and the composite layer may be three, five or more layers. The material of the control gate layer 108 may include a conductor material, such as doped polysilicon, undoped polysilicon, or a combination thereof. The material of metal layer 112 may be, for example, W, tiN or a combination thereof. The material of the cap layer 114 may include a dielectric material, such as silicon nitride, silicon oxynitride, or a combination thereof.

Then, the sacrificial layer 14 and the hard mask layer 16 are formed on the stack layer 110. The sacrificial layer 14 may also be referred to as a hard mask layer. The sacrificial layer 14 may be a silicon oxide layer. The hard mask layer 16 may be a single layer or a multilayer. The hard mask layer 16 is, for example, a polysilicon layer. Thereafter, a core layer 18 is formed on the hard mask layer 16. The core layer 18 includes

core patterns

18a, 18b, 18c at the array region R1, the transition region R2, and the winding region R3, respectively. The core pattern 18a extends in the direction D1; the

core patterns

18b, 18c extend in the direction D2. The direction D1 and the direction D2 are perpendicular to each other. The core pattern 18b is connected to the core pattern 18a, and is separated from the core pattern 18c.

In an embodiment, the core layer 18 may comprise a carbide layer. In another embodiment, the core layer 18 may include a carbide layer and an anti-reflective layer. The material of the carbide layer may be, for example, spin-on-carbon (SoC). The material of the anti-reflection layer may be, for example, silicon oxynitride. The core layer 18 is formed by, for example, first forming a carbide material layer and an antireflection material layer, and then forming a photoresist pattern on the antireflection material layer through a photolithography process. In some embodiments, after forming the photoresist pattern, a trimming process is also performed such that the width of the formed photoresist pattern is reduced. And then, carrying out an etching process to transfer the pattern of the photoresist pattern downwards to the anti-reflection material layer and the carbide material layer. Then, the photoresist pattern is removed.

Referring to fig. 2B to 5B and fig. 2C to 5C, a Self-aligned Double Patterning (SADP) process is performed to form the spacers 20 on the hard mask layer 16. The material of the spacer 20 includes an oxide, such as silicon oxide. In an alternative embodiment, a Self-aligned quad Patterning (SAQP) process may also be performed to form the spacers 20 with higher pattern density. The spacer 20 is formed, for example, by first forming a spacer material layer 19 on the hard mask layer 16 and on the top surface and sidewalls of the core layer 18, as shown in fig. 2B to 5B. An anisotropic etching process is then performed on the spacer material layer 19 to remove a portion of the spacer material layer 19 until the hard mask layer 16 and the top surface of the core layer 18 are exposed, so as to form a spacer 20 on the sidewall of the core layer 18. Then, the spacer 20 and the core layer 18 are used as masks, and etching is continued to remove the hard mask layer 16 not covered by the spacer 20 and the core layer 18, so as to form

hard mask patterns

16a, 16b, and 16c in the array region R1, the transition region R2, and the winding region R3, respectively. During the etching of the hard mask layer 16, the core layer 18 is also etched away to expose a portion of the top surface of the

hard mask patterns

16a, 16b, 16C, as shown in fig. 2C to 5C. The hard mask pattern 16a extends in the direction D1; the

hard mask patterns

16b, 16c extend in the direction D2. The hard mask pattern 16b is connected with the hard mask pattern 16a, and is separated from the hard mask pattern 16c.

Referring to fig. 2D to 5D and fig. 2E to 5E, a cutting process is performed on the spacer 20 to form the

spacers

20a, 20b, and 20c separated from each other. The process of dividing the spacer 20 is explained as follows.

First, referring to fig. 2D to fig. 5D, a mask layer 22 is formed on the sacrificial layer 14. The mask layer 22 is, for example, a patterned photoresist layer. The mask layer 22 includes

mask patterns

22a, 22b, 22c. The mask pattern 22a partially covers the array region R1; the mask pattern 22b covers a part of the winding region R3 and the transition region R2; the mask pattern 22c covers another portion of the winding region R3 and the transition region R2. The

mask patterns

22a, 22b, 22c are separated from each other. The spacers 20, the

hard mask patterns

16a and 16b, and the sacrificial layer 14 at the end of the array region R1 and at one side of the transition region R2 (near the array region R1) are exposed between the

mask patterns

22a and 22b and between the

mask patterns

22a and 22c. The spacers 20, the

hard mask patterns

16c and 16b, and the sacrificial layer 14 in the winding region R3 and on the other side (away from the array region R1) of the transition region R2 are exposed between the

mask patterns

22b and 22c.

Referring to fig. 2E to 5E, an etching process, such as an anisotropic etching process, is performed to remove the spacers 20 not covered by the

mask patterns

22a, 22b, and 22c, so as to form the

spacers

20a, 20b, and 20c. Thereafter, the

mask patterns

22a, 22b, 22c are removed. The spacers 20a are located in the array region R1 apart from each other, and each has a length in the direction D1 smaller than the length of the sacrificial layer 14 in the array region R1 not covered by the hard mask pattern 16 a. The spacers 20b are located in the transition region R2, extend in the direction D2, and are arranged apart from each other in the direction D2. The spacers 20c are located in the winding region R3, extend in the direction D2, and are arranged apart from each other in the direction D2.

Referring to fig. 2F to 5H, a patterning process of the target layer 12 is performed to form

target patterns

12a, 12b, and 12c. The patterning process of the target layer 12 is explained as follows. The target layer 12 is etched through the hard mask layer 16 'shown in fig. 2G, and the formation of the hard mask layer 16' is described below with reference to fig. 2F to 5G.

Referring to fig. 2F to 5G, a mask layer 24 is formed on the substrate 10. Mask layer 24 is, for example, a patterned photoresist layer. The mask layer 24 has openings OP1 and OP2. The opening OP1 exposes the spacers 20a, the hard mask pattern 16a and the sacrificial layer 14 in the array region R1. The opening OP2 extends in the directions D1 and D2. The shape of the opening OP2 is, for example, a double-row comb shape composed of a plurality of crosses. The opening OP2 exposes the hard mask pattern 16c and the sacrificial layer 14 in the routing region R3 in the direction D1. The opening OP2 exposes the hard mask pattern 16c in the winding region R3 in the direction D2.

Referring to fig. 2G to 5G, the

hard mask patterns

16a, 16b and 16c are patterned into a hard mask layer 16' by using the mask layer 24 and the spacers 20a as masks. The hard mask layer 16 'includes hard mask patterns 16a', 16b ', 16c'. The hard mask pattern 16a' covers the array region R1; the hard mask pattern 16b' covers the transition region R2 and extends to the array region R1; the hard mask pattern 16c' covers the winding region R3.

The hard mask pattern 16b' may also be referred to as a dummy pattern. The hard mask pattern 16b' has a comb shape, for example. The hard mask pattern 16b' includes a body portion mp and a plurality of extension portions ep. The main body portion mp is a solid block-shaped body extending in the direction D2 and located in the transition region R2And is adjacent to the hard mask pattern 16c 'by a non-zero distance d 2'. The plurality of extending portions ep extend along the direction D1, are arranged along the direction D2, and are located in the array region R1. The plurality of extension portions ep are connected to the body portion mp and are adjacent to the hard mask pattern 16a 'by a non-zero distance d 1'. Width W of main body mp ₃ ' greater than the width W of each extension ep ₂ ', and the width W of each extension ep ₂ ' greater than the width W of each hard mask pattern 16a ₁ '. The distance d1' between the hard mask pattern 16b ' and the hard mask pattern 16a ' is controlled according to the capability of the process to reduce the loading effect of the subsequent etching process. For example, the distance d1' is controlled to be less than 114nm, for example, between 30nm and 114 nm.

Referring to fig. 2H to 5H, an etching process, which may be an anisotropic etching process, such as a Reactive Ion Etching (RIE) process, is performed to pattern the sacrificial layer 14 and the target layer 12, using the hard mask layer 16' as a mask, thereby forming a patterned oxide layer and

target patterns

12a, 12b, 12c. The mask layer 24 and the spacers 20a are then removed. Since the distance d1' between the hard mask pattern 16b ' and the hard mask pattern 16a ' is controlled to be in a proper range and is a solid block, the loading effect between the central region and the end region of the array region R1 can be reduced during the etching process, so that the target pattern 12a between the central region and the end region has a similar profile.

The target pattern 12a may include a plurality of target patterns 12a ₁ . A plurality of target patterns 12a ₁ Is located in the array region R1, extends along the direction D1, and is arranged along the direction D2.

A plurality of target patterns 12c are located in the winding region R3. The plurality of target patterns 12c includes a plurality of target patterns 12c ₀ And 12c ₁ Which extend along the directions D2, respectively. A plurality of target patterns 12c ₀ And 12c ₁ Are arranged along the direction D1, and extend along the direction D2. Target pattern 12c ₀ And the target pattern 12c ₁ Are separated from each other and are arranged in a row along the direction D2. The width of the target pattern 12c is, for example, the target pattern 12a ₁ Width W of ₁ 4 times to 6 times.

The target patterns 12b are located in a plurality of target patterns 12a ₁ And a plurality of target patterns 12c. The target pattern 12b is also called a dummy structure, for example, in a comb shape. The target pattern 12b includes a main body portion MP and a plurality of extension portions EP. The main body portion MP is a solid block-shaped body extending along the direction D2, located in the transition region R2, and adjacent to the target pattern 12c with a non-zero distance. The plurality of extension portions EP extend along the direction D1, are arranged along the direction D2, and are located in the array region R1. The plurality of extending portions EP are connected to the main body portion MP and are spaced from the target pattern 12a by a non-zero distance d1 ₁ Adjacent and at a non-zero distance d2 from the target pattern 12c. Extension EP and target pattern 12a ₁ The distance d1 therebetween is smaller than 114nm, for example between 30nm and 114 nm.

Width W of extension EP ₂ Width W of the target pattern larger than 2 times ₁ E.g. the width W of the target pattern ₁ 2.5 times to 3.5 times. Width W of main body MP ₃ Greater than the width W of the extension EP ₂ For example, the target pattern 12a ₁ Width W of ₁ From 4 times to 9 times.

Referring to FIG. 1B, the target pattern 12a may further include a plurality of target patterns 12a ₁₀ 、12a ₁₁ . Target pattern 12a ₁₀ 、12a ₁₁ Is located at the target pattern 12a ₁ On both sides of the base. Target pattern 12a ₁₀ 、12a ₁₁ Is located in the array region R1, extends along the direction D1, and is arranged along the direction D2. Target pattern 12a ₁₀ 、12a ₁₁ Is, for example, the target pattern 12a ₁ Width W of ₁ 4 times to 6 times.

Referring to FIGS. 1A and 1B, in some embodiments, the target pattern 12a ₁ To include a word line WL ₁ Patterned stack layer 110a (shown in the enlarged partial view of fig. 5H). Patterned stack layer 110a includes tunneling dielectric layer 102, patterned floating gate layer 104a, inter-gate dielectric layer 106a, control gate layer 108, metal layer 112a, and capping layer 114a. In other embodiments, the tunneling dielectric layer 102 may also be patterned. The height-to-width ratio of patterned stacked layer 110a is 10 to 12. Target pattern 12a ₁₀ 、12a ₁₁ Respectively is an inclusion selectionLine SG ₁₀ And SG ₁₁ The patterned stack of layers of (a). Target pattern 12c ₀ 、12c ₁ Respectively include as word lines WL ₀ Landing pad LP of ₀₁ And word line WL ₂ Landing pad LP of ₂₀ The patterned stack of layers of (a). The target pattern 12b is a dummy structure including ₁ Patterned stack of layers.

Although the above embodiments illustrate a series of patterning steps by taking flash memory as an example, the invention is not limited thereto. In other embodiments, the patterning step may also be used to form Dynamic Random Access Memory (DRAM) or similar target layers/films.

In summary, the hard mask pattern (also referred to as dummy pattern) for forming the dummy structure DS can improve the loading effect during the etching process for forming the word line and the landing pad, so that the center and the end of the array region have similar profiles to avoid the occurrence of bridging or defects. Also in this case, the target layers in the array region and the routing region may be patterned simultaneously, thereby forming a plurality of stacked structures with different pattern densities in the array region and the routing region.

Claims

1. A storage assembly, comprising:

a substrate;

a plurality of word lines extending in a first direction, arranged in a second direction, and located on the substrate;

a dummy structure located on the substrate adjacent to ends of the plurality of word lines, wherein the dummy structure comprises:

a main body portion extending in the second direction; and

and a plurality of extension parts extending in the first direction, connected with the main body part, and interposed between the main body part and the plurality of word lines.

2. The storage component of claim 1, wherein the dummy structure is comb-shaped.

3. The storage component of claim 1, wherein a width of the main portion of the dummy structure is greater than a width of each extension, and a width of the each extension is greater than a width of each word line.

4. The memory component of claim 1, wherein the body portion of the dummy structure is a solid block-like body.

5. The memory assembly of claim 1, further comprising two select gates on either side of the plurality of word lines, wherein the length of the body portion is less than a distance between the two select gates.

6. The memory component of claim 1, further comprising a plurality of landing pads extending in the second direction respectively connected to another plurality of wordlines, wherein the dummy structure is located between the plurality of landing pads and the plurality of wordlines.

7. A method of manufacturing a memory assembly, comprising:

providing a substrate;

forming a target layer and a hard mask layer on the substrate;

patterning the hard mask layer to form a patterned hard mask layer, the patterned hard mask layer comprising: a plurality of first patterns, a plurality of second patterns and a plurality of third patterns, wherein the plurality of first patterns extend in a first direction and are arranged in a second direction, the second patterns are comb-shaped and are located between the plurality of first patterns and the third patterns, and the plurality of third patterns extend in the second direction and are arranged in the first direction; and

and transferring the plurality of first patterns, the plurality of second patterns and the plurality of third patterns to the target layer by using the patterned hard mask layer to form a plurality of word lines, a comb-shaped dummy structure and a plurality of landing pads.

8. The method of manufacturing a memory assembly according to claim 7, wherein the second pattern includes a main body portion extending in the second direction and a plurality of extension portions extending in the first direction and aligned in the second direction.

9. The method of manufacturing a memory assembly according to claim 8, wherein the width of the main body portion is greater than the width of each extension portion, and the width of each extension portion is greater than the width of each first pattern.

10. The method of manufacturing a storage assembly of claim 8, wherein the body portion is a solid block-like body.