CN115913221A - Programmable delay circuit applied to anti-fuse type FPGA embedded PLL _ IP - Google Patents
Programmable delay circuit applied to anti-fuse type FPGA embedded PLL _ IP Download PDFInfo
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Abstract
The invention discloses a programmable delay circuit applied to an anti-fuse FPGA embedded PLL _ IP, belonging to the field of anti-fuse FPGA logic design and comprising a decoding configuration circuit and two groups of programmable delay sub-module circuits; the configuration signals of two groups of programmable delay sub-module circuits are different, and are respectively designed into a reference clock input end and a feedback clock input end of an anti-fuse type FPGA embedded with PLL _ IP, and the decoding configuration circuit can be programmed to output t which is minus 15 to plus 15 times of t A A long delay time. The decoding configuration circuit comprises a one-bit enable signal and a four-bit data input signal, when the antifuse-type FPGA is in a test mode, the four-bit data input signal comes from an internal register chain of the antifuse-type FPGA, and the state of the input signal can be configured based on a JTAG protocol; when the antifuse-type FPGA is used in the active mode, its programming input signal comes from the programmed antifuse switch, whose state is one-time programming. The invention can improve the anti-fuseThe embedded PLL _ IP of the FPGA type has the working flexibility and optimizes the antifuse FPGA clock network.
Description
Technical Field
The invention relates to the technical field of anti-fuse type FPGA logic design, in particular to a programmable delay circuit applied to an anti-fuse type FPGA embedded PLL _ IP.
Background
An FPGA (Field Programmable Gate Array) is a Programmable semi-custom device, and has the characteristics of flexible configuration, high speed, strong adaptability, short development period and the like. The FPGA can be classified into SRAM type FPGA, antifuse type FPGA, and FLASH type FPGA according to its programmed logic structure. The anti-fuse FPGA belongs to a one-time programmable FPGA, adopts an anti-fuse as a basic configurable unit, has the characteristics of non-volatility, high reliability, high confidentiality, high radiation resistance and the like, and therefore has a leading position in the fields of military industry and aviation.
A PLL (Phase Locked Loop) _ IP core (Intellectual Property core) is a clock management module embedded in an FPGA, and FPGA designers can reduce a large amount of development time by calling the PLL _ IP. The typical structure comprises five modules of a reference clock frequency divider, a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a feedback clock frequency divider, and a user can generate various required clocks by utilizing a programmable PLL _ IP based on an external input reference clock in the process of using the FPGA.
At present, a commercial SRAM type FPGA is provided with a PLL _ IP core capable of generating a more free clock signal, for example, a xlinx 7-series FPGA can shift the phase of a clock signal, select a PLL _ IP input clock or a feedback clock from a variety of clock sources outside or inside the FPGA, and dynamically adjust PLL settings when the FPGA works, but since an antifuse type FPFA has an antifuse as a basic unit and a special application scenario thereof, domestic research on PLL _ IP function expansion of the antifuse type FPGA is rare, and usually internal logic resources of the FPGA need to be called to realize additional functions.
Disclosure of Invention
The invention aims to provide a programmable delay circuit applied to an anti-fuse type FPGA embedded PLL _ IP, which is used for solving the problems in the prior art.
In order to solve the technical problem, the invention provides a programmable delay circuit applied to an anti-fuse FPGA embedded PLL _ IP, which comprises a decoding configuration circuit and two groups of programmable delay sub-module circuits; wherein the content of the first and second substances,
the two groups of programmable delay sub-module circuits have the same circuit structure and different configuration signals; each group of programmable delay submodule circuits respectively comprise a first-stage programmable delay circuit and a second-stage programmable delay circuit, wherein:
the first stage programmable delay circuit is used for coarse precision adjustment of signal delay and comprises a unit delay buffer A, three quadruple delay buffers B and three multiplexers, namely the delay length of the unit delay buffer A is t A The delay length of the quadruple delay buffer B is 4 × t A The first-stage programmable delay circuit can realize 0, 4 x t output A 、8×t A 、12×t A Four delays of different lengths;
the second stage programmable delay circuit is used for fine precision signal delay adjustment and consists of four unit delay buffers A and three multiplexers, namely, the delay length of the unit delay buffer A is t A The second-stage programmable delay circuit can realize 0 and 1 × t output A 、2×t A 、3×t A Four delays of different time lengths;
each group of programmable delay sub-module circuits is formed by connecting a first-stage programmable delay circuit and a second-stage programmable delay circuit in series, and the decoding configuration circuit is programmed to output 4-bit control signals to control the programmable delay sub-module circuits to output delay of 0-15 times t A A long delay time.
In one embodiment, two sets of programmable delay sub-module circuits are respectively designed at the reference clock input end and the feedback clock input end of the embedded PLL _ IP of the anti-fuse type FPGA,by programming the decoding configuration circuit, t of-15 to plus-15 times can be output A The delay time of length, wherein "-" and "+" are used for distinguishing the position relation of the reference clock signal relative to the feedback clock signal, and "+" is used for configuring the input delay size of the reference clock signal so that the reference clock signal is advanced relative to the feedback clock signal; "-" is used to configure the feedback clock input delay size such that the reference clock signal lags the feedback clock signal.
In one embodiment, the decoding configuration circuit comprises a one-bit enable signal and a four-bit data input signal, when the antifuse-type FPGA is in the test mode, the four-bit data input signal comes from an internal register chain of the antifuse-type FPGA, and the state of the input signal can be configured based on a JTAG protocol; when the antifuse-type FPGA is used in the active mode, the four-bit data input signal comes from the state of the antifuse switch after programming, which is a one-time programming.
In one embodiment, in the use mode, the embedded PLL _ IP is called by the dedicated programmer for the antifuse-type FPGA, and the configuration flow of the programmable delay circuit applied to the embedded PLL _ IP of the antifuse-type FPGA in the programmer interface is as follows:
determining a use scene of a PLL _ IP embedded in an antifuse FPGA;
the programmer selects the circuit information of the programmable delay submodule;
selecting a delayed +/-state;
selecting a delay time length;
the programmer programs an anti-fuse type FPGA;
and powering on for use.
In one embodiment, in the use mode, the configuration flow of the programmable delay circuit applied to the antifuse-type FPGA embedded with the PLL _ IP is specifically as follows:
a user determines whether to use the embedded PLL _ IP according to the application scene of the antifuse type FPGA; if the embedded PLL _ IP is used, determining a use mode, acquiring clock network information and anti-fuse type FPGA internal layout wiring information based on programming software, determining whether a programmable delay circuit applied to the embedded PLL _ IP of the anti-fuse type FPGA needs to be used, and if the programmable delay circuit is used, determining delay time and a delay mode which need to be configured;
selecting a PLL _ IP on an IP calling interface of a programmer; selecting programmable delay on a PLL _ IP interface, selecting a +/-state, namely selecting a programmable delay submodule circuit of a reference clock input end embedded with a PLL _ IP or a programmable delay submodule circuit of a feedback clock input end embedded with the PLL _ IP, and configuring an antifuse type FPGA; selecting delay time of the programmable delay submodule circuit, and selecting adjustable delay time precision t in a discrete mode in a configuration mode A The adjustable range is 0 to 15 x t A The delay time of (d);
the configuration information of the programmable delay circuit with the PLL _ IP embedded in the antifuse type FPGA is sent to a chip in a data code stream mode through a programming upper computer, and an internal circuit of the antifuse type FPGA addresses a corresponding antifuse based on the data code stream and conducts programming to complete configuration;
after programming is finished, power is on, an input signal input by the decoding configuration circuit is determined by the programming state of the corresponding antifuse, and the delay state of the programmable delay circuit applied to the antifuse type FPGA embedded PLL _ IP is successfully configured and used by a user.
In one embodiment, in the test mode, the configuration flow of the programmable delay circuit applied to the antifuse-type FPGA with the PLL _ IP embedded therein is as follows:
determining a test item of the antifuse-type FPGA;
determining a configuration mode of a programmable delay submodule circuit;
sending test data to the antifuse-type FPGA;
configuring a programmable delay submodule circuit;
the delay state of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL _ IP is successfully configured;
test feedback and repeat tests.
In one embodiment, in the test mode, the configuration flow of the programmable delay circuit applied to the antifuse-type FPGA embedded with the PLL _ IP is specifically as follows:
according to items to be tested of the antifuse FPGA, including layout and wiring, IP testing and port testing, determining a testing mode and testing contents; selecting whether to use a programmable delay circuit applied to an anti-fuse FPGA embedded PLL _ IP or not based on the determined test mode and test contents, and if so, determining a delay time configuration mode of a programmable delay submodule circuit;
based on a JTAG protocol, sending an instruction and a data code stream to the interior of the antifuse type FPGA to be tested through a test platform, and accessing an internal register chain of the antifuse type FPGA to be tested; the latch data of the internal register chain is used as an input signal of a decoding configuration circuit to configure the delay state of the programmable delay submodule circuit;
after the test instruction and the test data are sent, the delay state configuration of the programmable delay circuit of the anti-fuse FPGA embedded with the PLL _ IP is finished; and comparing the test feedback result with the expected result, and repeatedly testing according to the comparison result and the content of the test item.
In one embodiment, the configuration mode of the programmable delay circuit applied to the embedded PLL _ IP of the anti-fuse type FPGA is determined by the internal clock network layout wiring delay of the anti-fuse type FPGA and the frequency of the input clock and the feedback clock of the embedded PLL _ IP of the anti-fuse type FPGA; the output delay of the programmable delay circuit applied to the anti-fuse type FPGA embedded PLL _ IP is static delay, namely after programming, the delay state is fixed in the using process.
In one embodiment, the input clock signal of the embedded PLL _ IP of the antifuse-type FPGA, i.e., the input signal corresponding to the first set of programmable delay sub-module circuits, is sourced from an external clock, the output clock of the PLL _ IP of the previous stage, the input clock CLKxP from the differential I/O;
the feedback clock signal of the PLL _ IP embedded in the anti-fuse FPGA, namely the input signal source corresponding to the second group of programmable delay submodule circuits is the output clock of the PLL _ IP, the clock of a self-clock network after wiring, and the input clock CLKxN from the differential I/O.
In one embodiment, the power signal applied to the programmable delay circuit with the built-in PLL _ IP of the antifuse-type FPGA is an antifuse-type FPGA core power signal, and the ground signal is a ground signal with the built-in PLL _ IP of the antifuse-type FPGA, and the power-on state is consistent with the power-on state.
The invention provides a programmable delay circuit applied to an anti-fuse FPGA embedded PLL _ IP, which has the following beneficial effects:
(1) The coarse-fine precision delay adjustment of the relative delay between the PLL _ IP input reference clock and the feedback clock embedded in the anti-fuse FPGA can be realized;
(2) The PLL _ IP and the PLL _ IP are used simultaneously in the using process, and internal resources of a chip cannot be occupied;
(3) The delay of the feedback clock of the PLL _ IP with the thickness precision lagging or advancing relative to the input reference clock can be generated, the delay is suitable for different working states of the antifuse FPGA under a high-frequency clock and a low-frequency clock, the clock locking speed of the PLL _ IP can be improved, and particularly for a specific application scene, the system performance can be effectively improved;
(4) The discrete delay can be generated, the distributed delay of the clock signal in the clock network is compensated, the influence of the delay brought by the load on the performance of the anti-fuse type FPGA is effectively reduced, and the effect is more obvious in a large-scale system;
(5) The programmable delay line has flexible programming and simple structure, is suitable for the use requirements of different users, does not need to design a large number of delay lines, and can reduce certain chip design area.
Drawings
Fig. 1 is a schematic diagram of a programmable delay circuit applied to an antifuse-type FPGA embedded PLL _ IP provided in the present invention.
Fig. 2 is a schematic diagram of a programmable delay submodule circuit.
FIG. 3 is a diagram showing the relationship between the delay time and the input/output signals of the decoding configuration circuit applied to the programmable delay circuit with PLL _ IP embedded in the antifuse FPGA.
FIG. 4 is a flow chart of programming in user mode for a programmable delay circuit with built-in PLL _ IP for an antifuse-type FPGA.
FIG. 5 is a flow chart of a test mode of a programmable delay circuit with built-in PLL _ IP for an antifuse-type FPGA.
Detailed Description
The following describes a programmable delay circuit applied to an antifuse-type FPGA embedded with PLL _ IP in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As shown in FIG. 1, the present invention provides a programmable delay circuit applied to an antifuse-type FPGA embedded with PLL _ IP, which comprises a decoding configuration circuit and two sets of programmable delay sub-module circuits. The configuration signals of the two groups of programmable delay sub-module circuits are different, the two groups of programmable delay sub-module circuits are respectively designed at the reference clock input end and the feedback clock input end of the PLL _ IP embedded in the anti-fuse FPGA, and the decoding configuration circuit can output t which is minus 15 to plus 15 times of t by programming A A delay time of length, where t A Is the delay length of the unit delay buffer; "-" and "+" are used for distinguishing the position relation of the reference clock signal relative to the feedback clock signal, and "+" is used for configuring the input delay of the reference clock signal to lead the reference clock signal relative to the feedback clock signal; "-" is used to configure the feedback clock input delay size such that the reference clock signal lags the feedback clock signal.
The two groups of programmable delay sub-module circuits have the same structure, and respectively comprise a first-stage programmable delay circuit and a second-stage programmable delay circuit, as shown in fig. 2, the first-stage programmable delay circuit is used for coarsely adjusting the signal delay and comprises a unit delay buffer A (buffer A: XI 1:), three quadruple delay buffers B (buffer B: XI2, XI3, XI 4) and three multiplexers (XM 1, XM2 and XM 3), namely the delay length of the unit delay buffer A is t A The delay length of the quadruple delay buffer B is 4 × t A The first-stage programmable delay circuit can realize 0, 4 x t output A 、8×t A 、12×t A Four delays of different lengths; the second stage programmable delay circuit for fine-precision adjustment of signal delay is composed of four sets of unit delay buffers A (i.e., XI5, XI6, XI7, XI 8) and three multiplexers (i.e., XM4, XM5, and XM 6)That is, the delay length of the unit delay buffer A is t A The second-stage programmable delay circuit can realize 0 and 1 × t output A 、2×t A 、3×t A Four different time lengths of delay. Each group of programmable delay sub-module circuits is formed by connecting a first-stage programmable delay circuit and a second-stage programmable delay circuit in series, and by programming the decoding configuration circuit, 4-bit control signals are output to control the programmable delay sub-module circuits to output delay of 0-15 times t A A long delay time.
The relationship between the output signal of the decoding configuration circuit and the delay result of the programmable delay circuit applied to the antifuse-type FPGA embedded PLL _ IP is shown in table 1, wherein an EN signal of the decoding configuration circuit is used for configuring a state that a feedback clock of the antifuse-type PLL _ IP lags or advances relative to an input reference clock, and when EN =1' b0, the feedback clock of the antifuse-type PLL _ IP lags relative to the input reference clock; when EN =1' b0, the feedback clock of the antifuse-type PLL _ IP is advanced relative to the input reference clock.
As shown in fig. 3, the decoding configuration circuit includes a one-bit enable signal and a four-bit data input signal, and the input signal sources of the decoding configuration module mainly come from: 1. in the test mode, based on the test data of JTAG, 2. In the use mode, based on the programming configuration signal of the programmer corresponding to the state of the antifuse after the antifuse; the configuration information relationship is shown in the following table 1:
TABLE 1 delay time and input/output signal relationship table of decoding configuration circuit
As shown in fig. 4, a configuration flow in user mode of a programmable delay circuit applied to an antifuse-type FPGA embedded with PLL _ IP of the present invention is specifically:
a user determines whether to use the embedded PLL _ IP according to the application scene of the antifuse type FPGA; if the embedded PLL _ IP is used, the using mode is determined, and whether the configurable delay is needed to be used or not is determined based on clock network information acquired by programming software, internal layout and wiring information of the antifuse type FPGA and the like. If used, the delay time and delay mode to be configured are determined.
Selecting a PLL _ IP on an IP calling interface of a programmer; selecting and using a delay output state of a programmable delay circuit applied to an embedded PLL _ IP of an antifuse type FPGA on a PLL _ IP interface, specifically selecting a +/-state, namely selecting and controlling a programmable delay submodule circuit of a reference clock input end of the embedded PLL _ IP of the antifuse type FPGA or a programmable delay submodule circuit of a feedback clock input end of the embedded PLL _ IP; selecting delay time of the programmable delay submodule circuit, wherein the configuration mode is a discrete mode, and the precision of adjustable delay time is selected to be t A The adjustable range is 0 to 15 x t A The delay time of (c).
And addressing the corresponding antifuse based on the data code stream by the internal circuit of the antifuse type FPGA, programming and finishing configuration. And after programming is finished, electrifying, determining the input signal of the decoding configuration circuit by the programming state of the corresponding antifuse, and successfully configuring the delay state of the programmable delay submodule circuit. After the chip is powered on by a user, a clock signal is input.
Under normal use of the antifuse-type FPGA, PLL _ IP locks the clock normally.
As shown in fig. 5, the configuration process in the test mode of the programmable delay circuit applied to the embedded PLL _ IP of the antifuse-type FPGA of the present invention specifically includes:
determining a test mode and test contents according to items to be tested of the antifuse-type FPGA, including layout and wiring, IP test, port test and the like; and selecting whether to use the programmable delay circuit applied to the embedded PLL _ IP of the antifuse-type FPGA or not based on the determined test mode and the test content, and if so, determining a delay time configuration mode of the programmable delay submodule circuit.
Based on JTAG protocol, the antifuse F to be tested is tested through a test platform, such as an ADVANTEST 93K test platform or a built-up real-mounted test boardThe PGA sends an instruction and a data code stream to access an internal register chain of the antifuse FPGA to be tested; the internal register chain latch data is used as an input signal of a decoding configuration circuit to configure the delay state of the programmable delay submodule circuit; specifically, based on the configuration code stream, the plus or minus state of programming delay is realized, namely, the programmable delay submodule circuit of the reference clock input end of the embedded PLL _ IP of the antifuse-type FPGA is selectively configured, or the programmable delay submodule circuit of the feedback clock input end of the embedded PLL _ IP is configured; programming delay time of programmable delay submodule circuit, and selecting adjustable delay time precision t in discrete mode A The adjustable range is 0-15 × t A The delay time of (c).
After the test instruction and the test data are sent, the delay state configuration of the programmable delay circuit with the PLL _ IP embedded in the antifuse FPGA is finished; and comparing the test feedback result with the expected result, and repeatedly testing according to the comparison result and the content of the test item.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A programmable delay circuit applied to an anti-fuse FPGA embedded PLL _ IP is characterized by comprising a decoding configuration circuit and two groups of programmable delay sub-module circuits; wherein the content of the first and second substances,
the two groups of programmable delay sub-module circuits have the same circuit structure and different configuration signals; each group of programmable delay submodule circuits respectively comprises a first-stage programmable delay circuit and a second-stage programmable delay circuit, wherein:
the first stage programmable delay circuit is used for coarse precision adjustment of signal delay and comprises a unit delay buffer A, three quadruple delay buffers B and three multiplexers, namely the delay length of the unit delay buffer A is t A The delay length of the quadruple delay buffer B is 4 × t A The first-stage programmable delay circuit can realize 0, 4 × t output A 、8×t A 、12×t A Four delays of different lengths;
the second stage programmable delay circuit is used for fine precision signal delay adjustment and consists of four unit delay buffers A and three multiplexers, namely, the delay length of the unit delay buffer A is t A The second-stage programmable delay circuit can realize 0 and 1 × t output A 、2×t A 、3×t A Four delays of different time lengths;
each group of programmable delay sub-module circuits is formed by connecting a first-stage programmable delay circuit and a second-stage programmable delay circuit in series, and the decoding configuration circuit is programmed to output 4-bit control signals to control the programmable delay sub-module circuits to output delay of 0-15 times t A A long delay time.
2. The programmable delay circuit applied to the PLL _ IP embedded in the anti-fuse FPGA of claim 1, wherein two sets of programmable delay sub-module circuits are respectively designed at the reference clock input and the feedback clock input of the PLL _ IP embedded in the anti-fuse FPGA, and can output-15 to +/-15 times t times of the clock input by programming the decoding configuration circuit A The delay time of length, wherein "-" and "+" are used for distinguishing the position relation of the reference clock signal relative to the feedback clock signal, and "+" is used for configuring the input delay size of the reference clock signal so that the reference clock signal is advanced relative to the feedback clock signal; "-" is used to configure the feedback clock input delay size such that the reference clock signal lags the feedback clock signal.
3. The programmable delay circuit for use in an antifuse-type FPGA with an embedded PLL _ IP as claimed in claim 2, wherein said decode configuration circuit comprises a one bit enable signal and a four bit data input signal, the four bit data input signal coming from an internal register chain of the antifuse-type FPGA whose input signal state is configurable based on JTAG protocol when the antifuse-type FPGA is in test mode; when the antifuse-type FPGA is used in the active mode, the four-bit data input signal comes from the programmed state of the antifuse switch, which is programmed once.
4. The programmable delay circuit of claim 3, wherein in the use mode, the embedded PLL _ IP is invoked by an anti-fuse FPGA specific programmer, and wherein in the programmer interface, the configuration flow of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL _ IP is as follows:
determining a use scene of a PLL _ IP embedded in an antifuse type FPGA;
the programmer selects the circuit information of the programmable delay submodule;
selecting a delayed "±" state;
selecting a delay time length;
the programmer programs an anti-fuse type FPGA;
and powering on for use.
5. The programmable delay circuit applied to the embedded PLL _ IP of the antifuse-type FPGA of claim 4, wherein in the using mode, the configuration flow of the programmable delay circuit applied to the embedded PLL _ IP of the antifuse-type FPGA is specifically as follows:
a user determines whether to use the embedded PLL _ IP according to the application scene of the antifuse type FPGA; if the embedded PLL _ IP is used, determining a use mode, acquiring clock network information and anti-fuse type FPGA internal layout wiring information based on programming software, determining whether a programmable delay circuit applied to the embedded PLL _ IP of the anti-fuse type FPGA needs to be used, and if the programmable delay circuit is used, determining delay time and a delay mode which need to be configured;
selecting a PLL _ IP on an IP calling interface of a programmer; selecting programmable delay on a PLL _ IP interface, selecting a +/-state, namely selecting a programmable delay submodule circuit for configuring a reference clock input end embedded with the PLL _ IP of an antifuse FPGA or a programmable delay submodule circuit for a feedback clock input end embedded with the PLL _ IP; selecting delay time of the programmable delay submodule circuit, and selecting adjustable delay time precision t in a discrete mode in a configuration mode A The adjustable range is 0-15 × t A The delay time of (d);
the configuration information of the programmable delay circuit applied to the anti-fuse FPGA embedded with the PLL _ IP is sent to a chip in a data code stream form through a programming upper computer, and an internal circuit of the anti-fuse FPGA addresses a corresponding anti-fuse based on the data code stream and programs the anti-fuse to complete configuration;
after programming is finished, the power is on, an input signal input by the decoding configuration circuit is determined by the programming state of the corresponding antifuse, and the delay state of the programmable delay circuit applied to the antifuse FPGA embedded PLL _ IP is successfully configured and used by a user.
6. The programmable delay circuit of claim 5, wherein in the test mode, the programmable delay circuit of claim is configured to:
determining a test item of the antifuse-type FPGA;
determining a configuration mode of a programmable delay submodule circuit;
sending test data to the antifuse-type FPGA;
configuring a programmable delay submodule circuit;
the delay state of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL _ IP is successfully configured;
test feedback and repeat tests.
7. The programmable delay circuit applied to the embedded PLL _ IP of the antifuse-type FPGA of claim 6, wherein in a test mode, the configuration flow of the programmable delay circuit applied to the embedded PLL _ IP of the antifuse-type FPGA is specifically as follows:
determining a test mode and test contents according to items to be tested of the antifuse-type FPGA, including layout and wiring, IP test and port test; selecting whether to use a programmable delay circuit applied to an anti-fuse FPGA embedded PLL _ IP or not based on the determined test mode and test contents, and if so, determining a delay time configuration mode of a programmable delay submodule circuit;
based on a JTAG protocol, sending an instruction and a data code stream to the interior of the antifuse type FPGA to be tested through a test platform, and accessing an internal register chain of the antifuse type FPGA to be tested; the latch data of the internal register chain is used as an input signal of a decoding configuration circuit to configure the delay state of the programmable delay submodule circuit;
after the test instruction and the test data are sent, the delay state configuration of the programmable delay circuit with the built-in PLL _ IP of the antifuse type FPGA is finished; and comparing the test feedback result with the expected result, and repeatedly testing according to the comparison result and the content of the test item.
8. The programmable delay circuit of claim 7, wherein the programmable delay circuit of the embedded PLL _ IP of the antifuse-type FPGA is configured in a manner determined by the internal clock net layout wiring delay of the antifuse-type FPGA and the frequency of the input clock and the feedback clock of the embedded PLL _ IP of the antifuse-type FPGA; the output delay of the programmable delay circuit applied to the anti-fuse type FPGA embedded PLL _ IP is static delay, namely after programming, the delay state is fixed in the using process.
9. The programmable delay circuit for embedded PLL _ IP in antifuse-type FPGA of claim 8, wherein the input clock signal of the embedded PLL _ IP in antifuse-type FPGA, i.e. the input signal corresponding to the first set of programmable delay sub-module circuits, is sourced from the external clock, the output clock of the previous PLL _ IP, the input clock CLKxP from the differential I/O;
the feedback clock signal of the PLL _ IP embedded in the anti-fuse FPGA, namely the input signal source corresponding to the second group of programmable delay submodule circuits is the output clock of the PLL _ IP, the clock of a self-clock network after wiring, and the input clock CLKxN from the differential I/O.
10. The programmable delay circuit of claim 9, wherein the power signal applied to the programmable delay circuit of the embedded PLL _ IP of the antifuse-type FPGA is an antifuse-type FPGA core power signal, and the ground signal is a ground signal of the embedded PLL _ IP of the antifuse-type FPGA, and the power-on state is consistent therewith.
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