CN115913179A - Duty ratio correction circuit and storage device - Google Patents
Duty ratio correction circuit and storage device Download PDFInfo
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- CN115913179A CN115913179A CN202110990381.2A CN202110990381A CN115913179A CN 115913179 A CN115913179 A CN 115913179A CN 202110990381 A CN202110990381 A CN 202110990381A CN 115913179 A CN115913179 A CN 115913179A
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Abstract
The application discloses a duty ratio correction circuit and a storage device. The duty cycle correction circuit includes: a delay circuit for receiving an input clock and outputting a delayed clock of the input clock; the sampling circuit is connected with the delay circuit and used for acquiring a phase difference between the input clock and the delay clock and generating a first pulse width signal and a second pulse width signal according to the phase difference; the duty ratio detection circuit is connected with the sampling circuit and is used for acquiring the voltage on the integrating capacitor in the duty ratio detection circuit; and the duty ratio adjusting circuit is respectively connected with the delay circuit and the duty ratio detection circuit and is used for comparing the voltage of the integrating capacitor with the reference voltage when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference between the reference voltage and the accumulated differential pressure and adjusting the time delay of the delay circuit based on the comparison result so as to correct the duty ratio of the output clock corresponding to the input clock. By the mode, the resolution and the accuracy of the duty ratio correction circuit can be improved.
Description
Technical Field
The present disclosure relates to electronic technologies, and in particular, to a duty cycle correction circuit and a memory device.
Background
With the widespread use of computers and various electronic devices, the demand for memory products (such as memories) is increasing. When the clock of the memory is disturbed, the duty ratio of the input clock is greatly changed, and the change of the duty ratio of the input clock of the memory is easy to cause the functional failure of the memory.
To reduce the duty cycle variation of the input clock of the memory, a duty cycle correction circuit (DCC) is usually used to adjust the duty cycle of the input clock.
In a conventional DCC, in order to obtain higher resolution and accuracy, an integration module requires a larger bias current and a smaller integration capacitor, but a comparison module needs to operate under a smaller current and a larger capacitance, so that the resolution and accuracy of the DCC are limited.
Disclosure of Invention
The technical problem that this application mainly solved provides a duty cycle correction circuit and memory device to improve duty cycle correction circuit's resolution ratio and precision.
In order to solve the technical problem, the application adopts a technical scheme that: a duty cycle correction circuit is provided. The duty cycle correction circuit includes: a delay circuit for receiving an input clock and outputting a delayed clock of the input clock; the sampling circuit is connected with the delay circuit and is used for acquiring the phase difference between the input clock and the delay clock and generating a first pulse width signal and a second pulse width signal according to the phase difference; the duty ratio detection circuit is connected with the sampling circuit and is used for acquiring the voltage on an integrating capacitor in the duty ratio detection circuit; and the duty ratio adjusting circuit is respectively connected with the delay circuit and the duty ratio detection circuit and is used for comparing the voltage of the integrating capacitor with the reference voltage when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference between the reference voltage and the accumulated differential pressure, and adjusting the time delay of the delay circuit based on the comparison result so as to correct the duty ratio of the output clock corresponding to the input clock.
In order to solve the above technical problem, another technical solution adopted by the present application is: a memory device is provided. The memory device includes the above-described duty cycle correction circuit.
The beneficial effect of this application is: different from the prior art, the method adopts a sampling circuit to obtain a first pulse width signal and a second pulse width signal which can embody phase difference information of an input clock and a delay clock thereof, obtains the voltage of an integrating capacitor through a duty ratio detection circuit, compares the voltage of the integrating capacitor with a reference voltage by utilizing a duty ratio adjusting circuit when the voltage of the integrating capacitor is less than or equal to an absolute value of a difference value between the reference voltage and an accumulated differential pressure (an accumulated value of the difference value between a discharging voltage of the first pulse width signal to the integrating capacitor and a charging voltage of the second pulse width signal to the integrating capacitor), and adjusts the time delay of the delay circuit based on the comparison to realize the adjustment of the duty ratio of the output clock; compared with the technical scheme that the time delay is adjusted by the comparison result of the voltages of the two integrating capacitors in the prior art, the voltage of the integrating capacitor and the absolute value of the difference between the reference voltage and the accumulated differential pressure are compared, namely a certain voltage threshold value is arranged between the voltage of the integrating capacitor and the reference voltage, so that the voltage fluctuation range of the integrating capacitor in each period is reduced, the duty ratio detection circuit can increase the resolution ratio and the accuracy by adopting larger current and smaller capacitor, and therefore the resolution ratio and the accuracy of the duty ratio correction circuit can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required in the embodiments will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a duty cycle correction circuit according to the present application;
FIG. 2 is a schematic circuit diagram of a duty cycle detection circuit and a duty cycle adjustment circuit in the duty cycle correction circuit of FIG. 1;
FIG. 3 is a signal waveform diagram of the duty cycle correction circuit of the embodiment of FIG. 1;
FIG. 4 is a schematic diagram of another circuit structure of a duty cycle detection circuit and a duty cycle adjustment circuit in another embodiment of the duty cycle correction circuit of the present application;
FIG. 5 is a schematic structural diagram of another embodiment of the duty cycle correction circuit of the present application;
FIG. 6 is a schematic diagram of an embodiment of the memory device of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "first" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The present application first provides a duty cycle correction circuit, as shown in fig. 1 to 3, fig. 1 is a schematic structural diagram of an embodiment of the duty cycle correction circuit of the present application; FIG. 2 is a schematic circuit diagram of a duty cycle detection circuit and a duty cycle adjustment circuit in the duty cycle correction circuit of FIG. 1; fig. 3 is a signal waveform diagram of the duty cycle correction circuit of the embodiment of fig. 1. The duty correction circuit 10 of the present embodiment includes: a delay circuit 110, a sampling circuit 120, a duty cycle detection circuit 130, and a duty cycle adjustment circuit 140; the delay circuit 110 is configured to receive an input clock clk0 and output a delay clock clk180 of the input clock clk 0; the sampling circuit 120 is connected to the delay circuit 110, and configured to obtain a phase difference between the input clock clk0 and the delay clock clk180, and generate a first pulse width signal clkr _ p (i.e., clkr) and a second pulse width signal clkf _ n (clkf _ n is an inverse signal of clkf) according to the phase difference; the duty ratio detection circuit 130 is connected to the sampling circuit 120, and is configured to obtain a voltage VX across an integrating capacitor C in the duty ratio detection circuit 130; the duty cycle adjusting circuit 140 is respectively connected to the delay circuit 110 and the duty cycle detecting circuit 130, and is configured to compare the voltage VX of the integrating capacitor C with a reference voltage Vref (i.e., vref, the voltage at the Y point) when the voltage VX of the integrating capacitor C is less than or equal to an absolute value of a difference between the reference voltage Vref and the accumulated voltage difference VY, and adjust the time delay of the delay circuit 110 based on the comparison result, so as to correct the duty cycle of the output clock corresponding to the input clock clk 0; the accumulated voltage difference VY is an accumulated value of a difference between a discharge voltage of the first pulse width signal clkr _ p to the integration capacitor C and a charge voltage of the second pulse width signal clkf _ n to the integration capacitor C.
Different from the prior art, in the embodiment, the sampling circuit 120 is adopted to obtain the first pulse width signal clkr _ p and the second pulse width signal clkf _ n which can represent the phase difference information between the input clock clk0 and the delay clock clk180 thereof, the voltage of the integrating capacitor C is obtained through the duty ratio detection circuit 130, the voltage VX of the integrating capacitor C is compared with the reference voltage vref by using the duty ratio adjusting circuit 140 when the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference value between the reference voltage vref and the accumulated differential pressure VY, and the time delay of the delay circuit 110 is adjusted based on the comparison result, so as to realize the adjustment of the duty ratio of the output clock; compared with the technical scheme of adjusting the time delay by using the comparison result of the voltages of the two integrating capacitors in the prior art, in this embodiment, the absolute value of the difference between the voltage VX of the integrating capacitor C and the reference voltage vref and the accumulated voltage difference VY is compared, that is, a certain voltage threshold is provided between the voltage VX of the integrating capacitor C and the reference voltage vref, so that the fluctuation range of the voltage VX of the integrating capacitor C in each period can be reduced, the duty cycle detection circuit 130 can increase the resolution and the accuracy by using a larger current and a smaller capacitor, and thus the resolution and the accuracy of the duty cycle correction circuit 10 can be improved.
Specifically, the delay circuit 110 of the present embodiment can delay the input clock by 180 ° phase difference.
Specifically, the sampling circuit 120 samples a rising edge of the input clock clk0 and a subsequent rising edge adjacent to the rising edge in the delayed clock clk180, respectively, and uses a phase difference between the two edges as a pulse width a of the first pulse width signal clkr _ p, and the sampling circuit 120 generates the first pulse width signal clkr _ p with the pulse width a; the sampling circuit 120 samples the rising edge of the delayed clock clk180 and the subsequent rising edge of the input clock clk0 adjacent to the rising edge, and the phase difference between the two is used as the pulse width b of the second pulse width signal clkf _ n, and the sampling circuit 120 generates the second pulse width signal clkf _ n with the pulse width b. The sampling circuit 120 of this embodiment may be a pulse generator.
The duty detection circuit 130 of the present embodiment is configured to amplify a pulse width signal corresponding to the clock phase difference and convert the pulse width signal into an accumulated voltage difference VY.
Optionally, the duty ratio detection circuit 130 of the present embodiment includes: the first input end and the second input end of the integrating circuit 131 are respectively connected to the sampling circuit 120, the first input end of the integrating circuit 131 is connected to the first pulse width signal clkr _ p for discharging the integrating capacitor C, and the second input end of the integrating circuit 131 is connected to the second pulse width signal clkf _ n for charging the integrating capacitor C.
As can be seen from the above analysis, when the duty ratio of the output clock corresponding to the input clock clk0 changes, the phase difference between the input clock clk0 and the delay clock clk180 is greater than or less than 180 °, so that the pulse width a of the first pulse width signal clkr _ p is not equal to the pulse width b of the second pulse width signal clkf _ n, and the time for the first pulse width signal clkr _ p to discharge the integrating capacitor C is different from the time for the second pulse width signal clkf _ n to charge the integrating capacitor C.
With the increase of the charging and discharging times of the integrating capacitor C, the integrating capacitor C will accumulate the charging and discharging differential pressure, i.e. the accumulated differential pressure VY.
Optionally, the duty cycle adjusting circuit 140 of this embodiment includes: a comparator circuit 141 and a logic control circuit 142; the first input end of the comparison circuit 141 is connected to one end of the integration capacitor C, the second input end of the comparison circuit 141 is connected to a reference voltage Vref (i.e., vref), and the comparison circuit is configured to generate a first adjustment signal when the voltage VX of the integration capacitor C is less than or equal to an absolute value of a difference between the reference voltage Vref and the accumulated voltage difference VY, and the voltage VX of the integration capacitor C is less than the reference voltage Vref, and generate a second adjustment signal when the voltage VX of the integration capacitor C is less than or equal to an absolute value of a difference between the reference voltage Vref and the accumulated voltage difference VY, and the voltage VX of the integration capacitor C is greater than the reference voltage Vref; the input end of the logic control circuit 142 is connected to the output end of the comparison circuit 141, and the output end of the logic control circuit 142 is connected to the delay circuit 110, and is configured to generate a control code according to the accumulated voltage difference VY, the number of pulses corresponding to the accumulated voltage difference VY, and the first adjustment signal or the second adjustment signal, and adjust the time delay of the delay circuit 110 according to the control code; and the time delay adjusting direction corresponding to the first adjusting signal is opposite to the time delay adjusting direction corresponding to the second adjusting signal.
As can be seen from the above analysis, the accumulated voltage difference VY between the charging and discharging of the integrating capacitor C and the first and second pulse width signals clkr _ p and clkf _ n with different pulse widths can reflect the change of the duty ratio of the output clock; the accumulated voltage difference VY is related to the number of charge and discharge pulses.
Specifically, the logic control circuit 142 may obtain the differential pressure generated by the single charge and discharge of the integrating capacitor C by comparing the accumulated differential pressure VY with the corresponding pulse number (the pulse number is 8 in fig. 3), where the differential pressure is the difference between the pulse width a of the first pulse width signal clkr _ p and the pulse width b of the second pulse width signal clkf _ n, that is, the difference between the pulse width between the rising edge of the input clock clk0 and the next rising edge adjacent to the rising edge in the delayed clock clk180, and the pulse width between the rising edge of the delayed clock clk180 and the next rising edge adjacent to the rising edge in the input clock clk0, and the logic control circuit 142 may adjust the time delay of the delay circuit 110 by corresponding control codes, that is, the difference between the input pulse clk0 and the delayed pulse 180 makes the width difference zero, that is, the duty ratio of the output clock may be corrected to 50%.
In this embodiment, based on that the pulse width a of the first pulse width signal clkr _ p obtained by the input clock clk0 and the delay clock clk180 is greater than the pulse width b of the second pulse width signal clkf _ n, so that the discharging time of the integrating capacitor C is greater than the charging time, and thus when the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref and the accumulated voltage difference VY, the voltage VX of the integrating capacitor C is less than the reference voltage vref, as shown in fig. 3; at this time, the comparison circuit 141 generates the first adjustment signal to reduce the duty ratio of the output clock to 50%. In another embodiment, the pulse width of the first pulse width signal obtained based on the input clock and the delay clock may be smaller than the pulse width of the second pulse width signal, so that the discharging time of the integrating capacitor is shorter than the charging time, and the voltage VX of the integrating capacitor is greater than the reference voltage when the voltage of the integrating capacitor is smaller than or equal to the absolute value of the difference between the reference voltage and the accumulated voltage difference. At this time, the comparison circuit generates a second adjustment signal to increase the duty ratio of the output clock to 50%. The adjustment direction of the time delay corresponding to the first adjustment signal is opposite to the adjustment direction of the time delay corresponding to the second adjustment signal.
Of course, in other embodiments, other duty cycle clocks may also be corrected using similar methods.
Optionally, the integrating circuit 131 of this embodiment includes: a first switch tube Mp, a second switch tube Mn, a current mirror 132 and an integrating capacitor C; the second switching tube Mn, the current mirror 132 and the first switching tube Mp are sequentially connected in series between the power supply terminal VDD and a ground terminal (not shown), a control terminal of the first switching tube Mp is connected to the sampling circuit 120 for accessing the first pulse width signal clkr _ p, a control terminal of the second switching tube Mn is connected to the sampling circuit 120 for accessing the second pulse width signal clkf _ n, one end of the integrating capacitor C is connected to the other output branch of the current mirror 132, and the other end of the integrating capacitor C is connected to the ground terminal.
Specifically, the input end of the second switching tube Mp is connected to the power supply end VDD, and the output end of the second switching tube Mp is connected to the input branch of the current mirror 132; the input terminal of the first switch Mn is connected to an output branch of the current mirror 132, and the output terminal of the first switch Mn is connected to the ground terminal.
In this embodiment, the second switching tube Mp is placed at the source end of the current mirror 132, so that the influence of the charge injection effect on the integrating capacitor C can be eliminated.
Of course, in other embodiments, other types of switching tubes may be used instead of the first switching tube Mp and the second switching tube Mn in the embodiments, and the connection relationship between elements in the integration circuit may be determined according to the operating properties of the switching tubes, as long as it is ensured that one switching tube charges the integration capacitor and the other switching tube discharges the integration capacitor.
The current of the input branch of the current mirror 132 is equal to the current of the output branch, that is, the transmission ratio of the input current to the output current is equal to 1, so that the current mirror 132 adopted in this embodiment can improve the charging and discharging accuracy of the integrating capacitor C, reduce the fluctuation, and thus can improve the accuracy of the duty ratio correction circuit 10; an output branch of the current mirror 132 is connected with the input end of the second switching tube Mn; the matching performance of the current in (input) and the current in (output) of the current mirror 132 directly determines the accuracy of the duty cycle correction circuit 10.
Optionally, the integrating circuit 131 of the present embodiment further includes: a control end of the third switching tube M is connected to an initialization control signal pre _ n (pre _ n is a reverse signal of lpre _ p), an input end of the third switching tube M is connected to one end of the integrating capacitor C, an output end of the third switching tube M is connected to a reference voltage Vref (i.e., vref), and the third switching tube M is used for controlling an initial voltage of the integrating capacitor C to be the reference voltage Vref.
When the comparing circuit 141 determines that the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref and the accumulated voltage difference VY, the third switching tube M is controlled to operate by initializing the control signal pre _ n to recover the initial voltage of the integrating capacitor C as the reference voltage vref.
It can be known that the voltage VX of the integrating capacitor C per period only contains net error information (duty error), and the variation range of the voltage VX is small, so that a larger current and a smaller capacitor can be used to increase the resolution and accuracy of the duty correction circuit 10.
Optionally, the current mirror 132 of this embodiment adopts a cascode structure, and the integrating circuit 131 of this embodiment further includes: and a negative feedback circuit (not shown) disposed in the input branch of the current mirror 132.
In the embodiment, the current mirror 132 with a cascode structure is adopted, so that the modulation of the fluctuation of the voltage VX of the integrating capacitor C on the current precision can be weakened; and a negative feedback circuit is introduced, so that the output impedance of the current mirror 132 can be further increased, and the accuracy of the current mirror 132 is improved.
In other embodiments, the negative feedback circuit may be further disposed on another output branch of the current mirror, that is, a charge/discharge loop of the integrating capacitor C, so as to increase the output impedance of the current mirror and improve the precision of the current mirror.
Further, the comparison circuit 141 of the present embodiment includes: switching tubes M1-M6 and switching tubes N1 and N2; the input ends of the switching tubes M1-M4 are respectively connected with a power supply end VDD, and the control ends of the switching tubes M1 and M4 are respectively connected with an initialization control signal pre _ n; the output end of the switch tube M1, the output end of the switch tube M2 and the control end of the switch tube M3 are respectively connected with the input end of the switch tube M5 and the control end of the switch tube M6, and are used as the first output end of the comparison circuit 141 to output a first comparison result dec; the output end of the switch tube M3, the output end of the switch tube M4, and the control end of the switch tube M2 are respectively connected to the input end of the switch tube M6 and the input end of the switch tube M5, and serve as a second output end of the comparison circuit 141 to output a second comparison result inc; the output end of the switch tube M5 is connected with the input end of the switch tube N1, and the output end of the switch tube M6 is connected with the input end of the switch tube N2; the control end of the switching tube N1 is connected to one end of the integrating capacitor C, and serves as a first input end of the comparison circuit 141; the control end of the switching tube N2 is connected with a reference voltage vref.
Further, the output terminals of the switching tubes N1 and N2 may also be connected to the ground terminal through two switching tubes (not shown), and the two switching tubes are used to control the comparison circuit 141 to operate or stop operating.
The comparing circuit 141 is configured to compare the voltage VX of the integrating capacitor C with the reference voltage vref when the voltage VX of the integrating capacitor C is less than or equal to an absolute value of a difference between the reference voltage vref and the accumulated voltage difference VY, and correspondingly output a first comparison result dec and a second comparison result inc (whether the phase is advanced or delayed from dec and inc), so that the logic control circuit 142 generates a control code according to the first comparison result dec, the second comparison result inc, the accumulated voltage difference VY, and a pulse number corresponding to the accumulated voltage difference VY.
The present application further provides a duty cycle correction circuit according to another embodiment, as shown in fig. 4, fig. 4 is another circuit structure schematic diagram of a duty cycle detection circuit and a duty cycle adjustment circuit according to another embodiment of the duty cycle correction circuit according to the present application. The duty cycle correction circuit (not shown) of the present embodiment is different from the duty cycle correction circuit 10 of the above embodiment in that: the integration circuit 410 of the present embodiment further includes: a capacitor C1 and a transmission gate TG; one end of the capacitor C1 is connected to the second input terminal of the comparison circuit 141, and the other end of the capacitor C1 is connected to the ground terminal; one end of the transmission gate TG is connected with one end of the capacitor C1, and the other end of the transmission gate TG is connected with a reference voltage Vref (Vref).
In this embodiment, the capacitor C1 and the transmission gate TG are added to the reference signal input end, i.e., the second input end, of the comparison circuit 141, so that the capacitor C1 is symmetrical to the integrating capacitor C, the transmission gate TG is symmetrical to the first switching tube Mp and the second switching tube Mn, and the circuit symmetry can be improved, thereby compensating for the leakage loss of the capacitor, the mismatch of the parasitic capacitance, and the like, and making the common mode influence factors the same as possible.
It should be noted that the integrating circuit and the comparing circuit of the present application can be integrated on the same circuit module, and therefore, the capacitor and the transmission gate can also be divided into the comparing circuit.
In another embodiment, as shown in fig. 5, fig. 5 is a schematic structural diagram of another embodiment of the duty cycle correction circuit of the present application. The duty correction circuit 50 of the present embodiment is different from the duty correction circuit 10 of the above embodiment in that: the duty correction circuit 50 of the present embodiment further includes: the pulse correction circuit 150, the pulse correction circuit 150 is respectively connected to the sampling circuit 120 and the duty cycle detection circuit 130, and is configured to correct the first pulse width signal and the second pulse charging voltage, so that the corrected first pulse width signal discharges the integration capacitor, and the corrected second pulse width voltage charges the integration capacitor.
This application can restrain the influence of the change between pressure, volume, temperature to current mirror 132 through pulse correction circuit 150, further improves current mirror 132's precision.
Optionally, the duty cycle correction circuit 50 of this embodiment further includes a clock gating circuit 160, which is respectively connected to the pulse correction circuit 150 and the duty cycle detection circuit 130; when the duty correction circuit 50 corrects a plurality of loop clocks, one loop clock may be selected by the clock gating circuit 160, and the pulse width signal containing the phase difference information corresponding to the selected loop clock may be transmitted to the duty detection circuit 130 for processing, so as to perform duty correction on the selected loop clock.
In other embodiments, the clock gating circuit and the pulse correction circuit can be selectively used according to actual conditions.
Of course, the duty ratio correction circuit 50 (and the above duty ratio correction circuit) of the present embodiment further includes another circuit 20, which is respectively connected to the input clock and the delay clock, and generates an output clock with a certain duty ratio (which may be 50%) according to the input clock and the delay clock. Reference is made to the prior art with regard to the specific circuit configuration of the further circuit 20.
The present application further proposes a memory device, as shown in fig. 6, fig. 6 is a schematic structural diagram of an embodiment of the memory device of the present application. The memory device 60 of the present embodiment includes a duty correction circuit 61. The structure and the operation principle of the duty cycle correction circuit 61 of this embodiment may refer to the duty cycle correction circuit of the above embodiment, which are not described herein again.
Further, the memory device 60 of the present embodiment may further include an input clock receiving circuit, a DLL delay circuit, an output clock generating circuit, and the like.
The Memory device 60 of the present embodiment is a Dynamic Random Access Memory (DRAM). In other embodiments, the Memory device may also be a Static Random-Access Memory (SRAM) or the like.
Different from the prior art, the method comprises the steps that a sampling circuit is adopted to obtain a first pulse width signal and a second pulse width signal which can represent phase difference information of an input clock and a delay clock of the input clock, the voltage of an integrating capacitor is obtained through a duty ratio detection circuit, the voltage of the integrating capacitor is compared with the reference voltage by utilizing a duty ratio regulation circuit when the voltage of the integrating capacitor is smaller than or equal to the absolute value of the difference between the reference voltage and an accumulated differential pressure (the accumulated value of the difference between the discharging voltage of the first pulse width signal to the integrating capacitor and the charging voltage of the second pulse width signal to the integrating capacitor), and the time delay of a delay circuit is adjusted based on the comparison, so that the duty ratio of the output clock is regulated; compared with the technical scheme that the time delay is adjusted by the comparison result of the voltages of the two integrating capacitors in the prior art, the voltage of the integrating capacitor and the absolute value of the difference between the reference voltage and the accumulated differential pressure are compared, namely a certain voltage threshold value is arranged between the voltage of the integrating capacitor and the reference voltage, so that the voltage fluctuation range of the integrating capacitor in each period is reduced, the duty ratio detection circuit can increase the resolution ratio and the accuracy by adopting larger current and smaller capacitor, and therefore the resolution ratio and the accuracy of the duty ratio correction circuit can be improved.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A duty cycle correction circuit, comprising:
a delay circuit for receiving an input clock and outputting a delayed clock of the input clock;
the sampling circuit is connected with the delay circuit and is used for acquiring the phase difference between the input clock and the delay clock and generating a first pulse width signal and a second pulse width signal according to the phase difference;
the duty ratio detection circuit is connected with the sampling circuit and is used for acquiring the voltage on an integrating capacitor in the duty ratio detection circuit;
the duty ratio adjusting circuit is respectively connected with the delay circuit and the duty ratio detection circuit and is used for comparing the voltage of the integrating capacitor with the reference voltage when the voltage of the integrating capacitor is smaller than or equal to the absolute value of the difference between the reference voltage and the accumulated differential pressure and adjusting the time delay of the delay circuit based on the comparison result so as to correct the duty ratio of the output clock corresponding to the input clock;
the accumulated voltage difference is an accumulated value of a difference value between a discharge voltage of the first pulse width signal to the integrating capacitor and a charge voltage of the second pulse width signal to the integrating capacitor.
2. The duty cycle correction circuit of claim 1, wherein the duty cycle adjustment circuit comprises:
a comparison circuit, a first input end of which is connected with one end of the integration capacitor, a second input end of which is connected with the reference voltage, and is used for generating a first adjusting signal when the voltage of the integration capacitor is less than or equal to the absolute value of the difference value and the voltage of the integration capacitor is less than the reference voltage, and generating a second adjusting signal when the voltage of the integration capacitor is less than or equal to the absolute value of the difference value and the voltage of the integration capacitor is greater than the reference voltage;
the input end of the logic control circuit is connected with the output end of the comparison circuit, the output end of the logic control circuit is connected with the delay circuit, and the logic control circuit is used for generating a control code according to the accumulated differential pressure, the pulse number corresponding to the accumulated differential pressure and the first adjusting signal or the second adjusting signal and adjusting the time delay of the delay circuit according to the control code;
wherein the adjustment direction of the time delay corresponding to the first adjustment signal is opposite to the adjustment direction of the time delay corresponding to the second adjustment signal.
3. The duty cycle correction circuit of claim 2, wherein the duty cycle detection circuit comprises: and a first input end and a second input end of the integrating circuit are respectively connected with the sampling circuit, the first input end is accessed to the first pulse width signal and used for discharging the integrating capacitor, and the second input end is accessed to the second pulse width signal and used for charging the integrating capacitor.
4. The duty cycle correction circuit of claim 3, wherein the integration circuit comprises: the first switch tube, the second switch tube, the current mirror and the integrating capacitor; the second switch tube, the current mirror and the first switch tube are sequentially connected between the power supply end and the grounding end in series, the control end of the first switch tube is connected with the sampling circuit and used for accessing the first pulse width signal, the control end of the second switch tube is connected with the sampling circuit and used for accessing the second pulse width signal, one end of the integrating capacitor is connected with another output branch of the current mirror, and the other end of the integrating capacitor is connected with the grounding end.
5. The duty cycle correction circuit of claim 4, wherein the integration circuit further comprises: and the control end of the third switching tube is connected with an initialization control signal, the input end of the third switching tube is connected with one end of the integrating capacitor, the output end of the third switching tube is connected with the reference voltage, and the third switching tube is used for controlling the initial voltage of the integrating capacitor to be the reference voltage when the voltage of the integrating capacitor is smaller than or equal to the absolute value of the difference value.
6. The duty cycle correction circuit of claim 4, wherein the current mirror is in a cascode configuration, and wherein the integration circuit further comprises: a negative feedback circuit provided on the input branch or the further output branch of the current mirror.
7. The duty cycle correction circuit of claim 4, wherein the input terminal of the second switching tube is connected to the power supply terminal, and the output terminal thereof is connected to the input branch of the current mirror; the input end of the first switch is connected with an output branch of the current mirror, and the output end of the first switch is connected with the grounding end.
8. The duty cycle correction circuit of claim 4, wherein the integration circuit further comprises:
one end of the capacitor is connected with the second input end of the comparison circuit, and the other end of the capacitor is connected with the grounding end;
and one end of the transmission gate is connected with one end of the capacitor, and the other end of the transmission gate is connected to the reference voltage.
9. The duty cycle correction circuit according to any one of claims 1 to 8, further comprising:
and the pulse correction circuit is respectively connected with the sampling circuit and the duty ratio detection circuit and is used for correcting the first pulse width signal and the second pulse width signal so as to discharge the integration capacitor by the corrected first pulse width signal and charge the integration capacitor by the corrected second pulse width signal.
10. A memory device comprising the duty cycle correction circuit of any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110990381.2A CN115913179A (en) | 2021-08-26 | 2021-08-26 | Duty ratio correction circuit and storage device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110990381.2A CN115913179A (en) | 2021-08-26 | 2021-08-26 | Duty ratio correction circuit and storage device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117639735A (en) * | 2024-01-23 | 2024-03-01 | 韬润半导体(无锡)有限公司 | Duty cycle detection circuit and duty cycle adjustment system |
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2021
- 2021-08-26 CN CN202110990381.2A patent/CN115913179A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117639735A (en) * | 2024-01-23 | 2024-03-01 | 韬润半导体(无锡)有限公司 | Duty cycle detection circuit and duty cycle adjustment system |
| CN117639735B (en) * | 2024-01-23 | 2024-03-29 | 韬润半导体(无锡)有限公司 | Duty cycle detection circuit and duty cycle adjustment system |
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