CN115911032A - 具有共享的电隔离的多种器件类型的单片集成 - Google Patents

具有共享的电隔离的多种器件类型的单片集成 Download PDF

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CN115911032A
CN115911032A CN202210979521.0A CN202210979521A CN115911032A CN 115911032 A CN115911032 A CN 115911032A CN 202210979521 A CN202210979521 A CN 202210979521A CN 115911032 A CN115911032 A CN 115911032A
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semiconductor layer
top surface
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semiconductor
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F·赫伯特
H·莱恩维希
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GlobalFoundries US Inc
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GlobalFoundries US Inc
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Abstract

本发明涉及一种具有共享的电隔离的多种器件类型的单片集成。包括集成在半导体衬底上的基于硅的器件和基于III‑V族化合物半导体的器件的结构以及形成这样的结构的方法。该结构包括衬底，该衬底具有器件层、处理衬底以及位于处理衬底和器件层之间的掩埋绝缘体层。该结构包括：第一半导体层，其位于在第一器件区中的器件层上；第二半导体层，其位于在第二器件区中的器件层上。第一半导体层包含III‑V族化合物半导体材料，并且第二半导体层包含硅。第一器件结构包括位于第一半导体层上的栅极结构；以及第二器件结构包括位于第二半导体层中的掺杂区。掺杂区和第二半导体层限定p‑n结。

Description

具有共享的电隔离的多种器件类型的单片集成
技术领域
本发明涉及半导体器件制造和集成电路，更具体地说，涉及包括集成在半导体衬底上的基于硅的器件和基于III-V族化合物半导体的器件的结构以及形成这样结构的方法。
背景技术
高压功率电子器件，例如高电子迁移率晶体管，可以使用III-V族化合物半导体来制造以利用其材料特性，例如大于硅的载流子迁移率的载流子迁移率和比硅宽的带隙。III-V族化合物半导体包括III族元素(铝、镓、铟)和与III族元素组合的V族元素(氮、磷、砷、锑)。在构建器件时用作基础材料的常见III-V族化合物半导体是氮化镓。高电子迁移率晶体管可以包括具有不同带隙的晶体III-V族化合物半导体材料之间的异质结，例如二元氮化镓和三元氮化铝镓之间的异质结。在操作期间，二维电子气在异质结处的界面附近形成，并限定高电子迁移率晶体管的沟道。
在同一芯片上集成高电子迁移率晶体管(例如场效应晶体管或异质结双极型晶体管)与基于硅的器件已被证明具有挑战性。集成可以通过晶圆键合或通过使用具有不同晶体取向部分的混合衬底来实现，这些部分本质上为集成高电子迁移率晶体管与这些其他类型的晶体管的工艺带来了显著的复杂性。
需要包括集成在半导体衬底上的基于硅的器件和基于III-V族化合物半导体的器件的改善的结构以及形成这样结构的方法。
发明内容
在本发明的一个实施例中，一种结构包括衬底，所述衬底具有器件层、处理衬底以及位于所述处理衬底和所述器件层之间的掩埋绝缘体层。所述结构包括：第一半导体层，其位于在第一器件区中的所述器件层上；以及第二半导体层，其位于在第二器件区中的所述器件层上。所述第一半导体层由III-V族化合物半导体材料构成，并且所述第二半导体层由硅构成。第一器件结构包括位于所述第一半导体层上的栅极结构，以及第二器件结构包括位于所述第二半导体层中的掺杂区。所述掺杂区和所述第二半导体层限定p-n结。
在本发明的一个实施例中，一种结构包括衬底，所述衬底包括器件层、处理衬底以及位于所述处理衬底和所述器件层之间的掩埋绝缘体层。所述结构包括：半导体层，其位于在第一器件区中的所述器件层上；第一器件结构，其包括位于所述半导体层上的栅极结构；以及第二器件结构，其包括位于所述器件层的在第二器件区中的掺杂区。所述器件层由单晶硅构成，并且所述半导体层由III-V族化合物半导体材料构成。所述掺杂区和所述器件层限定p-n结。
在本发明的一个实施例中，一种方法包括：提供衬底，所述衬底包括器件层、处理衬底以及位于所述处理衬底和所述器件层之间的掩埋绝缘体层；在所述器件层的第一器件区上形成第一半导体层，以及在所述器件层的第二器件区上形成第二半导体层。所述第一半导体层由III-V族化合物半导体材料构成，并且所述第二半导体层由硅构成。所述方法还包括：形成第一器件结构，所述第一器件结构具有位于所述第一半导体层上的栅极结构；以及形成第二器件结构，所述第二器件结构具有位于所述第二半导体层中的掺杂区。所述掺杂区和所述第二半导体层限定p-n结。
附图说明
包含在本说明书中并构成本说明书一部分的附图示出了本发明的各种实施例，并且与上文给出的本发明的一般描述和下文给出的实施例的详细描述一起用于解释本发明的实施例。在附图中，相同的参考标号在各个视图中指示相同特征。
图1是根据本发明的实施例的初始制造阶段的结构的截面图。
图2是在图1之后的制造阶段的结构的截面图。
图3是根据本发明的替代实施例的结构的截面图。
图4和5是根据本发明的替代实施例的结构的截面图。
图6是根据本发明的替代实施例的结构的截面图。
图7是根据本发明的替代实施例的结构的截面图。
图8是在图7之后的制造阶段的结构的截面图。
图9是根据本发明的替代实施例的结构的截面图。
图10是在图9之后的制造阶段的结构的截面图。
具体实施方式
参考图1并且根据本发明的实施例，提供了衬底10，该衬底10具有包括器件层12、掩埋绝缘体层14和处理衬底16的衬底堆叠。器件层12通过中间掩埋绝缘体层14与处理衬底16分隔开。器件层12具有顶表面18，该顶表面18是平坦的。掩埋绝缘体层14可以由掩埋氧化物(BOX)层构成，该掩埋氧化物(BOX)层由诸如二氧化硅之类的固体电介质材料层构成。
器件层12和处理衬底16可以包含半导体材料，例如单晶硅。在一个实施例中，器件层12的单晶半导体材料可以具有金刚石晶格结构，该金刚石晶格结构具有由密勒指数指定的<111>晶体取向。在一个实施例中，衬底10可以包含具有金刚石晶格结构的单晶硅，该金刚石晶格结构具有<111>晶体取向。对于具有<111>晶体取向的器件层12，(111)晶面平行于器件层12的顶表面18，[111]结晶方向法向于(111)平面。(100)晶轴不位于顶表面18的平面内。在一个实施例中，器件层12可以仅由具有<111>晶体取向的单晶半导体材料(例如，单晶硅)构成。
在器件区22中的器件层12上形成层堆叠20，以及在器件区30中的器件层12上形成半导体层28。沟槽隔离区32形成为与掩埋绝缘体层14协作以将器件区22与器件区30电隔离。
层堆叠20包括半导体层，例如缓冲层24和阻挡层26，其各自包含一个或多个化合物半导体层。缓冲层24和阻挡层26可以使用诸如金属有机化学气相沉积、气相外延或分子束外延之类的外延生长工艺被连续沉积以形成层堆叠。在形成层堆叠20之前，可以在器件层12上形成例如氮化铝的薄成核层。器件层12为外延生长提供种子。在一个实施例中，层堆叠20可以同时在器件区22、30中外延生长，并且通过蚀刻从器件区30被去除，其中器件区22中的层堆叠20被电介质层覆盖和保护。
缓冲层24和阻挡层26可以各自具有是单晶的晶体结构，或者替代地具有基本为单晶的晶体结构，该单晶中存在不同程度的晶体缺陷。缓冲层24可以包含二元III-V族化合物半导体材料，例如氮化镓、氮化铝、氮化铝镓或这些材料的组合，该二元III-V族化合物半导体材料在材料组成、掺杂和/或层厚度方面被定制以适应衬底10的材料与在缓冲层的顶部处包括的沟道层的材料之间的晶格失配、热性能差异和机械性能差异。被设置在缓冲层24上方的阻挡层26可以包含三元III-V族化合物半导体，例如具有15原子百分比的铝至35原子百分比的铝的氮化铝镓，其提供与不同组成的缓冲层24的异质界面。缓冲层24可以包括紧邻阻挡层26的未掺杂的III-V族化合物半导体(例如未掺杂的氮化镓)层。
在一个实施例中，半导体层28可以通过选择性外延生长(SEG)工艺形成，其中半导体材料成核以从器件层12的暴露表面进行外延生长。器件区22中的层堆叠20可以被阻止外延生长的诸如氮化硅层之类的电介质层覆盖和保护。在一个实施例中，在器件区30中的器件层12的部分可以在形成半导体层28之前被掺杂以具有n型导电性。
半导体层28可以由诸如单晶硅之类的单晶半导体材料构成，并且可以在外延生长期间被诸如n型掺杂剂(例如、磷或砷)之类的电活性掺杂剂进行原位掺杂。在替代实施例中，半导体层28可以非选择性地生长，然后用包括从器件区22去除的化学机械抛光进行平坦化。
可以在层堆叠20和半导体层28之间的接合处形成的沟槽隔离区32可以延伸穿过器件层12并进入掩埋绝缘体层14。沟槽隔离区32可以包含通过化学气相沉积被沉积到蚀刻的沟槽中并且然后被抛光和去釉的电介质材料。被包含在沟槽隔离区32中的电介质材料可以包括二氧化硅。
器件区22中的层堆叠20具有顶表面21，器件区30中的半导体层28具有顶表面27。在一个实施例中，层堆叠20的顶表面21可以与半导体层28的顶表面27共面。在一个实施例中，层堆叠20的顶表面21可以与半导体层28的顶表面27基本共面。在一个实施例中，层堆叠20的顶表面21和半导体层28的顶表面27的高度可以相差约100纳米(nm)至约500nm，这可以被认为构成基本共面性。
参考图2，其中相同的参考标号指示图1中的相同特征并且在随后的制造阶段，可以在器件区30中形成器件结构40。在一个实施例中，器件结构40可以是肖特基二极管，其包括掺杂区42、提供与限定阳极的掺杂区42的肖特基接触的硅化物层44、限定阴极的掺杂区46和提供围绕掺杂区42的保护环的掺杂区48。硅化物层44可以通过硅化工艺形成，掺杂区42、46可以通过掩蔽注入形成在半导体层28中，以及掺杂区48可以通过单独的掩蔽注入形成在半导体层28中。掺杂区46可以具有与半导体层28相同的导电类型并且包含比半导体层28高的掺杂剂浓度。掺杂区42被掺杂以具有与半导体层28相反的导电类型以限定p-n结43，以及掺杂区48也被掺杂以具有与半导体层28相反的导电类型以限定p-n结47。例如，如果半导体层28具有n型导电性，则掺杂区42、48可以被掺杂以具有p型导电性。
器件结构38形成在器件区22中。在器件结构38的形成期间，半导体层28可以被电介质层覆盖和保护。在一个实施例中，器件结构38可以是增强模式高电子迁移率晶体管(HEMT)。在一个实施例中，器件结构38可以包括位于层堆叠20上的栅极结构34。栅极结构34可以包括被定位为与阻挡层26接触的栅极36以及被定位在栅极36上和上方的栅极金属层37。栅极36可以由被掺杂的III-V族化合物半导体构成，例如掺杂有镁的p型氮化铝镓或p型氮化镓，以及栅极金属层37可以由一种或多种金属构成，例如铝-铜、氮化钛、钛等。在一个实施例中，栅极36可以通过在形成半导体层28之前或之后图案化在层堆叠20上外延生长的被掺杂的III-V族化合物半导体层来形成。
在代表性实施例中，栅极36位于层堆叠20的顶表面21处的阻挡层26上。在替代实施例中，阻挡层26可以在栅极36下方被减薄，其中在栅极36和减薄的阻挡层26之间施加可选的绝缘体层(例如，氮化硅层)。在一个实施例中，器件结构38可以通过调节阈值电压以使得在栅极36未被偏置时器件结构38被关断来在增强模式(E-模式)下操作。在一个实施例中，器件结构38可以通过调节阈值电压以使得在向栅极36施加负电压时器件结构38被关断，来在耗尽模式(D-模式)下操作。在替代实施例中，可以在器件区22中集成E模式器件结构38和D模式器件结构38的混合。在替代实施例中，诸如肖特基二极管之类的无源器件结构可以被集成到器件区22中。
随后进行中段制程处理和后段制程处理，其包括为位于衬底10上方并连接到器件结构38、40的互连结构形成接触、过孔和布线。
掩埋绝缘体层14将器件结构38和器件结构40与处理衬底16电隔离。关于共享的电隔离，掩埋绝缘体层14位于器件结构38和处理衬底16之间的竖直方向上，并且掩埋绝缘体层14也位于器件结构40和处理衬底16之间的竖直方向上。器件结构38和器件结构40形成在同一器件层12上，其中层堆叠20形成在器件区22中的器件层12上，并且半导体层28也形成在器件区30中的器件层12上。利用仅具有<111>晶体取向的器件层12允许器件结构38、40的集成不需要复杂的制造过程(例如晶圆键合)，或不使用工程化衬底或混合衬底(例如，具有关于器件层的一个或多个晶体取向的SOI衬底)。
在同一器件层12上的器件结构38、40的单片共集成同时提供了低成本构造和具有改善操作参数的高性能器件。与使用诸如氮化镓之类的III-V族化合物半导体材料形成的肖特基二极管相比，作为共集成器件结构40的肖特基二极管表现出低正向电压降和低存储电荷。与氮化镓相比，由关于硅的更小带隙提供的参数改善可在操作期间导致降低的功耗和改善的可靠性。
在替代实施例中，使用半导体层28形成的器件结构40可以是结型二极管，其由于使用半导体层28形成而表现出低泄漏。在替代实施例中，使用半导体层28形成的器件结构40可以是双极结型晶体管或异质结双极型晶体管，其中集电极、发射极和基极竖直或横向布置，并且基极被掺杂以具有p型导电性或n型导电性。在替代实施例中，使用半导体层28形成的器件结构40可以是可控硅整流器。在替代实施例中，器件结构40可以是绝缘栅双极型晶体管。在替代实施例中，器件结构40可以是扩散电阻器。在替代实施例中，器件结构40可以是结型场效应晶体管。在替代实施例中，可以使用半导体层28形成多种不同类型的器件结构40。
参考图3，其中相同的参考标号指示图2中的相同特征并且根据替代实施例，器件结构40可以是横向双极结型晶体管，其中掺杂区42限定发射极，掺杂区46参与限定基极，以及掺杂区48提供围绕发射极的集电极。具有不同掺杂剂浓度的重叠部分的掺杂区42被掺杂以具有与半导体层28相反的导电类型以限定p-n结。例如，如果半导体层28具有n型导电性，则掺杂区42可以被掺杂以具有p型导电性。
参考图4、5，其中相同的参考标号指示图2中的相同特征并且根据替代实施例，可以使用器件区30中的器件层12而不是半导体层28来形成器件结构40。在这种情况下，半导体层28未形成在器件区30中，这样便留下器件层12以用于形成器件结构40。层堆叠20的顶表面21和器件层12的顶表面18的高度可以相差超过500nm。
如图4所示，使用器件区30中的器件层12形成的器件结构40可以是肖特基二极管。如图5所示，使用器件区30中的器件层12形成的器件结构40可以是双极结型晶体管。
参考图6，其中相同的参考标号指示图4中的相同特征并且根据替代实施例，电介质层50可以形成在器件区30中的器件层12上。电介质层50由诸如二氧化硅之类的电介质材料构成，并具有顶表面52。电介质层50的电介质材料可以通过例如化学气相沉积来沉积，然后被平坦化。掺杂区42、46、48可以通过在电介质层50中被图案化并且从顶表面52完全穿透电介质层50到达器件层12的沟槽51而被访问。在替代实施例中，器件结构40可以是双极结型晶体管而不是肖特基二极管。
在一个实施例中，层堆叠20的顶表面21和器件区30中的电介质层50的顶表面52可以共面。在一个实施例中，层堆叠20的顶表面21与器件区30中的电介质层50的顶表面52可以基本共面。在一个实施例中，层堆叠20的顶表面21和器件区30中的电介质层50的顶表面52的高度可以相差约100nm至约500nm，这可以被认为构成基本共面性。
参考图7，其中相同的参考标号指示图1中的相同特征并且根据替代实施例，在形成层堆叠之前，器件区22中的器件层12可以从其原始厚度被减薄。在器件区30中，器件层12保持其原始厚度。在这种情况下，半导体层28未形成在器件区30中，并且器件层12的原始厚度大于层堆叠20的厚度。
在一个实施例中，层堆叠20的顶表面21和器件区30中的器件层12的顶表面18可以共面。在一个实施例中，层堆叠20的顶表面21与器件区30中的器件层12的顶表面18可以基本共面。在一个实施例中，层堆叠20的顶表面21和器件区30中的器件层12的顶表面18的高度可以相差约100nm至约500nm，这可以被认为构成基本共面性。
参考图8，其中相同的参考标号指示图7中的相同特征并且在随后的制造阶段，处理继续以形成器件结构38、40。在器件区30中，器件结构40使用器件层12的半导体材料来形成，该半导体材料可以被掺杂(例如，n-型掺杂)以有利于器件的形成。
参考图9，其中相同的参考标号指示图1中的相同特征并且根据替代实施例，衬底10可以是工程化衬底，其包括由与层堆叠20的材料的热膨胀特性紧密匹配的多晶陶瓷材料构成的处理衬底56。在一个实施例中，处理衬底56可以由与氮化镓的热膨胀特性紧密匹配的多晶氮化铝构成。在一个实施例中，处理衬底56可以由也与氮化镓的热膨胀特性紧密匹配的多晶碳化硅构成。处理衬底56被层堆叠54覆盖，该层堆叠54包括工程化层，例如包含二氧化硅、氮化硅、多晶硅等的层。器件层12位于层堆叠54上。
参考图10，其中相同的参考标号指示图9中的相同特征并且在随后的制造阶段，处理继续以形成层堆叠20，以可选地形成半导体层28，以及形成器件结构38、40。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(例如，作为具有多个未封装芯片的单个晶片)，作为裸芯或以封装形式分发。在后一种情况下，芯片被安装在单个芯片封装(例如，塑料载体，其中引线附接到主板或其他更高层级的载体上)或多个封装(例如，具有表面互连或掩埋互连中的一者或全部两者的陶瓷载体)中。在任一情况下，芯片可以与其它芯片、分立电路元件和/或其它信号处理器件集成，作为中间产品或最终产品的一部分。
本文对通过诸如“大约”、“大致”和“基本上”之类的近似语言修饰的术语的引用不限于所指定的精确值。近似语言可以对应于用于测量值的仪器的精度，并且除非依赖于仪器的精度，否则可以指示所述值的+/-10％。
本文对诸如“竖直”、“水平”等术语的引用是作为示例而不是作为限制来做出的，以建立参考系。如本文所用，术语“水平”被定义为与半导体衬底的常规平面平行的平面，而不管其实际的三维空间取向如何。如刚刚定义的，术语“竖直”和“法向”是指与水平垂直的方向。术语“横向”是指在水平面内的方向。
“连接”或“耦接”到另一特征或与另一特征“连接”或“耦接”的一个特征可以直接地连接或耦接到另一特征或与另一特征连接或耦接，相反，可以存在一个或多个中间特征。如果不存在中间特征，则一个特征可以“间接连接”或“间接耦接”到另一特征或与另一特征“间接连接”或“间接耦接”。如果存在至少一个中间特征，则一个特征可以“间接连接”或“间接耦接”到另一特征或与另一特征“间接连接”或“间接耦接”。“位于另一特征上”或“接触另一特征”的一个特征可以直接位于另一特征上或与另一特征直接接触，或者相反，可以存在一个或多个中间特征。如果不存在中间特征，则一个特征可以“直接位于另一特征上”或“直接接触另一特征”。如果存在至少一个中间特征，则一个特征可以“间接位于另一特征上”或“间接接触另一特征”。
本发明的各种实施例的描述已经出于说明的目的给出，但并非旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中发现的技术的技术改善，或者使本技术领域的其他普通技术人员能够理解本文公开的实施例。

Claims (20)

1.一种结构，包括：
衬底，其包括器件层、处理衬底以及位于所述处理衬底和所述器件层之间的掩埋绝缘体层；
第一半导体层，其位于在第一器件区中的所述器件层上，所述第一半导体层由III-V族化合物半导体材料构成；
第二半导体层，其位于在第二器件区中的所述器件层上，所述第二半导体层由硅构成；
第一器件结构，其包括位于所述第一半导体层上的栅极结构；以及
第二器件结构，其包括位于所述第二半导体层中的掺杂区，所述掺杂区和所述第二半导体层限定p-n结。
2.根据权利要求1所述的结构，其中，所述第一器件结构是高电子迁移率晶体管，并且所述第二器件结构是肖特基二极管。
3.根据权利要求1所述的结构，其中，所述第一器件结构是高电子迁移率晶体管，并且所述第二器件结构是双极结型晶体管。
4.根据权利要求1所述的结构，其中，所述器件层由具有<111>晶体取向的单晶硅构成，并且所述第二半导体层的所述硅是具有<111>晶体取向的单晶。
5.根据权利要求1所述的结构，其中，所述III-V族化合物半导体材料包括氮化镓。
6.根据权利要求1所述的结构，其中，所述第一半导体层具有第一顶表面，所述第二半导体层具有第二顶表面，并且所述第一顶表面与所述第二顶表面基本共面。
7.根据权利要求1所述的结构，其中，所述第一半导体层具有第一顶表面，所述第二半导体层具有第二顶表面，并且所述第一顶表面和所述第二顶表面的高度相差约100纳米至约500纳米。
8.根据权利要求1所述的结构，其中，所述处理衬底由多晶陶瓷材料构成，并且所述掩埋绝缘体层包括多个工程化层。
9.一种结构，包括：
衬底，其包括器件层、处理衬底以及位于所述处理衬底和所述器件层之间的掩埋绝缘体层，所述器件层由单晶硅构成；
半导体层，其位于在第一器件区中的所述器件层上，所述半导体层由III-V族化合物半导体材料构成；
第一器件结构，其包括位于所述半导体层上的栅极结构；以及
第二器件结构，其包括在第二器件区中的所述器件层中的掺杂区，所述掺杂区和所述器件层限定p-n结。
10.根据权利要求9所述的结构，其中，所述第一器件结构是高电子迁移率晶体管，并且所述第二器件结构是肖特基二极管。
11.根据权利要求9所述的结构，其中，所述第一器件结构是高电子迁移率晶体管，并且所述第二器件结构是双极结型晶体管。
12.根据权利要求9所述的结构，其中，所述器件层的所述单晶硅具有<111>晶体取向。
13.根据权利要求9所述的结构，其中，所述III-V族化合物半导体材料包括氮化镓。
14.根据权利要求9所述的结构，其中，所述半导体层具有第一顶表面，并且所述结构还包括：
电介质层，其位于在所述第二器件区中的所述器件层上，所述电介质层具有第二顶表面，所述电介质层包括在所述器件层中的所述掺杂区的位置处从所述第二顶表面延伸到所述器件层的沟槽，并且所述第一顶表面与所述第二顶表面基本共面。
15.根据权利要求9所述的结构，其中，所述半导体层具有第一顶表面，并且所述结构还包括：
电介质层，其位于在所述第二器件区中的所述器件层上，所述电介质层具有第二顶表面，所述电介质层包括在所述器件层中的所述掺杂区的位置处从所述第二顶表面延伸到所述器件层的沟槽，并且所述第一顶表面和所述第二顶表面的高度相差约100纳米至约500纳米。
16.一种方法，包括：
提供衬底，所述衬底包括器件层、处理衬底以及位于所述处理衬底和所述器件层之间的掩埋绝缘体层；
在第一器件区中的所述器件层上形成第一半导体层，其中所述第一半导体层由III-V族化合物半导体材料构成；
在第二器件区中的所述器件层上形成第二半导体层，其中所述第二半导体层由硅构成；
形成第一器件结构，所述第一器件结构包括位于所述第一半导体层上的栅极结构；以及
形成第二器件结构，所述第二器件结构包括位于所述第二半导体层中的掺杂区，其中所述掺杂区和所述第二半导体层限定p-n结。
17.根据权利要求16所述的方法，其中，在所述器件层的所述第一器件区上形成所述第一半导体层包括：
在所述第一器件区和所述第二器件区中外延生长所述第一半导体层；以及
从所述第二器件区去除所述第一半导体层。
18.根据权利要求17所述的方法，其中，在形成所述第二半导体层之前从所述第二器件区去除所述第一半导体层。
19.根据权利要求16所述的方法，其中，所述第一半导体层具有第一顶表面，所述第二半导体层具有第二顶表面，并且所述第一顶表面和所述第二顶表面的高度相差约100纳米至约500纳米。
20.根据权利要求16所述的方法，其中，所述器件层由具有<111>晶体取向的单晶硅构成，并且所述第二半导体层的所述硅是具有<111>晶体取向的单晶。
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