CN115911004A

CN115911004A - Semiconductor device, electronic system and electrostatic discharge protection method for semiconductor device

Info

Publication number: CN115911004A
Application number: CN202210350211.2A
Authority: CN
Inventors: 李俊禄
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2021-08-06
Filing date: 2022-04-02
Publication date: 2023-04-04
Also published as: US11695003B2; US20230042003A1; TW202308116A; TWI803090B; US20230290774A1

Abstract

The present disclosure provides a semiconductor device, an electronic system and an electrostatic discharge protection method of the semiconductor device. The semiconductor chip has a substrate; an operation solder structure disposed on a first surface of the substrate for receiving an operation signal; a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal; and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip has an operative electrical contact coupled to the operative solder structure; a detection electrical contact coupled to the detection solder structure; an electrostatic discharge protection unit coupled to the operation electrical contact point; and a logic circuit coupled to the detection electrical contact point for adjusting the capacitance of the ESD protection unit according to the chip connection signal.

Description

Semiconductor device, electronic system and electrostatic discharge protection method for semiconductor device

Cross-referencing

This application claims priority and benefit from U.S. official application No. 17/396,275, filed on 8/6/2021, the contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a semiconductor device. More particularly, to a semiconductor device having a plurality of esd protection units with adjustable capacitance.

Background

When two objects with different charges come into contact with each other, electrostatic discharge (ESD) occurs. For example, when a pad (pad) of a semiconductor chip contacts a charged object, such as a human body or a circuit board, an electrostatic discharge event occurs. In this case, a strong discharging current is induced on the pad of the semiconductor chip to discharge the charges accumulated in the semiconductor chip or the charged object. In order to protect the components in the semiconductor chip from the intense and intense discharge current, esd protection circuits are usually attached to the pads of the semiconductor chip.

However, esd protection circuits typically include capacitive elements that may distort signals received by the pads. For example, because a signal must charge or discharge the capacitive elements, a rise time and a fall time of the signal will be extended. Furthermore, when the signals have higher frequencies, it becomes more difficult to distinguish the data transmitted by the signals. In addition, in a multi-chip device, such as a memory device including a plurality of stacked Dynamic Random Access Memory (DRAM) chips, the chips of different ranks may be coupled to each other to receive the same signal and operate in parallel. In this case, those signals must charge or discharge the capacitive elements in all the chips coupled together, thereby deteriorating the quality of the signals even more.

The above description of "prior art" merely provides background and does not constitute an admission that the above description of "prior art" discloses the subject matter of the present disclosure, and does not constitute prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that such description is prior art.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor device, which includes a substrate, an operating solder structure, a detecting solder structure, and a first semiconductor chip. The operation solder structure is arranged on a first surface of the substrate and is configured to receive an operation signal. The solder detection structure is disposed on the first surface of the substrate and configured to receive a chip connection signal. The first semiconductor chip is disposed on a second surface of the substrate and includes a first operation electrical contact, a first detection electrical contact, a first electrostatic discharge protection unit, and a first logic circuit. The first operative electrical contact is coupled to the operative solder structure through the substrate. The first sensing electrical contact is coupled to the sensing solder structure through the substrate. The first ESD protection unit is coupled to the first operational electrical contact. The first logic circuit is coupled to the first detection electrical contact point and is configured to adjust a capacitance value of the first electrostatic discharge protection unit according to the first chip connection signal.

In some embodiments, the first semiconductor chip further comprises a memory circuit configured to perform a plurality of operations according to at least the operation signal.

In some embodiments, the first esd protection unit comprises a first esd protection element coupled between the first operative electrical contact and a voltage terminal; a second electrostatic discharge protection device; and a control circuit coupled in series with the second ESD protection device between the first operative electrical contact and the voltage terminal. The voltage terminal is coupled to a ground or a power voltage.

In some embodiments, the control circuit includes a switch, and the first logic circuit is configured to turn on or off the switch to adjust the capacitance of the first esd protection unit.

In some embodiments, the control circuit includes a fuse, and the first logic circuit is configured to blow the fuse to reduce the capacitance of the first esd protection unit.

In some embodiments, the semiconductor device further includes a second semiconductor chip laterally adjacent to the first semiconductor chip and disposed on the second surface of the substrate or stacked on the first semiconductor chip. The second semiconductor chip includes a second operation electrical contact, a second detection electrical contact, a second electrostatic discharge protection unit and a second logic circuit. The second operative electrical contact is coupled to the operative solder structure. The second sensing electrical contact is coupled to the sensing solder structure. The second ESD protection unit is coupled to the second operational electrical contact. The second logic circuit is coupled to the second detection electrical contact point and is configured to adjust a capacitance value of the second electrostatic discharge protection unit according to the chip connection signal.

Another embodiment of the present disclosure provides an electronic system. The electronic system includes a circuit board, a first semiconductor device and a second semiconductor device. The first semiconductor element is coupled to the circuit board and includes a first substrate, a first operation solder structure, a first detection solder structure and a first semiconductor chip. The first operating solder structure is disposed on a first surface of the first substrate and configured to receive a first operating signal. The first detection solder structure is disposed on the first surface of the first substrate and configured to receive a first chip connection signal. The first semiconductor chip is disposed on a second surface of the first substrate and includes a first operation electrical contact, a first detection electrical contact, a first electrostatic discharge protection unit, and a first logic circuit. The first operative electrical contact is coupled to the first operative solder structure. The first detection electrical contact is coupled to the first detection solder structure. The first ESD protection unit is coupled to the first operational electrical contact. The first logic circuit is coupled to the first detection electrical contact point and configured to adjust a capacitance of the first ESD protection unit according to at least the first chip connection signal.

In some embodiments, the first semiconductor device further includes a second semiconductor chip laterally adjacent to the first semiconductor chip and disposed on the second surface of the first substrate or stacked on the first semiconductor substrate. The second semiconductor chip includes a second operation electrical contact, a second detection electrical contact, a second electrostatic discharge protection unit and a second logic circuit. The second operative electrical contact is coupled to the first operative solder structure. The second sensing electrical contact is coupled to the first sensing solder structure. The second ESD protection unit is coupled to the second operational electrical contact. The second logic circuit is coupled to the second detection electrical contact point and is configured to adjust a capacitance value of the second electrostatic discharge protection unit according to the first chip connection signal.

In some embodiments, the electronic system further includes a second semiconductor device coupled to the first semiconductor device via the circuit board. A structure of the second semiconductor element is the same as a structure of the first semiconductor element. The second semiconductor device and the first semiconductor device receive the first operation signal and perform a plurality of operations in parallel accordingly. A third logic circuit of a third semiconductor chip in the second semiconductor device is configured to adjust a capacitance of a third esd protection unit of the third semiconductor chip according to the first chip connection signal.

In some embodiments, the first semiconductor element is disposed on a first surface of the circuit board, and the second semiconductor element is disposed on a second surface of the circuit board; and the first semiconductor element and the second semiconductor element are laterally arranged on the same surface of the circuit board.

In some embodiments, the first semiconductor chip further comprises a memory circuit configured to perform a plurality of operations according to at least the first operation signal.

In some embodiments, the electronic system further comprises a third semiconductor device coupled to the first semiconductor device via the circuit board, wherein the third semiconductor device comprises a memory controller configured to control the memory circuit in the first semiconductor chip and generate the first chip connect signal.

In some embodiments, the first semiconductor element is disposed on a first surface of the circuit board, and the third semiconductor element is disposed on a second surface of the circuit board; or the first semiconductor element and the second semiconductor element are laterally arranged on the same surface of the circuit board.

In some embodiments, the first esd protection unit comprises a first esd protection device, a second esd protection device and a control circuit. The first ESD protection device is coupled between the first electrical contact and a voltage terminal, wherein the voltage terminal is coupled to a ground or a power voltage. The control circuit is connected in series with the second ESD protection device and coupled between the first operational electrical contact and the ground.

Yet another embodiment of the present disclosure provides an electrostatic discharge protection method for a first semiconductor device. The first semiconductor device includes a substrate; an operating solder structure disposed on a first surface of the substrate; and a first semiconductor chip disposed on a second surface of the substrate. The ESD protection method includes forming an ESD protection unit in the first semiconductor chip, wherein the ESD protection unit is coupled between a voltage terminal and an operating electrical contact point of the first semiconductor chip coupled to the operating solder structure via the substrate, and the voltage terminal is coupled to a ground or a power voltage; coupling the first semiconductor element to a circuit board; transmitting an operation signal to the operation solder structure through the substrate; and adjusting the capacitance values of the plurality of electrostatic discharge protection units according to a total number of the plurality of semiconductor chips which transmit the operation signal and operate in parallel with the first semiconductor chip.

In some embodiments, the esd protection unit comprises a plurality of esd protection elements coupled between the operating electrical contact and the voltage terminal, and transmitting the operating signal and adjusting a capacitance of the plurality of esd protection units according to a total number of the plurality of semiconductor chips operating in parallel with the first semiconductor chip, including decoupling at least one esd protection element from the operating electrical contact or the voltage terminal.

In some embodiments, one of the semiconductor chips that transmits the operation signal and operates in parallel with the first semiconductor chip is in the first semiconductor element or in a second semiconductor element coupled to the first semiconductor element via the circuit board.

In some embodiments, the first semiconductor element and the second semiconductor element comprise memory circuits of different ranks (ranks).

Since the semiconductor device, the electronic system and the ESD protection method of the semiconductor device can adjust the capacitance values of the ESD protection units according to the number of the semiconductor devices coupled together to operate in parallel, signal distortion caused by the capacitance values of the ESD protection units can be reduced.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure of the present application may be more fully understood by reference to the following description of embodiments in conjunction with the appended claims, in which like reference numerals refer to like elements.

Fig. 1 is a schematic structural diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 is a circuit diagram illustrating the semiconductor chip of fig. 1 according to an embodiment of the present disclosure.

Fig. 3 is a circuit diagram illustrating a plurality of esd protection units in fig. 2 according to another embodiment of the disclosure.

Fig. 4 is a circuit diagram illustrating an esd protection unit according to another embodiment of the disclosure.

Fig. 5 is a circuit diagram illustrating an esd protection unit according to another embodiment of the disclosure.

Fig. 6 is a circuit diagram illustrating an esd protection unit according to another embodiment of the disclosure.

Fig. 7 is a schematic structural view illustrating a semiconductor device according to another embodiment of the present disclosure.

Fig. 8 is a circuit schematic diagram illustrating a plurality of semiconductor chips in fig. 7 according to an embodiment of the disclosure.

Fig. 9 is a schematic structural diagram illustrating an electronic system according to other embodiments of the present disclosure.

Fig. 10 is a circuit schematic diagram illustrating a plurality of semiconductor chips in fig. 9 according to an embodiment of the present disclosure.

Fig. 11 is a schematic structural diagram illustrating an electronic system according to other embodiments of the present disclosure.

Fig. 12 is a flow chart illustrating a method for esd protection of a semiconductor device according to an embodiment of the present disclosure.

Description of the reference numerals:

6: electronic system

7: electronic system

10: semiconductor device with a plurality of transistors

12: substrate

14A1 to 14AN: operation solder structure

16A1 to 16AM: solder detecting structure

50: semiconductor device with a plurality of semiconductor chips

52: substrate

54A1 to 54AN: operation solder structure

56A1 to 56AM: solder detecting structure

60A: first semiconductor element

60B: second semiconductor element

60C: third semiconductor element

62A: a first substrate

62B: second substrate

64A1 to 64AN: first operation solder structure

64B1 to 64BN: second operation solder structure

66A1 to 66AM: first detection solder structure

66B1 to 66BM: second detection solder structure

100: semiconductor chip

110A1 to 110AN: operating electrical contact

120: memory circuit

130A1 to 130AN: electrostatic discharge protection unit

130B1 to 130BN: electrostatic discharge protection unit

132A: first electrostatic discharge protection element

132B: first electrostatic discharge protection element

134A: second electrostatic discharge protection element

134B: second electrostatic discharge protection element

136A: control circuit

136B: control circuit

140A1 to 140AM: detecting electrical contacts

150: logic circuit

210: operating electrical contacts

230: electrostatic discharge protection unit

232: first electrostatic discharge protection element

234: second electrostatic discharge protection element

236: first control circuit

238: second control circuit

310: operating electrical contact

330: electrostatic discharge protection unit

332: electrostatic discharge protection element

336: control circuit

410: operating electrical contacts

430: electrostatic discharge protection unit

432: electrostatic discharge protection element

436: control circuit

500A: first semiconductor chip

500B: second semiconductor chip

510A1 to 510AN: first operation electrical contact

510B1 to 510BN: second operation electrical contact

520A: first memory circuit

520B: second memory circuit

530A1 to 530AN: a first electrostatic discharge protection unit

530B1 to 530BN: a first electrostatic discharge protection unit

540A1 to 540AN: the first detection electrical contact point

540B1 to 540BM: the second detection electrical contact

550A: first logic circuit

550B: second logic circuit

600A: first semiconductor chip

600B: second semiconductor chip

600C: third semiconductor chip

610A1 to 610AN: operating electrical contact

610B1 to 610BN: operating electrical contact

620A: memory circuit

620B: memory circuit

640A1 to 640AM: detecting electrical contacts

640B1 to 640BM: detecting electrical contacts

650A: logic circuit

650B: logic circuit

800: electrostatic discharge protection method

A1: first surface

A2: second surface

B1: circuit board

CL: inner conductive layer

D1A: diode with a high-voltage source

D1B: diode with a high-voltage source

D2A: diode with a high-voltage source

D2B: diode with a high-voltage source

F1: fuse wire

GND: ground connection

MC1: memory controller

S810: step (ii) of

S820: step (ii) of

S830: step (ii) of

S840: step (ii) of

SIG _CC1 ～SIG _CCM : chip connection signal

SIG _OP1 ～SIG _OPN : operating signal

SW1A: switch with a switch body

SW1B: switch with a switch body

V1: through-silicon via

VDD: supply voltage

VT: voltage terminal

Detailed Description

Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are merely illustrative and are not intended to limit the scope of the present disclosure. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed intermediate the first and second features such that the first and second features may not be in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. These repetitions are for simplicity and clarity and do not, in themselves, represent a particular relationship between the various embodiments and/or configurations discussed, unless specifically stated in the context.

Furthermore, for ease of description, spatially relative terms such as "under", "lower", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

It will be understood that when an element is formed on, connected to, and/or coupled to another element, it can include embodiments in which the elements are formed in direct contact, and can also include embodiments in which additional elements are formed between the elements such that the elements are not in direct contact.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

Unless otherwise indicated in the context, when representing orientation (orientation), layout (layout), location (location), shape (shapes), size (sizes), quantity (amounts), or other measurements (measures), then terms (terms), such as "same", "equal", "flat", or "coplanar", as used herein, are not necessarily meant to refer to exactly the same orientation, layout, location, shape, size, quantity, or other measurement, but are meant to include, within acceptable differences, more or less the exact same orientation, layout, location, shape, size, quantity, or other measurement, which may occur, for example, as a result of manufacturing processes. The term "substantially" may be used herein to convey this meaning. Such as, for example, substantially identical (substitionally the same), substantially equal (substitionally equivalent), or substantially flat (substitional planar), exactly identical, equal, or flat, or they may be identical, equal, or flat within acceptable differences that may occur, for example, as a result of a manufacturing process.

In the present disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics (semiconductor characteristics), and an electro-optical device (electro-optical device), a light-emitting display device (light-emitting display device), a semiconductor circuit (semiconductor circuit), and an electronic device (electronic device) are included in the scope of the semiconductor device.

Fig. 1 is a schematic structural diagram illustrating a semiconductor device 10 according to an embodiment of the present disclosure. The semiconductor device 10 includes a substrate 12, operating solder structures 14A 1-14 AN, detecting solder structures 16A 1-16 AM, and a semiconductor chip 100, where N and M are positive integers. In some embodiments, N and M may be 1, and the semiconductor device 10 may include one operating solder structure 14A1 and one detecting solder structure 16A1. The operating solder structures 14A 1-14 AN may receive AN operating signal SIG _OP1 ～SIG _OPN And detects that solder structures 16A 1-16 AM can receive chip connection signal SIG _CC1 ～SIG _CCM 。

As shown in fig. 1, the operating solder structures 14 A1-14 AN and the detecting solder structures 16 A1-16 AM are disposed on a first surface A1 of the substrate 12, and the semiconductor chip 100 is disposed on a second surface A2 of the substrate 12. In the present embodiment, the substrate 12 includes a plurality of inner conductive layers CL (or a plurality of redistribution layers) to couple the semiconductor chip 100 to the operation solder structures 14A1 to 14AN and the detection solder structures 16A1 to 16AM, so that the semiconductor chip 100 can receive the operation signal SIG for each corresponding operation _OP1 ～SIG _OPN And chip connection signal SIG _CC1 ～SIG _CCM . That is, the substrate 12 can be a package carrier, and the operation solder structures 14A 1-14 AN and the detection solder structures 16A 1-16 AM can be solder bumps (solder bumps)) Solder balls (solder balls) or other types of solder structures, so that the semiconductor element 10 can be mounted to a printed circuit board by soldering (soldering).

Fig. 2 is a circuit diagram illustrating the semiconductor chip 100 in fig. 1 according to an embodiment of the disclosure. The semiconductor chip 100 includes operational contacts 110A 1-110 AN, a memory circuit 120, ESD protection units 130A 1-130 AN and 130B 1-130 BN, sense contacts 140A 1-140 AM, and a logic circuit 150. In some embodiments, N and M may be positive integers, such as 4, 6, or 8. However, the present disclosure is not limited thereto. In some embodiments, N and M may be 1. In this example, the semiconductor chip 100 includes an operation electrical contact 110A1, an esd protection unit 130B1, and a detection electrical contact 140A1.

The operation electrical contacts 110A1 to 110AN and the detection electrical contacts 140A1 to 140AM may be pins (pins), pads (solder pads), micro bumps (micro bumps), or other types of contacts for external connection. In addition, as shown in fig. 1, each of the operative electrical contacts 110 A1-110 AN may be coupled to a corresponding one of the operative solder structures 14 A1-14 AN via the substrate 12 to receive AN operation signal, and each of the sensing electrical contacts 140 A1-140 AM may be coupled to a corresponding one of the sensing solder structures 16 A1-16 AM via the substrate 120 to receive a chip connect signal.

The memory circuit 120 can perform a plurality of operations according to the signals received by the operational electrical contacts 110A 1-110 AN. For example, the memory circuit 120 may be a Dynamic Random Access Memory (DRAM) circuit. In this example, the operational electrical contacts 110A 1-110 AN may receive a plurality of read/write commands and a plurality of addresses or data according to the commands, and the memory circuit 120 may perform a plurality of read operations or a plurality of write operations according to the commands and transmit the required data accordingly.

Since the operational electrical contacts 110A 1-110 AN are used for external connection, the ESD protection units 130A 1-130 AN and 130B 1-130 BN are coupled to the operational electrical contacts 110A 1-110 AN to provide a plurality of discharge paths at the electrical contacts 110A 1-110 AN, thereby preventing the discharge current from damaging the memory circuit 120. As shown in FIG. 2, each of the ESD protection units 130A 1-130 AN is coupled to a corresponding one of the operational electrical contacts 110A 1-110 AN and the ground GND, and each of the ESD protection units 130B 1-130 BN is coupled to a corresponding one of the operational electrical contacts 110A 1-110 AN and the power voltage VDD. For example, the esd protection unit 130AN is coupled between the operational electrical contact 110AN and the ground GND, and the esd protection unit 130BN is coupled between the operational electrical contact 110AN and the power voltage VDD. However, the disclosure is not so limited. In some embodiments, the semiconductor chip 100 may omit some of the ESD protection units 130A 1-130 AN and 130B 1-130 BN according to the system requirements. For example, the semiconductor chip 100 may omit the ESD protection units 130A 1-130 AN, the ESD protection units 130B 1-130 BN, or omit some of the ESD protection units 130A 1-130 AN and some of the ESD protection units 130B 1-130 BN.

Since the ESD protection units 130A 1-130 AN and 130B 1-13 BN are capacitive, the operation signal SIG received by the operation electrical contacts 110A 1-110 AN is detected before the memory circuit 120 can correctly sense the signals _OP1 ～SIC _OPN It is necessary to charge or discharge the equivalent capacitors or the parasitic capacitors of the electrostatic discharge protection units 130A1 to 130AN and 130B1 to 130BN. That is, the plurality of signals are distorted (distorted) due to the capacitance values of the esd protection units 130A1 to 130AN and 130B1 to 130BN. Furthermore, in some embodiments, the semiconductor chip 100 may be coupled to other semiconductor chips and may receive the same signals as those of the semiconductor chips to perform the operations in parallel. For example, if the semiconductor chip 100 and other semiconductor chips (e.g., other semiconductor chips disposed in a semiconductor device or other semiconductor chips disposed in other semiconductor devices not shown in fig. 1) correspond to different ranks of the same memory systemThen the semiconductor chip 100 and those semiconductor chips receive the same signal and perform a plurality of read/write operations in parallel. In this case, the signals transmitted to the electrical contacts of the semiconductor chip 100 and other semiconductor chips will have to charge the equivalent capacitors of the esd protection units of all semiconductor chips. Therefore, the distortion of the plurality of signals becomes more serious.

To mitigate this distortion, the semiconductor chip 100 may receive the plurality of chip connection signals SIG via the sensing electrical contacts 140A 1-104 AM when the semiconductor chip 100 is coupled to other semiconductor chips _CC1 ～SIG _CCM So that the semiconductor chip 100 can be informed of the presence of other connected chips. Therefore, the logic circuit 150 coupled to the detecting electrical contacts 140A 1-140 AM can be based on the plurality of chip connection signals SIG received by the detecting electrical contacts 140A 1-140 AM _CC1 ～SIG _CCM The capacitance values of the ESD protection units 1301-130N are adjusted. That is, the logic circuit 150 can be connected to the plurality of chip connection signals SIG _CC1 ～SIG _CCM The number of the semiconductor chips coupled to the semiconductor chip 100 is known, and the capacitance values of the ESD protection elements 130A 1-130 AN are adjusted according to the number of the semiconductor chips coupled to the semiconductor chip 100. For example, in some embodiments, the signal may be used as M binary bits to indicate the number of semiconductor chips coupled to the semiconductor chip 100, and the logic circuit 150 may decode the chip connection signal SIG _CC1 ～SIG _CCM The number of the semiconductor chips is obtained, and the ESD protection units 130A 1-130 AN and 130B 1-130 BN are adjusted accordingly.

Fig. 3 is a circuit diagram illustrating the esd protection units 130A1 and 130B1 according to an embodiment of the disclosure. In the present embodiment, the esd protection units 130A1 to 130AN and 130B1 to 130BN may have the same structure. As shown in fig. 3, the esd protection unit 130A1 includes a first esd protection device 132A, a second esd protection device 134A and a control circuit 136A.

The first esd protection element 132A is coupled between the operational electrical contact 110A1 and the ground GND, and the second esd protection element 134A is coupled between the operational electrical contact 110A1 and the ground GND. As shown in fig. 3, the first esd protection element 132A has a diode D1A. The diode D1A has an anode coupled to the ground GND and a cathode coupled to the operating electrical contact 110A1. Similarly, the second esd protection device 134A also has a diode D2A having an anode coupled to the ground GND and a cathode coupled to the operative electrical contact 110A1.

In some embodiments, the first esd protection element 132A has a first capacitance value, and the second esd protection element 134A has a second capacitance value. Since the first esd protection device 132A and the second esd protection device 134A are coupled in parallel between the operative electrical contact 110A1 and the ground GND, an equivalent capacitance (equivalent capacitance) of the esd protection unit 130A1 is approximately a sum of a first capacitance of the first esd protection device 132A and a second capacitance of the second esd protection device 134A. In the present embodiment, in order to allow the logic circuit 150 to adjust the capacitance of the esd protection unit 130A1, the control circuit 136A may be coupled in series between the second esd protection element 134A and the operative electrical contact 110A1 and the ground GND. As shown in fig. 3, the control circuit 136A includes a switch SW1A. In this case, the logic circuit 150 may close the switch SW1A to disconnect the coupling of the second esd protection element 134A from the operational electrical contact 110A1 or the ground GND, so that the second esd protection element 134A is no longer used to provide a plurality of discharge paths between the operational electrical contact 110A1 and the ground GND, and the capacitance of the first esd protection unit 130A1 is reduced. That is, by turning on or off the switch SW1A, the logic circuit 150 can adjust the capacitance of the first esd protection unit 130A1 according to the system requirement.

Similarly, the esd protection unit 130B1 has a first esd protection device 132B, a second esd protection device 134B and a control circuit 136B. The first ESD protection device 132B is coupled between the operational electrical contact 110A1 and the power voltage VDD, and the second ESD protection device 134B is coupled in series with the control circuit 136B between the operational electrical contact 110A1 and the power voltage VDD. As shown in fig. 3, the first esd protection device 132B has a diode D1B, and the second esd protection device 134A. Anodes of the diodes D1 and D2 are coupled to the operative electrical contact 110A1, and cathodes of the diodes D1 and D2 are coupled to the power voltage VDD. That is, the

esd protection devices

132B and 134B may be used to provide a discharge path between the operational electrical contact 110A1 and the power supply voltage VDD. Furthermore, the logic circuit 150 can turn on or off the switch SW1B of the control circuit 136B according to the system requirement to adjust the capacitance of the esd protection unit 130B1.

In some embodiments, the diodes D1A and D1B may have the same size as the diodes D2A and D2B in the esd protection units 130A1 and 130B1. In this case, the first capacitance of the first esd protection device 132A may be substantially equal to the second capacitance of the second esd protection device 134A. However, the present disclosure is not so limited. In some other embodiments, the diodes D1A and D2A may have different sizes, and the first capacitance of the first ESD protection device 132A may be different from the second capacitance of the second ESD protection device 134A. Furthermore, in some other embodiments, the first

esd protection elements

132A, 134A, 132B, 134B may include other types of elements, such as capacitors, resistors and/or transistors.

Fig. 4 is a circuit diagram illustrating an esd protection unit 230 according to another embodiment of the disclosure. In some embodiments, the ESD protection units 230 can be used to replace the ESD protection units 130A 1-130 AN and 130B 1-130 BN in the semiconductor chip 100. As shown in fig. 4, the esd protection unit 230 comprises a first esd protection device 232, a second esd protection device 234, a first control circuit 236 and a second control circuit 238. The first control circuit 236 is coupled in series to the first esd protection device 232 between an operational electrical contact 210 and a voltage terminal VT. In some embodiments, the voltage terminal VT may be coupled to ground GND or to a supply voltage VDD. The second control circuit 238 is coupled in series with the second esd protection device 234 between the operational electrical contact 210 and the voltage terminal VT. In addition, the capacitance of the first esd protection device 232 and the capacitance of the second esd protection device 234 may be different. In the case where each of the esd protection units 130A1 to 130AN and 130B1 to 130BN is replaced by the esd protection unit 230, the manufacturer may decide to turn off the switch SW1 of the first control circuit 236 or the switch SW2 of the second control circuit 238 according to the requirement to provide the esd protection with the desired capacitance. In some embodiments, the esd protection unit 230 may further include more esd protection elements and control circuits to provide more capacitance choices.

Fig. 5 is a schematic circuit diagram illustrating an esd protection unit 330 according to another embodiment of the disclosure. In the present embodiment, the electrostatic discharge protection unit 330 may be used to implement the electrostatic discharge protection units 130A1 to 130AN and 130B1 to 130BN of the semiconductor chip 100. As shown in fig. 5, the esd protection unit 330 includes a plurality of esd protection elements 332 and a plurality of control circuits 336. Each esd protection device 332 is coupled in series with a control circuit 336 between the operational electrical contact 310 and the voltage terminal VT. In this case, the esd protection unit 330 can be adjusted to have different capacitance values by turning on different numbers of switches SW of the control circuits 336. That is, by having more esd protection devices 332 and control circuits 336, it allows the esd protection unit 330 to provide more choices of different capacitance values.

In some embodiments, the control circuit may include a switch that may be opened or closed. However, the disclosure is not so limited. In some embodiments, the control circuit may include a plurality of fuses. Fig. 6 is a circuit diagram illustrating an esd protection unit 430 according to another embodiment of the disclosure. In the present embodiment, the electrostatic discharge protection units 430 may be used to implement the electrostatic discharge protection units 130A1 to 130AN and 130B1 to 130BN of the semiconductor chip 100. As shown in fig. 6, the esd protection unit 430 includes a plurality of esd protection elements 432 and a plurality of control circuits 436. Each esd protection device 432 is coupled in series with a control circuit 436 between the operational electrical contact 410 and the voltage terminal VT. In this example, the esd protection units 430 can be adjusted to have different capacitance values by blowing different numbers of fuses F1 of the plurality of control circuits 436. In some embodiments, the semiconductor chip 100 may further include other circuits or elements (not shown in fig. 6) to control the fuses F1 of the control circuits 436, so that the fuses F1 can be blown without damaging other elements in the semiconductor chip 100.

Fig. 7 is a schematic structural diagram illustrating a semiconductor device 50 according to an embodiment of the disclosure. The semiconductor device 50 includes a substrate 52, operating solder structures 54 A1-54 AN, detecting solder structures 56 A1-56 AM, a first semiconductor chip 500A, and a second semiconductor chip 500B. Operative solder structures 54A 1-54 AN may receive operative signal SIG _OP1 ～SIG _OPN And the detection solder structures 56A 1-56 AM can receive the chip connection signal SIG _CC1 ～SIG _CCM . In addition, the first operative electrical contacts 510A 1-510 AN of the first semiconductor chip 500A and the second operative electrical contacts 510B 1-510 BN of the second semiconductor chip 500B may be coupled to the operative solder structures 54A 1-54 AN to receive the operative signal SIG _OP1 ～SIG _OPN . Furthermore, the first sensing electrical contacts 540A 1-540 AM of the first semiconductor chip 500A and the second sensing electrical contacts 540B 1-540 BM of the second semiconductor chip 500B may be coupled to the sensing solder structures 56A 1-56 AM to receive the chip connect signal SIG _CC1 ～SIG _CCM 。

Further, as shown in fig. 7, a first semiconductor chip 500A is disposed on the base 52, and a second semiconductor chip 500B is stacked on the first semiconductor chip 500A. In the present embodiment, each of the second operation esd protection units 530B1 to 530BN may be coupled in a corresponding one of the second operation electrical contacts 510A1 to 510AN through a Through Silicon Via (TSV) V1. However, the present disclosure is not so limited. For example, in some other embodiments, the second semiconductor chip 500B may be stacked on the first semiconductor chip 500A without covering the first operational electrical contacts 510A 1-510 AN, so the second operational electrical contacts 510B 1-510 BN may be coupled to the first operational electrical contacts 510A 1-510 AN by wire bonding (wire bonding). However, the first semiconductor chip 500A and the second semiconductor chip 500B are stacked, and the disclosure is not limited thereto. In some other embodiments, the first semiconductor chip 500A and the second semiconductor chip 500B may be disposed laterally adjacent to each other on the same surface of a substrate.

Fig. 8 is a circuit diagram illustrating a semiconductor chip 500A and a semiconductor chip 500B according to an embodiment of the disclosure. In the present embodiment, the

semiconductor chips

500A, 500B may have the same structure. For example, as shown in fig. 8, the first semiconductor chip 500A includes first operation electrical contacts 510A1 to 510AN, a first memory circuit 520A, first esd protection units 530A1 to 530AN, first detection electrical contacts 540A1 to 540AN, and a first logic circuit 550A. Moreover, the second semiconductor chip 500B includes second operation electrical contacts 510B 1-510 BN, a second memory circuit 520B, second ESD protection units 530B 1-530 BN, second sensing electrical contacts 540B 1-540 BM and a second logic circuit 550B.

In the present embodiment, the semiconductor device 50 can be a memory device, and the first memory circuit 520A and the second memory circuit 520B can be DRAM circuits, which are combined to provide a wider bandwidth and a larger memory space for the semiconductor device 50. In this example, the first operative electrical contacts 510A 1-510 AN and the second operative electrical contacts 510B 1-510 BN may be used to receive the plurality of identical operative signals SIG _OP1 ～SIG _OPN The

memory circuits

520A and 520B can be operated according to an operation signal SIG _OP1 ～SIG _OPN But operate in parallel. In addition, since the first ESD protection unit 530A1 and the second ESD protection unit 530B1 are capacitive, the signal SIG _OP1 The signal SIG required to be sensed by the first memory circuit 520A and the second memory circuit 520B _OP1 Before the actual voltage of (3), signal SIG _OP1 The equivalent electric currents of the first ESD protection unit 530A1 and the second ESD protection unit 530B1 are requiredThe or each parasitic capacitor is charged. Therefore, the signal SIG is generated by the capacitance values of the first ESD protection unit 530A1 and the second ESD protection unit 530B1 _OP1 Will be distorted (distorted).

To mitigate signal SIG _OP1 The capacitance of the first ESD protection unit 530A1 and the capacitance of the second ESD protection unit 530B1 can be adjusted. For example, the first esd protection unit 530A1 and the second esd protection unit 530B1 may have the same structure as the esd protection unit 130A1 shown in fig. 3. In this example, the capacitance of each of the first ESD protection unit 530A1 and the second ESD protection unit 530B1 can be reduced because the logic circuit 550A can turn off the switch in the first ESD protection unit 530A1 and the logic circuit 550B can turn off the switch in the second ESD protection unit 530B 1. In some embodiments, the chip connect signal SIG _CC1 ～SIG _CCM Logic circuits 520A, 520B operable to inform the total number of the plurality of semiconductor chips coupled together to operate in parallel. Due to the operation signal SIG _OP1 ～SIG _OPN Is associated with the total number of the plurality of semiconductor chips coupled together to operate in parallel, the

logic circuits

520A, 520B may depend on the chip connection signal SIG _CC1 ～SIG _CCM The capacitance values of the ESD protection units 530A 1-530 AN and 530B 1-530 BN are adjusted.

Furthermore, the disclosure is not limited to the first ESD protection units 530A 1-530 AN and the second ESD protection units 530B 1-530 BN being implemented by the ESD protection unit 130A1 shown in FIG. 3. In some other embodiments, the esd protection units 230 shown in fig. 4, 330 shown in fig. 5, or 430 shown in fig. 6 may be adopted to implement the first esd protection units 530A1 to 530AN and the second esd protection units 530B1 to 530BN according to system requirements. Furthermore, in order to provide a plurality of discharge paths to the ground GND and the power voltage VDD, the first semiconductor chip 500A and the second semiconductor chip 500B may include more esd protection units, such that each of the electrical contacts 510A 1-510 AN and 510B 1-510 BN may be protected by two esd protection units, one coupled to the ground GND and the other coupled to the power voltage VDD, which is similar to the semiconductor chip 100 shown in fig. 2.

In some embodiments, the semiconductor device 50 may include more semiconductor chips than the

semiconductor chips

500A and 500B according to system requirements. Also, in some embodiments, different semiconductor elements may be coupled together such that the plurality of semiconductor chips in different semiconductor elements may receive the same operating signal and operate in parallel.

Fig. 9 is a schematic structural diagram illustrating an electronic system 6 according to other embodiments of the present disclosure. The electronic system 6 includes a circuit board B1, a first semiconductor device 60A and a second semiconductor device 60B. The second semiconductor element 60B may be coupled to the first semiconductor element 60A via a circuit board B1. As shown in fig. 9, the first semiconductor element 60A is disposed on a first surface of the circuit board B1, and the second semiconductor element 60B is disposed on a second surface of the circuit board B1. That is, the first semiconductor element 60A and the second semiconductor element 60B may be mounted to the circuit board B1 in a back-to-back (back-to-back) method. However, the disclosure is not so limited. In some embodiments, the first semiconductor element 60A and the second semiconductor element 60B may be laterally disposed on the same surface of the circuit board B1.

In the present embodiment, the first semiconductor element 60A and the second semiconductor element 60B may have the same structure. For example, the

semiconductor devices

60A and 60B may be implemented using the semiconductor device 10. For example, the first semiconductor device 60A includes a first substrate 62A, first operating solder structures 64A1 to 64AN, first detecting solder structures 66A1 to 66AM, and a first semiconductor chip 600A. The first operating solder structures 64A1 to 64AN and the first detecting solder structures 66A1 to 66AM are disposed on a first surface of the first substrate 62A, and the first semiconductor chip 600A is disposed on a second surface of the first substrate 62A. Moreover, the second semiconductor element 60B includes a second substrate 62B, second handle solder structures 64B1 to 64BN, second sensing solder structures 66B1 to 66BM, and a second semiconductor chip 600B. The second handling solder structures 64B1 to 64BN and the second detecting solder structures 66B1 to 66BM are disposed on a first surface of the second substrate 62B, and the second semiconductor chip 600B is disposed on a second surface of the second substrate 62B.

In the present embodiment, each of the first operating solder structures 64A 1-64 AN may be coupled to a corresponding one of the second operating solder structures 64B 1-64 BN to receive the same operating signal SIG _OP1 ～SIG _OPN Accordingly, the circuits in the first semiconductor device 60A and the second semiconductor device 60B can perform a plurality of operations in parallel. Fig. 10 is a circuit schematic diagram illustrating a semiconductor chip 600A in the first semiconductor element 60A and a semiconductor chip 600B in the second semiconductor element 60B of the present disclosure. In the present embodiment, the

semiconductor chips

600A and 600B have the same structure as the semiconductor chip 500A shown in fig. 8. In this example, operative electrical contacts 610A 1-610 AN of semiconductor chip 600A are coupled to operative electrical contacts 610B 1-610 BN of semiconductor chip 600B via operative solder structures 64A 1-64 AN and 64B 1-64 BN, respectively, such that

semiconductor chips

600A and 600B may receive the same operative signal SIG _OP1 ～SIG _OPN . Accordingly, the memory circuit 620A of the semiconductor chip 600A and the memory circuit 620B of the semiconductor chip 600B can perform a plurality of operations in parallel. In this example, the operation signal SIG _OP1 ～SIG _OPN The equivalent capacitances or parasitic capacitances of the esd protection units 630A1 to 630AN in the semiconductor chips 600A1 and 600B1 must be charged or discharged, and thus, are distorted.

In order to reduce the distortion caused by the capacitance values of the ESD protection units 630A 1-630 AN, the logic circuit 650A may be connected to the signal SIG according to the chip connection signal SIG _CC1 ～SIG _CCM The chip connection signal SIG is then generated by adjusting the capacitance of the ESD protection units 630A 1-630 AN of the semiconductor chip 600A _CC1 ～SIG _CCM Are received by the test electrical contacts 640 A1-640 AM through the test solder structures 66 A1-66 AM. Similarly, the logic circuit 650B may be responsive to the chip connect signal SIG _CC1 ～SIG _CCM Thereby adjusting the ESD protection unit of the semiconductor chip 600B630B 1-630 BN, and chip connection signal SIG _CC1 ～SIG _CCM Are received by the sensing electrical contacts 640B 1-640 BM from the sensing solder structures 66B 1-66 BM. In some embodiments, the chip connect signal SIG _CC1 ～SIG _CCM Can be transmitted to the

semiconductor devices

60A and 60B via the circuit board B1 and can be generated by a control circuit or a processor (not shown in FIG. 9) of the electronic system 6.

Fig. 11 is a schematic structural diagram illustrating an electronic system 7 according to another embodiment of the present disclosure. The electronic system 7 has a similar structure to the electronic system 6. However, the electronic system 7 further includes a third semiconductor element 60C. When the

semiconductor chips

600A and 600B of the

semiconductor devices

60A and 60B have the

memory circuits

620A and 620B as shown in fig. 10, the third semiconductor device 60C has a memory controller MC1 for controlling the

memory circuits

620A and 620B in the

semiconductor chips

600A and 600B. As shown in fig. 11, the memory controller MC1 may be formed in the semiconductor chip 600C in the third semiconductor element 60C. In this case, since the memory controller MC1 must know the total number of

semiconductor chips

600A and 600B coupled together to operate in parallel, the memory controller MC1 can also be used to generate the chip connection signal SIG _CC1 ～SIG _CCM . As shown in fig. 11, the third semiconductor element 60C can be coupled to the first semiconductor element 60A and the second semiconductor element 60B via the circuit board B2, so that the first semiconductor element 60A and the second semiconductor element 60B can receive the operation signal SIG transmitted by the third semiconductor element 60C _OP1 ～SIG _OPN And chip connection signal SIG _CC1 ～SIG _CCM And may therefore perform a plurality of operations and adjust the capacitance values of the esd protection units 630 A1-630 AN and 630B 1-630 AN accordingly.

In some embodiments, the

electronic components

60A and 60B may include a plurality of semiconductor chips. For example, the electronic element 50 shown in fig. 7 may be employed in place of the electronic element 60A and/or the electronic element 60B. In this example, since memory controller MC1 can still know the total number of the plurality of semiconductor chips in electronic system 7 coupled together to operate in parallel, the memory controllerMC1 can generate chip connection signal SIG according to the above _CC1 ～SIG _CCM To further reduce the ESD protection units 630A 1-630 AN and 630B 1-630 BN.

Furthermore, as shown in fig. 11, the third semiconductor element 60C and the first semiconductor element 60A are laterally disposed on a first surface of the circuit board B2, and the second semiconductor element 60B is disposed on a second surface of the circuit board B2. However, in some other embodiments, the electronic system 7 also includes a different number of semiconductor elements, and those semiconductor elements may be configured differently. For example, in some embodiments, the electronic system 7 may omit the second semiconductor element 60B, and the third semiconductor element 60C may be disposed on the second surface of the circuit board B2. That is, the third semiconductor element 60C and the first semiconductor element 60A may be coupled via the circuit board B2 in a back-to-back manner. Further, in this example, since the number of the plurality of semiconductor chips coupled together to operate in parallel is reduced, the chip connection signal SIG generated by the memory controller MC1 of the third semiconductor element 60C _CC1 ～SIG _CCM Different from the embodiment shown in FIG. 11, the logic circuit 650A can adjust the capacitance of the ESD protection units 630A 1-630 AN according to the actual state of the chip connection.

Fig. 12 is a flow chart illustrating a method 800 of esd protection of a semiconductor device according to an embodiment of the disclosure. In some embodiments, the esd protection method 800 may be applied to the semiconductor device 60A shown in fig. 9 and 10. For example, in step S810, the esd protection units 630 A1-630 AN may be formed in the semiconductor chip 600A of the semiconductor device 60A. As shown in FIG. 10, each ESD protection unit 630A 1-630 AN is coupled between the voltage terminal VT and a corresponding operating electrical contact 610A 1-610 AN. The voltage terminal VT can be coupled to the GND or the power voltage VDD. In some embodiments, the ESD protection units 630A 1-630 AN can be implemented by using the ESD protection unit 130A1 or 130B1 shown in FIG. 3. However, in some other embodiments, the esd protection units 6301-630 AN may be implemented by using the esd protection unit 230 shown in fig. 4, the esd protection unit 330 shown in fig. 5, or the esd protection unit 430 shown in fig. 6 according to system requirements.

In addition, in step S820, the first semiconductor element 60A may be coupled to the circuit board B1 as shown in fig. 9, so the first semiconductor element 60A may be coupled to the second semiconductor element 60B via the circuit board B1. In some embodiments, the first semiconductor element 60A and the second semiconductor element 60B may include memory circuits of different orderings. In this example, in step S830, the signal SIG is operated _OP1 ～SIG _OPN Can be transmitted to the first semiconductor element 60A and the second semiconductor element 60B via the circuit board B1, and the first semiconductor element 60A and the second semiconductor element 60B can be operated according to the operation signal SIG _OP1 ～SIG _OPN While multiple operations are performed in parallel.

Furthermore, in step S840, the capacitance values of the esd protection units 630A 1-630 AN of the semiconductor chip 600A may be determined according to the receiving operation signal SIG _OP1 ～SIG _OPN A total number of the plurality of semiconductor chips operated in parallel is adjusted. For example, if each esd protection unit 630 A1-630 AN includes a plurality of esd protection devices coupled between the voltage terminal VT and a corresponding operating electrical contact 610 A1-610 AN, the logic circuit 650A may disconnect at least one esd protection device from the corresponding operating electrical contact or voltage terminal VT by turning off some switches in the esd protection units 630 A1-630 AN or blowing some fuses in the esd protection units 630 A1-630 AN. Accordingly, the capacitance values of the esd protection units 630A1 to 630AN and 630B1 to 630BN of the semiconductor chip 600A can be adjusted.

Further, in the present embodiment, the operation signal SIG is received _OP1 ～SIG _OPN And the semiconductor chip operating in parallel with the first semiconductor chip 600A is in the second semiconductor element 60B and is coupled to the first semiconductor element 60A via the circuit board B1 as shown in fig. 9. However, in some embodiments, the semiconductor element 60A may include more than one semiconductor chip. In this caseWhen calculating the receiving operation signal SIG _OP1 ～SIG _OPN And the total number of the plurality of semiconductor chips operated in parallel includes all of the plurality of semiconductor chips in the semiconductor device 60A.

In short, the semiconductor chip, the semiconductor device and the method for protecting the semiconductor device from electrostatic discharge can adjust the capacitance of the plurality of electrostatic discharge protection units according to the system requirements. Therefore, when a plurality of semiconductor chips are stacked or coupled together to operate in parallel, signal distortion caused by capacitance values of the plurality of ESD protection units of those semiconductor chips can be mitigated, thereby shortening rise time and fall time of the plurality of signals and improving transmission quality of the plurality of signals.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this application.

Claims

1. A semiconductor element, comprising:

a substrate;

an operation solder structure disposed on a first surface of the substrate and configured to receive an operation signal;

a detection solder structure disposed on the first surface of the substrate and configured to receive a chip connect signal; and

a first semiconductor chip disposed on a second surface of the substrate and including:

a first operative electrical contact coupled to the operative solder structure through the substrate;

a first sensing electrical contact coupled to the sensing solder structure through the substrate;

a first ESD protection unit coupled to the first operational electrical contact; and

a first logic circuit coupled to the first detection electrical contact and configured to adjust a capacitance of the first ESD protection unit according to the chip connection signal.

2. The semiconductor device of claim 1, wherein the first semiconductor chip further comprises a memory circuit configured to perform a plurality of operations according to at least the operation signal.

3. The semiconductor device as claimed in claim 1, wherein the first ESD protection unit comprises:

a first ESD protection device coupled between the first operative electrical contact and a voltage terminal;

a second electrostatic discharge protection device; and

a control circuit coupled in series with the second ESD protection device between the first operative electrical contact and the voltage terminal;

wherein the voltage terminal is coupled to a ground or a power voltage.

4. The semiconductor device as claimed in claim 3, wherein the control circuit comprises a switch, and the first logic circuit is configured to turn on or off the switch to adjust the capacitance of the first ESD protection unit.

5. The semiconductor device as claimed in claim 3, wherein the control circuit comprises a fuse, and the first logic circuit is configured to blow the fuse to reduce the capacitance of the first ESD protection unit.

6. The semiconductor device of claim 1, further comprising a second semiconductor chip laterally adjacent to the first semiconductor chip and disposed on the second surface of the substrate or stacked on the first semiconductor chip, wherein the second semiconductor chip comprises:

a second operative electrical contact coupled to the operative solder structure;

a second detection electrical contact coupled to the detection solder structure;

a second ESD protection unit coupled to the second operational electrical contact; and

a second logic circuit coupled to the second detection electrical contact and configured to adjust a capacitance of the second ESD protection unit according to the chip connection signal.

7. An electronic system, comprising:

a circuit board; and

a first semiconductor element coupled to the circuit board and including:

a first substrate;

a first operating solder structure disposed on a first surface of the first substrate and configured to receive a first operating signal;

a first detection solder structure disposed on the first surface of the first substrate and configured to receive a first chip connect signal; and

a first semiconductor chip disposed on a second surface of the first substrate and including:

a first operative electrical contact coupled to the first operative solder structure;

a first detection electrical contact coupled to the first detection solder structure;

a first logic circuit coupled to the first detection electrical contact and configured to adjust a capacitance of the first ESD protection unit according to at least the first chip connection signal.

8. The electronic system of claim 7, wherein the first semiconductor device further comprises a second semiconductor chip laterally adjacent to the first semiconductor chip and disposed on the second surface of the first substrate or stacked on the first semiconductor substrate, wherein the second semiconductor chip comprises:

a second operative electrical contact coupled to the first operative solder structure;

a second detection electrical contact coupled to the first detection solder structure;

a second ESD protection unit coupled to the second operation electrical contact; and

a second logic circuit coupled to the second detection electrical contact and configured to adjust a capacitance of the second ESD protection unit according to the first chip connection signal.

9. The electronic system of claim 7, further comprising a second semiconductor device coupled to the first semiconductor device via the circuit board, wherein:

a structure of the second semiconductor element is the same as a structure of the first semiconductor element;

the second semiconductor element and the first semiconductor element receive the first operation signal and execute a plurality of operations in parallel according to the first operation signal; and

a third logic circuit of a third semiconductor chip in the second semiconductor device is configured to adjust a capacitance of a third esd protection unit of the third semiconductor chip according to the first chip connection signal.

10. The electronic system of claim 9, wherein:

the first semiconductor element is arranged on a first surface of the circuit board, and the second semiconductor element is arranged on a second surface of the circuit board; and

the first semiconductor element and the second semiconductor element are laterally arranged on the same surface of the circuit board.

11. The electronic system of claim 7, wherein the first semiconductor chip further comprises:

a memory circuit configured to perform a plurality of operations in accordance with at least the first operation signal.

12. The electronic system of claim 11, further comprising a third semiconductor device coupled to the first semiconductor device via the circuit board, wherein the third semiconductor device comprises a memory controller configured to control the memory circuit in the first semiconductor chip and generate the first chip connect signal.

13. The electronic system of claim 12, wherein:

the first semiconductor element is arranged on a first surface of the circuit board, and the third semiconductor element is arranged on a second surface of the circuit board; or is

The first semiconductor element and the third semiconductor element are laterally arranged on the same surface of the circuit board.

14. The electronic system of claim 7, wherein the first ESD protection unit comprises:

a first ESD protection device coupled between the first operational electrical contact and a voltage terminal, wherein the voltage terminal is coupled to a ground or a power voltage;

a second electrostatic discharge protection device; and

a control circuit connected in series with the second ESD protection device and coupled between the first operational electrical contact and the ground.

15. The electronic system of claim 14, wherein the control circuit comprises a switch, and the first logic circuit is configured to turn on or off the switch to adjust the capacitance of the first esd protection unit.

16. The electronic system as recited in claim 14, wherein the control circuit comprises a fuse, and the first logic circuit is configured to blow the fuse to reduce the capacitance of the first esd protection unit.

17. A method for protecting a first semiconductor device from electrostatic discharge, wherein the first semiconductor device comprises a substrate; an operation solder structure disposed on a first surface of the substrate; and a first semiconductor chip disposed on a second surface of the substrate; and the electrostatic discharge protection method comprises:

forming an ESD protection unit in the first semiconductor chip, wherein the ESD protection unit is coupled between a voltage terminal and an operating electrical contact point of the first semiconductor chip coupled to the operating solder structure via the substrate, and the voltage terminal is coupled to a ground or a power voltage;

coupling the first semiconductor element to a circuit board;

transmitting an operation signal to the operation solder structure through the substrate; and

the capacitance values of the electrostatic discharge protection units are adjusted according to the total number of the semiconductor chips which transmit the operation signal and operate in parallel with the first semiconductor chip.

18. The esd protection method of claim 17, wherein the esd protection unit comprises a plurality of esd protection devices coupled between the operating electrical contact and the voltage terminal, and transmitting the operating signal and adjusting capacitance of the plurality of esd protection units according to a total number of the plurality of semiconductor chips operating in parallel with the first semiconductor chip, comprising:

disconnecting at least one ESD protection device from the operative electrical contact or the voltage terminal.

19. The esd protection method of claim 17, wherein one of the semiconductor chips transmitting the operation signal and operating in parallel with the first semiconductor chip is in the first semiconductor device or in a second semiconductor device coupled to the first semiconductor device via the circuit board.

20. The esd protection method of claim 19, wherein the first semiconductor device and the second semiconductor device comprise memory circuits of different ranks.