CN115910796A - Method for forming semiconductor element - Google Patents
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- CN115910796A CN115910796A CN202211547990.1A CN202211547990A CN115910796A CN 115910796 A CN115910796 A CN 115910796A CN 202211547990 A CN202211547990 A CN 202211547990A CN 115910796 A CN115910796 A CN 115910796A
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Abstract
The invention provides a method for forming a semiconductor element, which comprises the following steps: providing a substrate; forming a dielectric layer on the substrate, wherein a first grid groove is formed in the dielectric layer; a first dielectric layer and a first high-dielectric-constant dielectric layer are formed in the first grid groove; carrying out a first annealing process on the first high-dielectric-constant dielectric layer; carrying out a first threshold voltage doping manufacturing process in the first grid groove; and forming a first gate in the first gate groove. According to the forming method of the semiconductor element, after the high-dielectric-constant dielectric layer is formed, ions are implanted into the channel region through the threshold voltage doping manufacturing process, and the influence of the thermal effect of the high-dielectric-constant dielectric layer annealing process on ion diffusion can be reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing methods, and particularly relates to a forming method of a semiconductor element.
Background
As MOS transistors become smaller in feature size, the threshold voltage must be adjusted lower in order to increase saturation current. The threshold voltage is mainly influenced by the following factors: the positive charge density in the gate oxide layer, the substrate doping concentration, the dielectric permittivity, the difference in work function between the gate material and the substrate, etc. At present, the industry often uses a metal gate as a control electrode instead of a polysilicon gate, and the metal gate is matched with a gate dielectric layer with a high dielectric constant, and the threshold voltage of the transistor is adjusted by ion implantation.
Disclosure of Invention
To overcome one of the drawbacks of the prior art, the present invention provides a method for forming a semiconductor device.
The technical scheme adopted by the invention is as follows:
a method for forming a semiconductor element includes:
providing a substrate;
forming a dielectric layer on the substrate, wherein a first grid groove is formed in the dielectric layer;
a first dielectric layer and a first high-dielectric-constant dielectric layer are formed in the first grid groove;
performing a first annealing process on the first high-dielectric-constant dielectric layer;
performing a first threshold voltage doping process in the first gate trench;
and forming a first gate in the first gate groove.
In some embodiments, a second annealing process is performed after the first threshold voltage doping process.
In some of these embodiments, a barrier layer is deposited on the first high-k dielectric layer prior to the first annealing process.
In some embodiments, a high-k dielectric layer protection layer is formed on the barrier layer before the second annealing process; removing the high-k dielectric layer protection layer after the second annealing process.
In some embodiments, a first dummy gate structure is formed on the substrate, wherein the first dummy gate structure comprises the first dielectric layer and a dummy gate;
removing the dummy gate of the first dummy gate structure to form the first gate trench.
In some embodiments, a fin structure is formed on the substrate, wherein the first dummy gate structure is formed on the fin structure.
In some embodiments, after the second annealing process, at least one first work function layer is formed within the first gate trench before the first gate is formed.
The invention also provides a method for forming a semiconductor element, which comprises the following steps:
providing a substrate;
forming a dielectric layer on the substrate, wherein a first grid groove and a second grid groove are formed in the dielectric layer;
a first dielectric layer and a first high-dielectric-constant dielectric layer are formed in the first grid groove, and a second dielectric layer and a second high-dielectric-constant dielectric layer are formed in the second grid groove;
performing a first annealing process on the first high-k dielectric layer and the second high-k dielectric layer;
performing a first threshold voltage doping process in the first gate trench;
performing a second threshold voltage doping process in the second gate trench;
the second threshold voltage doping manufacturing process is to implant dopants different from the first threshold voltage doping manufacturing process;
forming a first grid in the first grid groove;
and forming a second gate in the second gate groove.
In some of these embodiments, a barrier layer is deposited on the first high-k dielectric layer and on the second high-k dielectric layer prior to the first annealing process;
after the first threshold voltage doping manufacturing process and the second threshold voltage doping manufacturing process, performing a second annealing process;
before the second annealing process, forming a high-dielectric-constant dielectric layer protection layer on the barrier layer; removing the high-k dielectric layer protection layer after the second annealing process.
In some embodiments, after the second annealing process and before the first gate is formed, a first work function layer is formed in the first gate trench; before the second grid is formed, a second work function layer is formed in the second grid groove; wherein the second work function layer and the first work function layer have the same conductivity type and different thicknesses.
Compared with the prior art, the invention has the advantages and positive effects that: the threshold voltage doping manufacturing process is carried out after the high-dielectric-constant dielectric layer is formed, ions are injected into the channel region, and the influence of the thermal effect of the annealing process of the high-dielectric-constant dielectric layer on ion diffusion can be reduced, so that the influence of the high-dielectric-constant dielectric layer on threshold voltage adjustment is reduced, and the threshold voltage is adjusted more accurately.
Drawings
FIG. 1 is a cross-sectional view of a step of a method of forming a semiconductor device in which a dummy gate structure has been formed, according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a step of a method of forming a semiconductor device in accordance with an embodiment of the present invention, wherein the dummy gate is removed;
FIG. 3 is a cross-sectional view of a step of a method for forming a semiconductor device according to an embodiment of the present invention, wherein a high-k dielectric layer is formed;
FIG. 4 is a cross-sectional view of a step of a method of forming a semiconductor device in accordance with an embodiment of the present invention, wherein a first threshold voltage doping process is being performed;
FIG. 5 is a cross-sectional view of a step of a method of forming a semiconductor device in accordance with an embodiment of the present invention, wherein a second threshold voltage doping process is being performed;
FIG. 6 is a cross-sectional view of a step of a method of forming a semiconductor device in accordance with an embodiment of the present invention, wherein a third threshold voltage doping process is being performed;
FIG. 7 is a cross-sectional view of a step in a method of forming a semiconductor device in which a work function layer and a gate have been formed, according to an embodiment of the present invention;
FIG. 8 is a cross-sectional view of a step of a method of forming a semiconductor device in which a planarization process has been performed, in accordance with an embodiment of the present invention;
fig. 9 is a flow chart illustrating a method for forming a semiconductor device according to an embodiment of the invention.
In the figure:
100. a substrate; 101. a dielectric layer; 102. a fin structure; 103. a source/drain electrode;
110. a first transistor region; 110a, a first gate; 110b, a first dummy gate structure; 111. a first gate trench; 112. a first dielectric layer; 113. a first high-k dielectric layer; 114. a first dummy gate; 115. a first high-k dielectric layer protection layer; 116. a first work function layer;
120. a second transistor region; 120a, a second gate; 120b, a second dummy gate structure; 121. a second gate trench; 122. a second dielectric layer; 123. a second high-k dielectric layer; 124. a second dummy gate; 125. a second high-k dielectric layer protection layer; 126. a second work function layer;
130. a third transistor region; 130a, a third gate; 130b, a third dummy gate structure; 131. a third gate trench; 132. a third dielectric layer; 133. a third high-k dielectric layer; 134. a third dummy gate; 135. a third high-k dielectric layer protection layer; 136. a third work function layer;
200. a first patterned photoresist layer;
400. a second patterned photoresist layer;
600. and a third patterned photoresist layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a method for forming a semiconductor element, which comprises the following steps:
providing a substrate 100;
forming a dielectric layer 101 on the substrate 100, wherein a first gate trench 111 is formed in the dielectric layer 101;
a first dielectric layer 112 and a first high-k dielectric layer 113 are formed in the first gate trench;
performing a first annealing process on the first high-k dielectric layer 113;
performing a first threshold voltage doping process P1 in the first gate trench 111;
a first gate electrode 110a is formed within the first gate trench 111.
The first threshold voltage doping manufacturing process P1 is used for injecting threshold voltage adjusting ions into the channel region, and the first threshold voltage doping manufacturing process P1 is carried out after the high-dielectric-constant dielectric layer is formed, so that the influence of the thermal effect of the high-dielectric-constant dielectric layer annealing process on ion diffusion can be reduced, and the influence of the high-dielectric-constant dielectric layer on threshold voltage adjustment is reduced.
Fig. 1 to 8 are schematic views illustrating a method for forming a semiconductor device according to a first embodiment of the present invention. First, as shown in fig. 1, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate. At least one transistor region 110 is defined on the substrate 100.
The method for forming the semiconductor device of the present application is described by taking a fin field effect transistor (FinFET) as an example. The method comprises the steps of forming a fin-shaped structure 102 on a substrate, sequentially forming a dielectric material layer, a dummy gate material layer and a cap material layer on the fin-shaped structure 102, patterning the stacked material layers to form a dummy gate structure, wherein the dummy gate structure comprises the dielectric layer, the dummy gate and a cap layer, forming spacers on sidewalls of the dummy gate structure, and forming source/drain electrodes on two sides of the dummy gate structure. The dielectric layer is composed of silicon oxide, silicon nitride or silicon oxynitride, the dummy gate is composed of a doped polysilicon material, a polysilicon material without any dopant or an amorphous silicon material, and the cap layer is composed of a single-layer or multi-layer structure. The spacer material includes a high-temperature silicon oxide layer, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride formed using hexachlorodisilane, or the like. And forming a contact hole etching stop layer to cover the whole virtual grid structure and forming a dielectric layer on the contact hole etching stop layer. The dielectric layer material comprises a silicon oxide layer or tetraethoxysilane. Then, the dielectric layer and the contact hole etching stop layer are flattened to expose the top of the virtual grid, and a selective dry etching or wet etching manufacturing process is carried out to remove the virtual grid so as to form a grid groove in the dielectric layer. As shown in fig. 2, in one embodiment, a first dummy gate structure 110b is formed on the substrate, wherein the first dummy gate structure 110b includes a first dielectric layer 112 and a first dummy gate 114; the first dummy gate 114 is removed to form a first gate trench 111.
Then, a first high-k dielectric layer 113 is sequentially formed in the first gate trench. As shown in FIG. 3, the first dielectric layer 112 is U-shaped, and the first high-k dielectric layer 113 is U-shaped. The method includes, for example, forming a dielectric material layer and a high-k dielectric material layer on the fin structure 102, and performing a planarization process, such as a chemical mechanical polishing or etching process, to remove the dielectric material layer and the high-k dielectric material layer. In some embodiments, the first dielectric layer 112 comprises silicon oxide or silicon nitride, for example. The first high-k dielectric layer 113 is, for example, a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO) 2 ) Hafnium silicate oxide (HfSiO) 4 ) Hafnium silicate oxynitride (HfSiON), aluminum oxide (Al) 2 O 3 ) And the like or combinations thereof.
After the first high-k dielectric layer 113 is formed, a first annealing process is performed. Wherein the first annealing process may be any one of a blanket anneal, a spike anneal, and a laser anneal, for example, the preheating is performed at a temperature in a range of about 400 ℃ to about 900 ℃ for a duration in a range of about 3 seconds to about 40 seconds, and the annealing is performed at a peak temperature in a range of 950 ℃ to about 1200 ℃ for a duration in a range of about 1 millisecond to about 20 milliseconds. The first annealing process mixes the first high-k dielectric layer 113 and the first dielectric layer 112 interface with each other.
Then, a first threshold voltage doping process P1 is performed on the exposed first gate trench 111, and for a semiconductor device having only one gate trench (the first gate trench 111) on the substrate, doping may be directly performed without using a patterned mask layer, so as to adjust a threshold voltage of a gate structure to be formed subsequently. For example, if a P-type transistor is selected to be formed in the transistor region, N-type dopants may be doped into the fin structure to adjust the threshold voltage of the gate structure formed in the transistor region. On the contrary, if the N-type transistor is selected to be formed in the transistor region, the P-type dopant is doped to adjust the threshold voltage. In some of these embodiments, the N-type dopants are, for example, arsenic atoms, phosphorus atoms, antimony atoms, or bismuth atoms, and the P-type dopants are, for example, boron atoms, aluminum atoms, gallium atoms, or indium atoms.
As shown in fig. 1 to 8, a plurality of transistor regions, for example, three transistor regions, specifically, a first transistor region 110, a second transistor region 120, and a third transistor region 130, are defined on a substrate 100. Of course, two transistor regions may be defined on the substrate. For the case of three transistor regions, the three transistor regions are transistor regions of the same conductivity type, such as all PMOS transistor regions or all NMOS transistor regions, and the three transistor regions are respectively predetermined for the subsequent fabrication of gate structures with different threshold voltages. The three transistor regions may alternatively comprise transistor regions of different conductivity types. For the semiconductor requiring three gate trenches, for example, three fin-shaped structures are formed on a substrate, then a dielectric material layer, a dummy gate material layer and a cap material layer are sequentially formed on the fin-shaped structures, and then the stacked material layers are patterned to form three dummy gate structures, spacers are respectively formed on sidewalls of the three dummy gate structures, and source/drain electrodes are formed on two sides of the three dummy gate structures. Then, a contact hole etching stop layer and a dielectric layer are formed in sequence. The dielectric layer and the contact hole etch stop layer are then planarized to expose the tops of the three dummy gates, and the three dummy gates are removed to form three gate trenches in the dielectric layer. For example, as shown in fig. 1 and fig. 2, a first dummy gate structure 110b, a second dummy gate structure 120b, and a third dummy gate structure 130b are formed on the substrate, wherein the first dummy gate structure 110b includes a first dielectric layer 112 and a first dummy gate 114, the second dummy gate structure 120b includes a second dielectric layer 122 and a second dummy gate 124, and the third dummy gate structure 130b includes a third dielectric layer 132 and a third dummy gate 134; the first dummy gate 114 of the first dummy gate structure is removed to form a first gate trench 111, the second dummy gate 124 of the second dummy gate structure is removed to form a second gate trench 121, and the third dummy gate 134 of the third dummy gate structure is removed to form a third gate trench 131. Next, as shown in fig. 3, a dielectric layer and a high-k dielectric layer are sequentially formed in the first gate trench 111, the second gate trench 121 and the third gate trench 131, respectively, the first dielectric layer 112 and the first high-k dielectric layer 113 are located in the first gate trench, the second dielectric layer 122 and the second high-k dielectric layer 123 are located in the second gate trench 121, and the third dielectric layer 132 and the third high-k dielectric layer 133 are located in the third gate trench 131. After the high-k dielectric layer is formed, a first annealing process is performed on the high-k dielectric layer to mix the interfaces of the high-k dielectric layer and the dielectric layer.
Next, as shown in fig. 4, a first threshold voltage doping process P1 is performed on the exposed first gate trench 111. The forming method includes, for example, forming a patterned mask layer, such as a first patterned photoresist layer 200, covering the second transistor region 120 and the third transistor region 130, and performing a first threshold voltage doping process P1 on the exposed first gate trench 111 using the first patterned photoresist layer 200 as a mask to form a doped region, thereby adjusting a threshold voltage of a gate structure formed in the first transistor region 110. Then, as shown in fig. 5, the first patterned photoresist layer 200 is removed, and a second patterned photoresist layer 400 covering the first transistor region 110 and the third transistor region 130 is formed. The second gate trench 121 (located in the second transistor region 120) is subjected to a second threshold voltage doping process P2 using the second patterned photoresist layer 400 as a mask to form a doped region, and a threshold voltage of a gate structure subsequently formed in the second transistor region 120 is adjusted. Specifically, the second threshold voltage doping process P2 may select a dopant having the same conductivity type as the first threshold voltage doping process P1 but containing a different dopant material. For example, if the first threshold voltage doping process P1 is antimony atom (N-type dopant), the second threshold voltage doping process P2 may be bismuth atom (N-type dopant) to make the gate structure in the first transistor region 110 have a different threshold value than the second transistor region 120 and the third transistor region 130, but not limited thereto. Then, as shown in fig. 6, the second patterned photoresist layer 400 is removed, and a third patterned photoresist layer 600 covering the first transistor region 110 and the second transistor region 120 is formed. A third threshold voltage doping process P3 is performed on the exposed third gate trench 131 (located in the third transistor region 130) using the third patterned photoresist layer 600 as a mask to form a doped region, and a threshold voltage of a gate structure subsequently formed in the third transistor region 130 is adjusted. The third threshold voltage doping process P3 may also select a dopant having the same conductivity type as the first threshold voltage doping process P1 but including a different dopant material, or select a dopant material the same as the first threshold voltage doping process P1 and the second threshold voltage doping process P2 but different from the dopant dose of the first threshold voltage doping process P1 and the second threshold voltage doping process P2, so that the first transistor region 110, the second transistor region 120, and the third transistor region 130 respectively have different dopant concentrations and different threshold voltages, but are not limited thereto.
In some embodiments, the first threshold voltage doping process is followed by a second annealing process. The second annealing process allows the implanted ions to be further controllably diffused to further adjust the threshold voltage of the gate structures subsequently formed in the transistor regions 110, 120, 130.
In some of these embodiments, a barrier layer is deposited on the high- k dielectric layer 113, 123, 133 prior to the first annealing process. The barrier layer may comprise a metallic material such as titanium nitride (TiN), titanium aluminide TiAl, tantalum nitride (TaN). Depositing a first barrier layer on the first high-k dielectric layer 113; depositing a second barrier layer on the second high-k dielectric layer 123; a third barrier layer is deposited over the third high-k dielectric layer 133. And forming a TiN layer by adopting an atomic layer deposition method or a physical vapor deposition method, wherein the thickness of the TiN layer is 10-30 angstroms. The barrier layer may serve as a barrier to protect the high-k dielectric layers 113, 123, 133. The TiN layer serves to prevent ions generated during the formation of the metal gate from diffusing into the underlying work function layer.
In some embodiments, as shown in fig. 3, a high-k dielectric layer protection layer 115, 125, 135 is formed on the high-k dielectric layers 113, 123, 133 before the second annealing process. The high-k dielectric layer protection layers 115, 125, 135 may be amorphous silicon layers or polysilicon layers. The high-k dielectric layer protection layers 115, 125, 135 are removed after the second annealing process. Forming a first high-k dielectric layer protection layer 115 on the first high-k dielectric layer 113; forming a second high-k dielectric layer protection layer 125 on the second high-k dielectric layer 123; a third high-k dielectric layer protection layer 135 is formed on the third high-k dielectric layer 133. The amorphous silicon layer may be deposited at a temperature of less than about 530 c. The amorphous silicon layer may be formed by PVD, CVD, ALD, and PECVD methods. The amorphous silicon layer may prevent the high- k dielectric layer 113, 123, 133 from degrading during a subsequent annealing process. For embodiments employing an amorphous silicon layer in a semiconductor forming method, the second annealing process may be a spike anneal, and the second annealing process may be, for example: the stable temperature of the spike annealing is 550-650 ℃, the peak temperature range is 950-1050 ℃, and the heating rate is 150-220 ℃/s. The second annealing process causes the amorphous silicon layer to absorb oxygen elements in the high-k dielectric layers 113, 123, 133. In the fin field effect transistor process, a layer of amorphous silicon, namely an amorphous silicon layer, is deposited after a high dielectric constant dielectric layer is formed, the amorphous silicon layer absorbs oxygen elements in the high dielectric constant dielectric layer through annealing, and then the amorphous silicon layer is removed and metal gate deposition is carried out.
In some embodiments, after the second annealing process and before the gate formation, a work function layer is formed in the gate trench, wherein the work function layer of each gate has the same conductivity type and different thickness. For example, two transistor regions are formed on the substrate, after the second annealing process, a first work function layer 116 is formed in the first gate trench 111 before the first gate 110a is formed, and a second work function layer 126 is formed in the second gate trench 121 before the second gate 120a is formed; wherein the second work function layer 126 and the first work function layer 116 have the same conductivity type and different thicknesses. For example, as shown in fig. 7, three transistor regions are formed on the substrate, after the second annealing process, a first work function layer 116 is formed in the first gate trench 111 before the first gate 110a is formed, a second work function layer 126 is formed in the second gate trench 121 before the second gate 120a is formed, and a third work function layer 136 is formed in the third gate trench 131 before the third gate 130a is formed; wherein the third work function 136, the second work function layer 126, and the first work function layer 116 have the same conductivity type and different thicknesses. The composition of the work function layer is preferably different materials depending on the type of transistor used. For example, if the transistor is an N-type transistor, the work function layer may comprise a metal material having a work function of 3.9 electron volts (eV) to 4.3eV, such as, but not limited to, titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC). Conversely, if the transistor is a P-type transistor, the work function layer comprises a metal material having a work function of 4.8eV to 5.2eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC).
In some embodiments, the fin structure may be formed by forming a patterned mask on the substrate, and then transferring the pattern of the patterned mask to the substrate by an etching process. Then, according to the different structure characteristics of tri-gate transistor element or double-gate fin transistor element, the patterned mask can be selectively removed or left, and then the deposition, chemical mechanical polishing and back etching processes are matched to form the insulating layer, and the fin structure is formed on the substrate protruding from the insulating layer. In another embodiment, the fin structure is formed by first forming a patterned hard mask layer on the substrate, and then growing a semiconductor layer, such as a semiconductor layer including silicon or silicon germanium, on the substrate exposed outside the patterned hard mask layer by an epitaxial process to form a corresponding fin structure.
As shown in fig. 9, a method for forming a semiconductor device according to an embodiment of the present invention includes the following steps:
providing a substrate, and forming a fin-shaped structure on the substrate;
forming a dummy gate structure on the fin structure;
removing the dummy gate to form a gate trench;
forming a dielectric layer and a high dielectric constant dielectric layer in the gate trench;
forming a barrier layer on the high-k dielectric layer;
carrying out a first annealing process;
forming a high-dielectric-constant dielectric layer protection layer on the barrier layer;
carrying out a threshold voltage doping manufacturing process on the grid groove;
carrying out a second annealing process;
removing the high-dielectric-constant dielectric layer protection amorphous silicon layer;
depositing a work function layer;
depositing a metal grid;
and carrying out a planarization manufacturing process.
Wherein the substrate is a silicon substrate; the dielectric layer is silicon oxide; the high-k dielectric layer is hafnium oxide (HfO) 2 ) And hafnium silicate oxide (HfSiO) 4 ) (ii) a Doping P-type dopant boron atoms in the threshold voltage doping manufacturing process; the work function layer comprises titanium aluminide (TiAl); the metal gate may include titanium (Ti), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicide nitride (TaSiN), titanium nitride (TiN), tantalum nitride (TaN), other suitable metal materials, and/or combinations thereof.
In summary, the method for forming a semiconductor device of the present invention mainly utilizes a threshold voltage doping process to adjust the threshold voltage of the transistor region after the high-k dielectric layer is formed. For the case that a plurality of transistor areas coexist, after the high-dielectric-constant dielectric layer is formed, different threshold voltage doping manufacturing processes are adopted, so that the gate structures formed in the transistor areas can have different threshold voltages, and the semiconductor element with the metal gates with different threshold voltages is formed. The forming method of the invention can be applied to manufacturing three or more metal grid structures, so that each metal grid has different critical voltages.
Claims (10)
1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a dielectric layer on the substrate, wherein a first grid groove is formed in the dielectric layer;
a first dielectric layer and a first high-dielectric-constant dielectric layer are formed in the first grid groove;
performing a first annealing process on the first high-dielectric-constant dielectric layer;
performing a first threshold voltage doping process in the first gate trench;
and forming a first gate in the first gate groove.
2. The method as claimed in claim 1, wherein a second annealing process is performed after the first threshold voltage doping process.
3. The method as claimed in claim 2, wherein a barrier layer is deposited on the first high-k dielectric layer before the first annealing process.
4. The method for forming a semiconductor element according to claim 3, wherein:
forming a high dielectric constant dielectric layer protection layer on the barrier layer; removing the high-k dielectric layer protection layer after the second annealing process.
5. The method for forming a semiconductor element according to claim 1, wherein:
forming a first virtual grid structure on the substrate, wherein the first virtual grid structure comprises the first dielectric layer and a virtual grid;
removing the dummy gate of the first dummy gate structure to form the first gate trench.
6. The method for forming a semiconductor device according to claim 5,
a fin structure is formed on the substrate, wherein the first dummy gate structure is formed on the fin structure.
7. The method for forming a semiconductor element according to claim 4, further comprising:
after the second annealing process and before the first gate is formed, at least one first work function layer is formed in the first gate trench.
8. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a dielectric layer on the substrate, wherein a first grid electrode groove and a second grid electrode groove are formed in the dielectric layer;
a first dielectric layer and a first high-dielectric-constant dielectric layer are formed in the first grid groove, and a second dielectric layer and a second high-dielectric-constant dielectric layer are formed in the second grid groove;
performing a first annealing process on the first high-k dielectric layer and the second high-k dielectric layer;
carrying out a first threshold voltage doping manufacturing process in the first grid groove;
performing a second threshold voltage doping process in the second gate trench;
the second threshold voltage doping manufacturing process is to inject dopants different from the first threshold voltage doping manufacturing process;
forming a first grid in the first grid groove;
and forming a second gate in the second gate trench.
9. The method for forming a semiconductor device according to claim 8,
depositing a barrier layer on the first high-permittivity dielectric layer and on the second high-permittivity dielectric layer prior to the first annealing process;
after the first threshold voltage doping manufacturing process and the second threshold voltage doping manufacturing process, performing a second annealing process;
forming a high-dielectric-constant dielectric layer protection layer on the barrier layer before the second annealing process; removing the high-k dielectric layer protection layer after the second annealing process.
10. The method for forming a semiconductor element according to claim 9, further comprising:
after the second annealing process, forming a first work function layer in the first gate trench before the first gate is formed, and forming a second work function layer in the second gate trench before the second gate is formed; wherein the second work function layer and the first work function layer have the same conductivity type and different thicknesses.
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