CN115910796A - Method for forming semiconductor element - Google Patents

Abstract

The present invention provides a method for forming a semiconductor element, comprising: providing a substrate; forming a dielectric layer on the substrate, wherein a first gate trench is formed in the dielectric layer; the first gate A first dielectric layer and a first high-permittivity dielectric layer are formed in the trench; a first annealing process is performed on the first high-permittivity dielectric layer; a first annealing process is performed in the first gate trench A first threshold voltage doping process; forming a first gate in the first gate trench. In the forming method of the semiconductor element, after the high dielectric constant dielectric layer is formed, the threshold voltage doping process is performed on the channel region to implant ions, which can reduce the influence of the thermal effect of the high dielectric constant dielectric layer annealing process on ion diffusion.

Description

Method for forming semiconductor element

technical field

The invention belongs to the technical field of semiconductor manufacturing methods, in particular to a method for forming a semiconductor element.

Background technique

As the feature size of MOS transistors becomes smaller and smaller, in order to increase the saturation current, the threshold voltage must be lowered. The main factors affecting the threshold voltage are: the positive charge density in the gate oxide layer, the doping concentration of the substrate, the dielectric constant of the dielectric, the difference between the work function of the gate material and the substrate, etc. At present, the industry often uses metal gates to replace polysilicon gates as control electrodes, which match with high dielectric constant gate dielectric layers, and at the same time adjust the threshold voltage of transistors by ion implantation. However, when adjusting the threshold voltage by ion implantation, Due to the uncontrollable interference of the subsequent process, the threshold voltage of the obtained semiconductor often cannot meet expectations.

Contents of the invention

To overcome one of the defects in the prior art, the present invention provides a method for forming a semiconductor device.

The technical scheme adopted in the present invention is:

A method of forming a semiconductor device, comprising:

provide a base;

forming a dielectric layer on the substrate, wherein a first gate trench is formed in the dielectric layer;

A first dielectric layer and a first high dielectric constant dielectric layer are formed in the first gate trench;

performing a first annealing process on the first high-k dielectric layer;

performing a first threshold voltage doping process in the first gate trench;

A first gate is formed in the first gate trench.

In some of the embodiments, after the first threshold voltage doping process, a second annealing process is performed.

In some of the embodiments, before the first annealing process, a barrier layer is deposited on the first high-k dielectric layer.

In some of these embodiments, before the second annealing process, a high-k dielectric protection layer is formed on the barrier layer; after the second annealing process, the high-k dielectric layer is removed. Dielectric protective layer.

In some of these embodiments, a first dummy gate structure is formed on the substrate, wherein the first dummy gate structure includes the first dielectric layer and a dummy gate;

The dummy gate of the first dummy gate structure is removed to form the first gate trench.

In some embodiments, a fin structure is formed on the substrate, wherein the first dummy gate structure is formed on the fin structure.

In some of the embodiments, after the second annealing process and before the formation of the first gate, at least one first work function layer is formed in the first gate trench.

The present invention also provides a method for forming a semiconductor element, comprising:

provide a base;

forming a dielectric layer on the substrate, wherein a first gate trench and a second gate trench are formed in the dielectric layer;

A first dielectric layer and a first high-permittivity dielectric layer are formed in the first gate trench, and a second dielectric layer and a second high-permittivity dielectric layer are formed in the second gate trench. layer;

performing a first annealing process on the first high-k dielectric layer and the second high-k dielectric layer;

performing a first threshold voltage doping process in the first gate trench;

performing a second threshold voltage doping process in the second gate trench;

The second threshold voltage doping process is to implant dopants different from the first threshold voltage doping process;

forming a first gate within the first gate trench;

A second gate is formed in the second gate trench.

In some of the embodiments, before the first annealing process, a barrier layer is deposited on the first high-k dielectric layer and on the second high-k dielectric layer;

After the first threshold voltage doping process and the second threshold voltage doping process, a second annealing process is performed;

Before the second annealing process, a high-k dielectric protection layer is formed on the barrier layer; after the second annealing process, the high-k dielectric protection layer is removed.

In some of these embodiments, after the second annealing process, before the formation of the first gate, a first work function layer is formed in the trench of the first gate; Before the electrode is formed, a second work function layer is formed in the second gate trench; wherein the second work function layer and the first work function layer have the same conductivity type and different thicknesses.

Compared with the prior art, the advantages and positive effects of the present invention are: after the high dielectric constant dielectric layer is formed, the threshold voltage doping process is performed to implant ions into the channel region, which can reduce the high dielectric constant dielectric layer. The influence of the thermal effect of the annealing process on the ion diffusion, thereby reducing the influence of the high dielectric constant dielectric layer on the adjustment of the threshold voltage, makes the adjustment of the threshold voltage more accurate.

Description of drawings

1 is a schematic cross-sectional view of steps in a method for forming a semiconductor element in an embodiment of the present invention, wherein a dummy gate structure has been formed;

2 is a schematic cross-sectional view of steps in a method for forming a semiconductor device in an embodiment of the present invention, wherein dummy gates are removed;

3 is a schematic cross-sectional view of steps in a method for forming a semiconductor element in an embodiment of the present invention, wherein a high-k dielectric layer is formed;

4 is a schematic cross-sectional view of steps in a method for forming a semiconductor element in an embodiment of the present invention, wherein the first threshold voltage doping process is being implemented;

5 is a schematic cross-sectional view of steps in a method for forming a semiconductor element in an embodiment of the present invention, wherein a second threshold voltage doping process is being implemented;

6 is a schematic cross-sectional view of steps in a method for forming a semiconductor element in an embodiment of the present invention, wherein a third threshold voltage doping process is being implemented;

7 is a schematic cross-sectional view of steps in a method for forming a semiconductor element in an embodiment of the present invention, wherein a work function layer and a gate have been formed;

8 is a schematic cross-sectional view of steps in a method for forming a semiconductor element in an embodiment of the present invention, wherein the planarization process has been completed;

FIG. 9 is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.

In the picture:

100, base; 101, dielectric layer; 102, fin structure; 103, source/drain;

110, the first transistor region; 110a, the first gate; 110b, the first dummy gate structure; 111, the first gate trench; 112, the first dielectric layer; 113, the first high dielectric constant dielectric layer; 114, the first dummy gate; 115, the first high dielectric constant dielectric layer protective layer; 116, the first work function layer;

120, the second transistor region; 120a, the second gate; 120b, the second dummy gate structure; 121, the second gate trench; 122, the second dielectric layer; 123, the second high dielectric constant dielectric layer; 124, the second dummy gate; 125, the second high dielectric constant dielectric layer protection layer; 126, the second work function layer;

130, the third transistor region; 130a, the third gate; 130b, the third dummy gate structure; 131, the third gate trench; 132, the third dielectric layer; 133, the third high dielectric constant dielectric layer; 134, the third dummy gate; 135, the third high dielectric constant dielectric layer protective layer; 136, the third work function layer;

200. A first patterned photoresist layer;

400. A second patterned photoresist layer;

600. A third patterned photoresist layer.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

An embodiment of the present invention provides a method for forming a semiconductor element, including:

providing a base 100;

forming a dielectric layer 101 on the substrate 100, wherein a first gate trench 111 is formed in the dielectric layer 101;

A first dielectric layer 112 and a first high dielectric constant dielectric layer 113 are formed in the first gate trench;

performing a first annealing process on the first high-k dielectric layer 113;

performing a first threshold voltage doping process P1 in the first gate trench 111;

The first gate 110 a is formed within the first gate trench 111 .

The first threshold voltage doping manufacturing process P1 implants threshold voltage adjusting ions into the channel region. This application chooses to perform the first threshold voltage doping manufacturing process P1 after the formation of the high dielectric constant dielectric layer, which can reduce the high dielectric constant dielectric layer. The influence of the thermal effect of the electric layer annealing process on ion diffusion, thereby reducing the influence of the high dielectric constant dielectric layer on threshold voltage adjustment.

1 to 8 are schematic diagrams of a method for forming a semiconductor device in the first embodiment of the present invention. First, as shown in FIG. 1 , a substrate 100 is provided. The substrate 100 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-covered insulating substrate. At least one transistor region 110 is defined on the substrate 100 .

Taking a Fin Field Effect Transistor (FinFET) as an example, the method for forming the semiconductor device of the present application will be described. A fin structure 102 is formed on the substrate, and then a dielectric material layer, a dummy gate material layer, and a cap material layer are sequentially formed on the fin structure 102, and then these stacked material layers are patterned to form a dummy gate. electrode structure, wherein the dummy gate structure respectively includes a dielectric layer, a dummy gate and a cover layer, spacers are formed on the side walls of the dummy gate structure, and sources are formed on both sides of the dummy gate structure /drain. Among them, the dielectric layer is made of silicon oxide, silicon nitride or silicon oxynitride, the dummy gate is made of polysilicon material with dopant, polysilicon material without any dopant or amorphous silicon material, and the cover layer is made of single layer or multilayer structure. The spacer material includes high temperature silicon oxide layer, silicon nitride, silicon oxide, silicon oxynitride or silicon nitride formed by using hexachlorodisilane. Afterwards, a contact hole etch stop layer is formed to cover the entire dummy gate structure, and a dielectric layer is formed on the contact hole etch stop layer. The material of the dielectric layer includes silicon oxide layer or tetraethoxysilane. Then planarize the dielectric layer and contact hole etch stop layer to expose the top of the dummy gate, and perform a selective dry etch or wet etch process to remove the dummy gate to form a gate in the dielectric layer pole groove. As shown in FIG. 2, in one embodiment, a first dummy gate structure 110b is formed on the substrate, wherein the first dummy gate structure 110b includes a first dielectric layer 112 and a first dummy gate structure. Gate 114 ; removing the first dummy gate 114 to form the first gate trench 111 .

Next, a first high-k dielectric layer 113 is sequentially formed in the first gate trench. As shown in FIG. 3 , the first dielectric layer 112 is U-shaped, and the first high-k dielectric layer 113 is U-shaped. The forming method includes, for example, completely forming a dielectric material layer and a high-k dielectric material layer on the fin structure 102, and then performing a planarization process, such as a chemical mechanical polishing or etching process. In addition to the dielectric material layer and the high dielectric constant dielectric material layer located in the dielectric layer. In some of the embodiments, the first dielectric layer 112 includes silicon oxide or silicon nitride, for example. The first high-k dielectric layer 113 is, for example, made of a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO ₂ ), hafnium oxysilicate (HfSiO ₄ ), hafnium oxynitride silicate (HfSiON), aluminum oxide (Al ₂ O ₃ ), etc., or a group consisting of combinations thereof.

After forming the first high-k dielectric layer 113, a first annealing process is performed. Wherein the first annealing process can be any one of uniform temperature annealing, spike annealing, and laser annealing, for example, at a temperature in the range of about 400°C to about 900°C, for about 3 seconds to about 40 seconds The preheating is performed for a duration in the range of 950° C. to about 1200° C., and the annealing is performed for a duration in the range of about 1 millisecond to about 20 milliseconds at a peak temperature in the range of 950° C. to about 1200° C. The first annealing process makes the interface of the first high-k dielectric layer 113 and the first dielectric layer 112 mixed with each other.

Then, the first threshold voltage doping process P1 is performed on the exposed first gate trench 111. For a semiconductor element with only one gate trench (first gate trench 111) on the substrate, no It is necessary to use a patterned mask layer, which can be directly doped, thereby adjusting the threshold voltage of the subsequently formed gate structure. For example, if a P-type transistor is selected to be formed in the transistor region, N-type dopant can be doped to the fin structure to adjust the threshold voltage of the gate structure formed in the transistor region. On the contrary, if an N-type transistor is selected to be formed in the transistor region, P-type dopants need to be doped to adjust the threshold voltage. In some of the embodiments, the N-type dopant is, for example, arsenic atom, phosphorus atom, antimony atom or bismuth atom, and the P-type dopant is, for example, boron atom, aluminum atom, gallium atom or indium atom.

As shown in FIGS. 1 to 8 , multiple transistor regions are defined on the substrate 100 , for example, three transistor regions, specifically a first transistor region 110 , a second transistor region 120 and a third transistor region 130 . Of course, two transistor regions can also be defined on the substrate. For the case of three transistor regions, the three transistor regions are transistor regions of the same conductivity type, for example, all are PMOS transistor regions or all are NMOS transistor regions, and the three transistor regions are respectively intended to be gates with different threshold voltages for subsequent fabrication. pole structure. The three transistor regions can also optionally include transistor regions of different conductivity types. For a semiconductor that needs to form three gate trenches, the formation method, for example, is to form three fin structures on the substrate, and then sequentially form a dielectric material layer, a dummy gate material layer and A cap material layer, and then pattern these stacked material layers to form three dummy gate structures, spacers are formed on the side walls of the three dummy gate structures, and spacers are formed on the two sides of the three dummy gate structures. The side forms the source/drain. Afterwards, a contact hole etch stop layer and a dielectric layer are sequentially formed. Then planarize the dielectric layer and the contact hole etching stop layer to expose the tops of the three dummy gates, and remove the three dummy gates to form three gate trenches in the dielectric layer. For example, as shown in FIG. 1 and FIG. 2, a first dummy gate structure 110b, a second dummy gate structure 120b, and a third dummy gate structure 130b are formed on the substrate, wherein the first The dummy gate structure 110b includes a first dielectric layer 112 and a first dummy gate 114, the second dummy gate structure 120b includes a second dielectric layer 122 and a second dummy gate 124, and the third dummy gate The gate structure 130b includes a third dielectric layer 132 and a third dummy gate 134; the first dummy gate 114 of the first dummy gate structure is removed to form the first gate trench 111, and the The second dummy gate 124 of the second dummy gate structure to form the second gate trench 121, and the third dummy gate 134 of the third dummy gate structure is removed to form the third gate groove 131 . Next, as shown in FIG. 3 , a dielectric layer and a high-permittivity dielectric layer are respectively formed in the first gate trench 111, the second gate trench 121 and the third gate trench 131 in sequence, and the dielectric layer at the first The first dielectric layer 112 and the first high-permittivity dielectric layer 113 are in the first gate trench, and the second dielectric layer 122 and the second high-permittivity dielectric layer are located in the second gate trench 121. Layer 123 , located in the third gate trench 131 is a third dielectric layer 132 and a third high-k dielectric layer 133 . After the high-permittivity dielectric layer is formed, a first annealing process is performed on the high-permittivity dielectric layer, so that the interfaces of the high-permittivity dielectric layer and the dielectric layer are mixed with each other.

Next, as shown in FIG. 4 , a first threshold voltage doping process P1 is performed on the exposed first gate trench 111 . Its forming method is, for example, to form a patterned mask layer, such as a first patterned photoresist layer 200, covering the second transistor region 120 and the third transistor region 130, and using the first patterned photoresist layer The etchant layer 200 is used as a mask to perform the first threshold voltage doping process P1 on the exposed first gate trench 111 to form a doped region, thereby adjusting the gate electrode formed in the first transistor region 110 subsequently. The threshold voltage of the structure. Then, as shown in FIG. 5 , the first patterned photoresist layer 200 is removed, and a second patterned photoresist layer 400 covering the first transistor region 110 and the third transistor region 130 is formed. Use the second patterned photoresist layer 400 as a mask to perform the second threshold voltage doping process P2 on the exposed second gate trench 121 (located in the second transistor region 120), forming a doping region to adjust the threshold voltage of the gate structure subsequently formed in the second transistor region 120 . Specifically, the second threshold voltage doping process P2 may choose to use a dopant having the same conductivity type as the first threshold voltage doping process P1 but including a different dopant material. For example, if the first threshold voltage doping process P1 is doped with antimony atoms (N-type dopant), then the second threshold voltage doping process P2 can be doped with bismuth atoms (N-type dopant), so that Compared with the second transistor region 120 and the third transistor region 130 , the gate structure in the first transistor region 110 may have different thresholds, but not limited thereto. Then, as shown in FIG. 6 , the second patterned photoresist layer 400 is removed, and a third patterned photoresist layer 600 covering the first transistor region 110 and the second transistor region 120 is formed. Use the third patterned photoresist layer 600 as a mask to perform the third threshold voltage doping process P3 on the exposed third gate trench 131 (located in the third transistor region 130 ) to form a doping region to adjust the threshold voltage of the gate structure subsequently formed in the third transistor region 130 . The third threshold voltage doping process P3 can also choose to use a dopant that has the same conductivity type as the first threshold voltage doping process P1 but contains a different dopant material, or use the same doping process as the first threshold voltage doping process. P1, the same doping material of the second threshold voltage doping manufacturing process P2, but different from the doping dose of the first threshold voltage doping manufacturing process P1 and the second threshold voltage doping manufacturing process P2, so that the first transistor region 110 , the second transistor region 120 , and the third transistor region 130 have different doping concentrations and different threshold voltages respectively, but are not limited thereto.

In some of the embodiments, after the first threshold voltage doping process, the second annealing process is performed. The second annealing process enables the implanted ions to further perform controllable diffusion, so as to further adjust the threshold voltage of the gate structures subsequently formed in the transistor regions 110 , 120 , 130 .

In some of the embodiments, before the first annealing process, a barrier layer is deposited on the high-k dielectric layer 113 , 123 , 133 . The barrier layer may comprise metal materials such as titanium nitride (TiN), titanium aluminide TiAl, tantalum nitride (TaN). A first barrier layer is deposited on the first high-permittivity dielectric layer 113; a second barrier layer is deposited on the second high-permittivity dielectric layer 123; on the third high-permittivity dielectric layer A third barrier layer is deposited on 133. The TiN layer is formed by atomic layer deposition or physical vapor deposition, and the thickness of the TiN layer is 10 to 30 angstroms. The barrier layer can be used as a barrier to protect the high-k dielectric layers 113 , 123 , 133 . The TiN layer is used to prevent the diffusion of ions generated during the formation of the metal gate to the underlying work function layer.

In some of these embodiments, as shown in FIG. 3 , before the second annealing process, a high-k dielectric protection layer 115 , 125 , 135 is formed on the high-k dielectric layer 113 , 123 , 133 . The protective layers 115, 125, and 135 of the high-k dielectric layer can be amorphous silicon layers or polysilicon layers. The high-k dielectric capping layers 115 , 125 , 135 are removed after the second annealing process. Form a first high-permittivity dielectric layer protective layer 115 on the first high-permittivity dielectric layer 113; form a second high-permittivity dielectric layer protection layer on the second high-permittivity dielectric layer 123 125 : Form a third high-k dielectric layer protection layer 135 on the third high-k dielectric layer 133 . The amorphous silicon layer can be deposited at a temperature below about 530°C. The amorphous silicon layer can be formed by PVD, CVD, ALD, and PECVD methods. The amorphous silicon layer can prevent the high-k dielectric layers 113 , 123 , 133 from deteriorating in the subsequent annealing process. For the embodiment in which an amorphous silicon layer is used in the semiconductor formation method, the second annealing process may be a spike annealing process, and the second annealing process may be, for example: the stable temperature of the spike annealing is 550° C. to 650° C., and the peak temperature range is 950° C. ～1050℃, the heating rate is 150℃/s～220℃/s. The second annealing process makes the amorphous silicon layer absorb oxygen in the high-k dielectric layers 113 , 123 , 133 . In the fin field effect transistor process, a layer of amorphous silicon, that is, an amorphous silicon layer, is deposited after the formation of the high dielectric constant dielectric layer. The amorphous silicon layer absorbs the oxygen element in the high dielectric constant dielectric layer through annealing. Metal gate deposition is then performed after removal of the amorphous silicon layer.

In some of the embodiments, after the second annealing process, before forming the gate, a work function layer is formed in the gate trench, wherein the work function layers of each gate have the same conductivity type and different thicknesses. For example, two transistor regions are formed on the substrate. After the second annealing process, before the first gate 110a is formed, a first work function layer 116 is formed in the first gate trench 111, and a first work function layer 116 is formed in the second gate Before 120 a is formed, a second work function layer 126 is formed in the second gate trench 121 ; wherein the second work function layer 126 and the first work function layer 116 have the same conductivity type and different thicknesses. For example, as shown in FIG. 7, three transistor regions are formed on the substrate, after the second annealing process, before the formation of the first gate 110a, a first work function layer 116 is formed in the first gate trench 111, Before the second gate 120a is formed, a second work function layer 126 is formed in the second gate trench 121, and before the third gate 130a is formed, a third work function layer 126 is formed in the third gate trench 131. Function layer 136 ; wherein the third work function layer 136 , the second work function layer 126 and the first work function layer 116 have the same conductivity type and different thicknesses. The composition of the work function layer is preferably made of different materials according to the applicable transistor type. For example, if the transistor is an N-type transistor, the work function layer may include metal materials with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl ), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or titanium aluminum carbide (TiAlC), etc., but not limited thereto. On the contrary, if the transistor is a P-type transistor, the work function layer includes a metal material with a work function of 4.8eV-5.2eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC).

In some embodiments, the fin structure may be formed by first forming a patterned mask on the substrate, and then transferring the pattern of the patterned mask to the substrate through an etching process. Then, due to the different structural characteristics of tri-gate transistor elements or double-gate fin transistor elements, a part of the patterned mask can be selectively removed or left, and then combined with deposition, chemical mechanical polishing, and etch-back manufacturing processes. The insulating layer is formed, and the base protruding from the insulating layer forms a fin structure. In addition, in another embodiment, the formation method of the fin structure is also selected to first form a patterned hard mask layer on the substrate, and then use an epitaxial manufacturing process to expose the patterned mask layer. A semiconductor layer such as silicon or silicon germanium is grown on the substrate as a corresponding fin structure.

As shown in FIG. 9, the method for forming a semiconductor element according to one embodiment of the present application includes the following steps:

providing a base on which fin structures are formed;

forming a dummy gate structure on the fin structure;

removing dummy gates to form gate trenches;

forming a dielectric layer and a high-k dielectric layer in the gate trench;

forming a barrier layer on the high-k dielectric layer;

performing a first annealing process;

forming a high-k dielectric layer protection layer on the barrier layer;

performing a threshold voltage doping process on the gate trench;

Carrying out the second annealing process;

Remove the high dielectric constant dielectric layer to protect the amorphous silicon layer;

depositing a work function layer;

Depositing metal gates;

A planarization process is performed.

Among them, the substrate is a silicon substrate; the dielectric layer is silicon oxide; the high dielectric constant dielectric layer is hafnium oxide (HfO ₂ ) and hafnium oxide silicate (HfSiO ₄ ); the threshold voltage doping process is P-type Doped boron atoms; work function layer contains titanium aluminide (TiAl); metal gate can include titanium (Ti), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), titanium nitride (TiN), tantalum nitride (TaN), other suitable metal materials and/or combinations thereof.

To sum up, the method for forming the semiconductor device of the present invention mainly utilizes the threshold voltage doping process after the high-k dielectric layer is formed to adjust the threshold voltage of the transistor region. For the coexistence of multiple transistor regions, after the high-k dielectric layer is formed, different threshold voltage doping processes are used, so that the subsequent gate structures formed in each transistor region can have different threshold voltages, forming A semiconductor element with metal gates of different threshold voltages. The forming method of the present invention can be applied to fabricate three or more metal gate structures, so that each metal gate has different critical voltages.

Claims (10)

1. A method for forming a semiconductor element, comprising: provide a base; forming a dielectric layer on the substrate, wherein a first gate trench is formed in the dielectric layer; A first dielectric layer and a first high dielectric constant dielectric layer are formed in the first gate trench; performing a first annealing process on the first high-k dielectric layer; performing a first threshold voltage doping process in the first gate trench; A first gate is formed in the first gate trench. 2 . The method for forming a semiconductor element according to claim 1 , wherein a second annealing process is performed after the first threshold voltage doping process. 3 . 3 . The method for forming a semiconductor device according to claim 2 , wherein before the first annealing process, a barrier layer is deposited on the first high-k dielectric layer. 4 . 4. The method for forming a semiconductor element according to claim 3, characterized in that: A high-k dielectric protection layer is formed on the barrier layer; and the high-k dielectric protection layer is removed after the second annealing process. 5. The method for forming a semiconductor element according to claim 1, characterized in that: forming a first dummy gate structure on the substrate, wherein the first dummy gate structure includes the first dielectric layer and a dummy gate; The dummy gate of the first dummy gate structure is removed to form the first gate trench. 6. The method for forming a semiconductor element according to claim 5, wherein: A fin structure is formed on the substrate, wherein the first dummy gate structure is formed on the fin structure. 7. The method for forming a semiconductor element according to claim 4, further comprising: After the second annealing process, before the first gate is formed, at least one first work function layer is formed in the first gate trench. 8. A method for forming a semiconductor element, comprising: provide a base; forming a dielectric layer on the substrate, wherein a first gate trench and a second gate trench are formed in the dielectric layer; A first dielectric layer and a first high-permittivity dielectric layer are formed in the first gate trench, and a second dielectric layer and a second high-permittivity dielectric layer are formed in the second gate trench. layer; performing a first annealing process on the first high-k dielectric layer and the second high-k dielectric layer; performing a first threshold voltage doping process in the first gate trench; performing a second threshold voltage doping process in the second gate trench; The second threshold voltage doping process is to implant dopants different from the first threshold voltage doping process; forming a first gate within the first gate trench; A second gate is formed in the second gate trench. 9. The method for forming a semiconductor element according to claim 8, wherein: Before the first annealing process, depositing a barrier layer on the first high-k dielectric layer and on the second high-k dielectric layer; After the first threshold voltage doping process and the second threshold voltage doping process, a second annealing process is performed; Before the second annealing process, a high-k dielectric protection layer is formed on the barrier layer; after the second annealing process, the high-k dielectric protection layer is removed. 10. The method for forming a semiconductor element according to claim 9, further comprising: After the second annealing process, before the first gate is formed, a first work function layer is formed in the first gate trench, and before the second gate is formed, the A second work function layer is formed in the second gate trench; wherein the second work function layer and the first work function layer have the same conductivity type and different thicknesses.

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