CN115906726B - Target integrated circuit diagram generating and displaying system - Google Patents
Target integrated circuit diagram generating and displaying system Download PDFInfo
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- CN115906726B CN115906726B CN202310220869.6A CN202310220869A CN115906726B CN 115906726 B CN115906726 B CN 115906726B CN 202310220869 A CN202310220869 A CN 202310220869A CN 115906726 B CN115906726 B CN 115906726B
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Abstract
The invention relates to the technical field of chips, in particular to a target comprehensive circuit diagram generating and displaying system, which comprises the following steps of S1, setting a source code window on a display interface, and presenting a code to be processed in a code file to be processed; s2, acquiring a target comprehensive circuit diagram generation instruction based on a source code window; step S3, acquiring a start code row identifier and an end code row identifier corresponding to the target always block identifier based on a mapping table; step S4, traversing the comprehensive device library, and determining the circuit device information from the start code line identifier corresponding to the target always block identifier to the end code line identifier as target circuit device information; s5, generating a target comprehensive circuit diagram based on the information of all target circuit devices; and S6, presenting the target integrated circuit diagram in a source code window. The invention reduces the complexity of user operation and improves the chip design and debugging efficiency.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a target comprehensive circuit diagram generating and displaying system.
Background
In the conventional chip design verification debugging software, two independent windows corresponding to a source code and a circuit diagram are generally set separately, and a user can check functions such as source code, search and debugging in the source code window to ensure logic correctness of a behavior level. When the structural level logic information of the design is needed to be known, the circuit diagram window needs to be switched to be debugged. The two views are cross-referenced by dragging signals or instances between each other. However, in the debugging process, a user usually only needs to pay attention to a circuit diagram of one of the adjacencies at the same time, while the existing circuit diagrams are all generated by taking a complete module (module) in a chip design, and the opened content of the circuit diagram is an integrated circuit diagram by taking the complete module as a unit. In addition, the comparison reference is switched back and forth between the two windows, so that the complexity of user operation is increased, and the chip design and debugging efficiency is reduced. Therefore, how to improve the technology for generating and displaying the target integrated circuit diagram, reduce the complexity of user operation, and improve the chip design and debugging efficiency is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a target comprehensive circuit diagram generating and displaying system, which reduces the operation complexity of a user and improves the chip design and debugging efficiency.
According to one aspect of the invention, a target integrated circuit diagram generating and displaying system is provided, which comprises a code file to be processed, an integrated device library, a mapping table, a display interface, a memory and a processor, wherein the memory stores a computer program, and the code file to be processed comprises a code file identifier, a plurality of lines of codes and a code line identifier corresponding to each line of codes; the comprehensive device library comprises a plurality of circuit device records which are comprehensively generated based on the code files to be processed, and each circuit device record comprises circuit device information, code file identification information to be processed corresponding to the circuit device information, and a start code row identification and an end code row identification corresponding to the circuit device information in the corresponding code files to be processed; the mapping table comprises an always block identifier and a start code row identifier and an end code row identifier corresponding to the always block identifier in the code file to be processed; when the processor executes the computer program, the following steps are implemented:
step S1, setting a source code window on the display interface, and presenting the to-be-processed codes in the to-be-processed code file in the source code window, wherein the to-be-processed codes comprise at least one always block.
And S2, acquiring a target comprehensive circuit diagram generation instruction based on the source code window, wherein the target comprehensive circuit diagram generation instruction comprises a target always block identifier.
And step S3, acquiring a start code row identifier and an end code row identifier corresponding to the target always block identifier based on the mapping table.
And S4, traversing the comprehensive device library, and determining the circuit device information from the start code line identifier corresponding to the target always block identifier to the end code line identifier within the range from the start code line identifier to the end code line identifier corresponding to the target always block identifier as target circuit device information.
And S5, generating a target comprehensive circuit diagram based on the information of all the target circuit devices.
And step S6, the target comprehensive circuit diagram is presented in the source code window.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the target comprehensive circuit diagram generating and displaying system provided by the invention can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects:
the invention can only extract the target integrated circuit diagram corresponding to the always block for presentation instead of presenting the complex circuit diagram of the whole module, and the target integrated circuit diagram and the source code are positioned in the same window, thereby avoiding switching, reducing the operation complexity of a user and improving the design and debugging efficiency of the chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart for generating and displaying a target integrated circuit diagram provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of source code of a module included in a code file to be processed according to an embodiment of the present invention;
FIG. 3 is a comprehensive circuit diagram corresponding to an entire module generated based on the prior art;
fig. 4 is a schematic diagram of a target integrated circuit generated and displayed according to the present invention according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a target integrated circuit diagram generating and displaying system, which comprises a to-be-processed code file, an integrated device library, a mapping table, a display interface, a memory and a processor, wherein the memory is used for storing a computer program, the to-be-processed code file comprises a code file identifier, a plurality of lines of codes and code line identifiers corresponding to each line of codes, and the codes in the to-be-processed code file are Verilog codes as an example. The comprehensive device library comprises a plurality of circuit device records which are comprehensively generated based on the code files to be processed, and each circuit device record comprises circuit device information, code file identification information to be processed corresponding to the circuit device information, and a start code row identification and an end code row identification corresponding to the circuit device information in the corresponding code files to be processed. It should be noted that, one circuit device information may correspond to one line of codes or may correspond to multiple lines of codes in the to-be-processed code file, and in the synthesis process, code lines defined in a module (module) and located outside an always block for declaring input and output may also be required, but only a start code line identifier and an end code line identifier recorded in the always block are required in the circuit device record. The mapping table includes an always block identifier and a start code line identifier and an end code line identifier corresponding to the always block identifier in the code file to be processed, and it can be understood that the mapping table also includes code file identifier information to be processed, and a correspondence relationship between the always block identifier and the code file identifier to be processed can be obtained, and as an example, the always block identifier can be directly associated with the code file identifier to be processed. When the processor executes the computer program, as shown in fig. 1, the following steps are implemented:
step S1, setting a source code window on the display interface, and presenting the to-be-processed codes in the to-be-processed code file in the source code window, wherein the to-be-processed codes comprise at least one always block.
By way of example, the code to be processed is Verilog code, the always block is a process block in Verilog code,
and S2, acquiring a target comprehensive circuit diagram generation instruction based on the source code window, wherein the target comprehensive circuit diagram generation instruction comprises a target always block identifier.
The code to be processed is a chip design code, and the target always block is an always block which needs to be debugged in the chip design or chip verification process.
And step S3, acquiring a start code row identifier and an end code row identifier corresponding to the target always block identifier based on the mapping table.
And S4, traversing the comprehensive device library, and determining the circuit device information from the start code line identifier corresponding to the target always block identifier to the end code line identifier within the range from the start code line identifier to the end code line identifier corresponding to the target always block identifier as target circuit device information.
All device information corresponding to the target always block can be extracted through the step S4.
And S5, generating a target comprehensive circuit diagram based on the information of all the target circuit devices.
It can be understood that the target integrated circuit diagram only comprises all device information corresponding to the target always blocks, and is not information of the whole module, so that the structure is simpler, and the circuit composition of the target always blocks can be clearly displayed.
And step S6, the target comprehensive circuit diagram is presented in the source code window.
The source code of the target always block and the target comprehensive circuit diagram corresponding to the target always block can be displayed in the same window through the step S6, the window does not need to be switched, the operation complexity of a user is reduced, and therefore the debugging efficiency can be improved.
As an example, the system comprises a preset synthesis tool, an existing synthesis tool or synthesis algorithm all falling within the scope of the invention, when the processor executes the computer program, the following steps are also implemented:
step S10, traversing the code file to be processed, and extracting each section of logic code in the code file to be processed, and a start code row identifier and an end code row identifier corresponding to each section of logic code.
And step S20, integrating each section of logic code based on the preset integration tool to generate circuit device information, wherein the circuit device information comprises a circuit device, and corresponding input information and output information.
Step S30, generating a corresponding circuit device record based on each circuit device information, the identification information of the code file to be processed corresponding to each circuit device information, and the start code line identification and the end code line identification corresponding to each circuit device information in the corresponding code file to be processed.
And step S40, generating the comprehensive device library based on all the circuit device records.
It should be noted that, the present invention extracts the circuit device information corresponding to each section of logic code in the code file to be processed, and records the corresponding start code line identifier and end code line identifier, and does not directly integrate the whole module, but it can be understood that if there is a need to display the whole module, the codes corresponding to the whole module are also integrated to generate the corresponding integrated circuit, which is not limited by the present invention.
The present invention can acquire the target integrated circuit diagram generation instruction in various ways, and the following description is made by two embodiments:
embodiment one,
As an example, the step S2 includes:
and S21, acquiring a code line identifier corresponding to the mouse position in real time.
And S22, when the code line identifications corresponding to the mouse positions are continuously located in the range from the start code line identifications to the end code line identifications corresponding to the same always block, and the continuous time exceeds a preset time threshold, determining the always block identifications corresponding to the mouse positions as target always block identifications.
As an example, the preset time threshold set by each always block may be the same, and may be set to 3 seconds, for example. A corresponding time threshold may also be set for each of the blocks according to the size of the blocks, the time threshold being proportional to the size of the blocks. Setting the preset time threshold can avoid false triggering.
And S23, generating the target comprehensive circuit diagram generation instruction based on the target always block identifier.
Through steps S21-S23, the user only needs to move the mouse in the source code window to trigger the generation of the target integrated circuit diagram, and it can be understood that when the mouse moves to another always block and the code line identifier corresponding to the mouse position is continuously located in the range from the start code line identifier corresponding to the same always block to the end code line identifier, and the continuous time exceeds the preset time threshold, another target integrated circuit diagram corresponding to the always block is generated and displayed in the source code window. When the mouse is continuously positioned outside the always block for a long time, the target integrated circuit diagram disappears, so that the target integrated circuit diagram can be updated or disappear along with the movement of the mouse.
Embodiment II,
As an example, the step S2 includes:
step S201, a code line identifier corresponding to a selected position of a mouse is obtained.
The mouse selection mode can be specifically that the mouse is double-clicked, the mouse is clicked or a telescopic selection frame is arranged, and the position is selected by operating the mouse.
Step S202, if a code line identifier corresponding to a selected position of the mouse is located in a range from a start code line identifier corresponding to a first always block to an end code line identifier, determining the identifier of the first always block as a target always block identifier.
It is understood that the first always block is any one always block in the code file to be processed.
And step 203, generating the target comprehensive circuit diagram generating instruction based on the target always block identifier.
After the target integrated circuit diagram is presented, if the selection operation is performed on another one of the always blocks, the target integrated circuit diagram corresponding to the other one of the always blocks is displayed in the source code window. A close button of the target integrated circuit map may also be provided to manually close the target integrated circuit map.
As an example, the step S5 includes:
step S51, determining a connection relationship between the target circuit devices based on the circuit devices corresponding to all the target circuit device information and the corresponding input information and output information.
It will be appreciated that if the output of one circuit device is the same as the input of another circuit device, there is a connection relationship, and therefore, the connection relationship between the target circuit devices can be determined based on the circuit devices corresponding to all the target circuit device information and the corresponding input information and output information.
And step S52, connecting the target circuit devices based on the connection relation among the target circuit devices to generate the target comprehensive circuit diagram.
As an example, the step S6 includes:
and step S61, determining the area which does not display codes in the source code window currently as a candidate area.
And step S62, determining a candidate area which can display the target comprehensive circuit diagram and is nearest to a target always block in the candidate area as a target display area.
And step S63, presenting the target comprehensive circuit diagram in the target display area.
In step S63, the target integrated circuit diagram may be specifically presented in the target display area in an embedded or suspended manner. The existing manner of embedding or suspending the image in the window will all fall within the protection scope of the present invention, and will not be described herein.
For further explanation of the present invention, as will be shown by way of a specific example, FIG. 2 is a Verilog code of a design module in a code file to be processed, which includes 3 blocks of always, each of which is labeled with a code line identifier, and the target always blocks are always blocks corresponding to 13-20 lines.
Fig. 3 shows a circuit diagram generated based on the prior art and obtained by abstracting and integrating the whole module of fig. 2, and as can be seen from fig. 3, the contents of the whole module are shown together, and it is difficult to distinguish which circuit device corresponds to which always block. According to the example of the invention, the source codes are displayed in the source code window, and the corresponding objective comprehensive circuit diagram of the corresponding always blocks of 13-20 rows can be displayed in the source code window by selecting the corresponding always blocks of 13-20 rows, as shown in the example of fig. 4, the circuit structure of the corresponding always blocks of 13-20 rows can be clearly displayed in fig. 4, and the corresponding objective comprehensive circuit diagram and the source codes can be directly displayed in the same window. It should be noted that, depending on the application requirements, more detailed information may be shown near each circuit device in the figure.
According to the embodiment of the invention, only the target integrated circuit diagram corresponding to the always block can be extracted for presentation instead of presenting the complex circuit diagram of the whole module, and the target integrated circuit diagram and the source code are positioned in the same window, so that switching is avoided, the operation complexity of a user is reduced, and the chip design and debugging efficiency is improved.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (8)
1. A target integrated circuit diagram generating and displaying system is characterized in that,
the device comprises a code file to be processed, a comprehensive device library, a mapping table, a display interface, a memory for storing a computer program and a processor, wherein the code file to be processed comprises a code file identifier, a plurality of lines of codes and a code line identifier corresponding to each line of codes; the comprehensive device library comprises a plurality of circuit device records which are comprehensively generated based on the code files to be processed, and each circuit device record comprises circuit device information, code file identification information to be processed corresponding to the circuit device information, and a start code row identification and an end code row identification corresponding to the circuit device information in the corresponding code files to be processed; the mapping table comprises an always block identifier and a start code row identifier and an end code row identifier corresponding to the always block identifier in the code file to be processed; when the processor executes the computer program, the following steps are implemented:
step S1, setting a source code window on the display interface, and presenting a to-be-processed code in a to-be-processed code file in the source code window, wherein the to-be-processed code comprises at least one always block;
s2, acquiring a target comprehensive circuit diagram generation instruction based on the source code window, wherein the target comprehensive circuit diagram generation instruction comprises a target always block identifier;
step S3, acquiring a start code row identifier and an end code row identifier corresponding to the target always block identifier based on the mapping table;
step S4, traversing the comprehensive device library, and determining circuit device information from the start code line identification corresponding to the target always block identification to the end code line identification within the range from the start code line identification to the end code line identification of all the start code line identification and the end code line identification as target circuit device information;
s5, generating a target comprehensive circuit diagram based on the information of all target circuit devices;
and step S6, the target comprehensive circuit diagram is presented in the source code window.
2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the system comprises a preset synthesis tool, which when executed by the processor, further implements the steps of:
step S10, traversing the code file to be processed, and extracting each section of logic code in the code file to be processed, and a start code row identifier and an end code row identifier corresponding to each section of logic code;
step S20, integrating each section of logic code based on the preset integration tool to generate circuit device information, wherein the circuit device information comprises a circuit device, and corresponding input information and output information;
step S30, generating a corresponding circuit device record based on each circuit device information, the identification information of the code file to be processed corresponding to each circuit device information, and the start code line identification and the end code line identification corresponding to each circuit device information in the corresponding code file to be processed;
and step S40, generating the comprehensive device library based on all the circuit device records.
3. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the step S2 includes:
s21, acquiring a code line identifier corresponding to a mouse position in real time;
step S22, when the code line identifications corresponding to the mouse positions are continuously located in the range from the start code line identifications to the end code line identifications corresponding to the same always block, and the continuous time exceeds a preset time threshold, determining the always block identifications corresponding to the mouse positions as target always block identifications;
and S23, generating the target comprehensive circuit diagram generation instruction based on the target always block identifier.
4. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the step S2 includes:
step S201, acquiring a code line identifier corresponding to a selected position of a mouse;
step S202, if a code line identifier corresponding to a selected position of a mouse is located in a range from a start code line identifier corresponding to a first always block to an end code line identifier, determining the identifier of the first always block as a target always block identifier;
and step 203, generating the target comprehensive circuit diagram generating instruction based on the target always block identifier.
5. The system of claim 2, wherein the system further comprises a controller configured to control the controller,
the step S5 includes:
step S51, determining the connection relation between the target circuit devices based on the circuit devices corresponding to all the target circuit device information and the corresponding input information and output information;
and step S52, connecting the target circuit devices based on the connection relation among the target circuit devices to generate the target comprehensive circuit diagram.
6. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the step S6 includes:
step S61, determining the area which does not display codes in the source code window currently as a candidate area;
step S62, determining a candidate area which can display the target comprehensive circuit diagram and is nearest to a target always block in the candidate area as a target display area;
and step S63, presenting the target comprehensive circuit diagram in the target display area.
7. The system of claim 6, wherein the system further comprises a controller configured to control the controller,
in step S63, the target integrated circuit diagram is presented in the target display area in an embedded or suspended manner.
8. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the code in the code file to be processed is Verilog code.
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| US7165231B2 (en) * | 2000-12-18 | 2007-01-16 | Yardstick Research, Llc | Method and system for incremental behavioral validation of digital design expressed in hardware description language |
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| DE102018003142A1 (en) * | 2017-12-13 | 2019-06-13 | The Mathworks, Inc. | Automatic setting of multitasking configurations for a code checking system |
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| JPH09160949A (en) * | 1995-12-07 | 1997-06-20 | Hitachi Ltd | Design supporting method in mixed system of hardware and software |
| CN112817673A (en) * | 2021-01-07 | 2021-05-18 | 北京芯愿景软件技术股份有限公司 | Information navigation system and method |
| CN114548003A (en) * | 2022-01-27 | 2022-05-27 | 中国科学院微电子研究所 | VerilogRTL code reinforcing method and related equipment |
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