CN115881728A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method comprising: etching the side wall of the initial channel layer to form a channel layer, forming a groove between two adjacent sacrificial layers, and enabling the side wall of the channel layer exposed by the groove to be sunken relative to the side wall of the sacrificial layer; forming a dielectric wall in the opening and the groove; after the dielectric wall is formed, forming an interlayer dielectric layer and a gate opening in the interlayer dielectric layer on the substrate, wherein the gate opening is positioned on the side wall and the top surface of part of the initial composite layer and exposes part of the sacrificial layer; removing the exposed sacrificial layer from the gate opening, forming a gate trench between the adjacent channel layers and between the channel layers and the dielectric wall, and forming a composite layer by using the gate trench and the channel layers; and forming a grid electrode in the grid opening and the grid groove, wherein the grid electrode surrounds the channel layer, so that the control capability of the grid electrode on the channel is improved, and the performance of the device is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In the existing semiconductor field, a fin field effect transistor (FinFET) is an emerging multi-gate device, and compared with a planar metal-oxide semiconductor field effect transistor (MOSFET), the FinFET has stronger short channel suppression capability and stronger working current, and is now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor dimension is reduced to below a few nanometers, after the size of the FinFET itself is reduced to the limit, no matter the fin distance, the short channel effect, the leakage and the material limit cause the transistor manufacture to become a risk-down element, and even the physical structure cannot be completed.

Gate-all-around (GAA) devices are becoming a new direction for research and development in the industry. The technology is characterized in that four sides of a channel are wrapped by a grid electrode, a source electrode and a drain electrode are not contacted with a substrate any more, and the basic structure and the function of the MOSFET are realized after a plurality of linear (which can be understood as a stick shape) or flat plate-shaped and sheet-shaped source electrodes and drain electrodes are transversely distributed perpendicular to the grid electrode. The design has solved various problems that bring after the grid interval size reduces to a great extent, including capacitive effect etc. in addition the channel is wrapped up by the grid four sides, therefore the channel current is also more smooth and easy than the trilateral parcel of FinFET.

As semiconductor technology develops more deeply, smaller spacing between NFET and PFET devices within a standard cell is required. However, for finfet and wrap-around gates, the process limits the spacing between N-type and P-type devices. To extend the scalability of the device, the forkshet device is considered a natural extension of the wrap-around gate. The channel of the forkshet device is controlled by a fork gate structure, as compared to a wrap-around gate device, by introducing a "dielectric wall" between the PMOS and NMOS devices prior to gate patterning that physically isolates the P-gate trench from the N-gate trench, allowing tighter N-to-P spacing, scalability with better area and performance.

However, the technology of the forkshet device is still imperfect and needs to be further improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the semiconductor structure.

In order to solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate; the composite layer comprises a plurality of layers of overlapped gate grooves on the substrate, a channel layer between adjacent gate grooves and a groove on the side wall of the channel layer, and the side wall of the channel layer exposed by the groove is sunken relative to the side wall of the gate groove; a dielectric wall located within the opening and the recess adjacent to the opening; the gate opening is positioned on the interlayer dielectric layer on the substrate and in the interlayer dielectric layer, and the gate opening is positioned on the side wall and the top surface of part of the composite layer; and the grid electrode is positioned in the grid opening and the grid groove and surrounds the channel layer.

Optionally, the composite layer further comprises a bottom structure, and the bottom structure is located at the bottom of the composite layer.

Optionally, the dielectric wall and the sidewall of the channel layer have a gap; the gate is also located in the void.

Optionally, the size of the gap in a direction perpendicular to the sidewall of the opening is in a range of 1 nm to 3 nm.

Optionally, the size of the groove in the direction perpendicular to the opening sidewall ranges from 1 nm to 3 nm.

Optionally, the substrate further comprises an isolation layer located on the substrate and in the opening, the isolation layer is located on the sidewall of the bottom structure and below the dielectric wall, and a top surface of the isolation layer is flush with a top surface of the bottom structure.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: forming a substrate and two initial composite layers which are mutually separated on the substrate, wherein an opening is formed between the two initial composite layers, and each initial composite layer comprises a plurality of overlapped sacrificial layers positioned on the substrate and an initial channel layer positioned between two adjacent sacrificial layers; etching the side wall of the initial channel layer to form a channel layer, forming a groove between two adjacent sacrificial layers, and enabling the side wall of the channel layer exposed by the groove to be sunken relative to the side wall of the sacrificial layer; forming a dielectric wall in the opening and the groove; after the dielectric wall is formed, forming an interlayer dielectric layer and a gate opening in the interlayer dielectric layer on the substrate, wherein the gate opening is positioned on the side wall and the top surface of part of the initial composite layer and exposes part of the sacrificial layer; removing the exposed sacrificial layer from the gate opening, forming a gate trench between the adjacent channel layers and between the channel layers and the dielectric wall, and forming a composite layer by using the gate trench and the channel layers; and forming a grid electrode in the grid opening and the grid groove, wherein the grid electrode surrounds the channel layer.

Optionally, after forming the gate trench and before forming the gate, the method further includes: etching the dielectric wall to form a gap between the dielectric wall and the side wall of the channel layer; the gate is also located in the void.

Optionally, the process of performing etching treatment on the dielectric wall includes a wet etching process.

Optionally, the initial composite layer further comprises a bottom structure, and the bottom structure is located at the bottom of the initial composite layer.

Optionally, after forming the initial composite layer and before forming the dielectric wall, the method further includes: and forming an isolation layer on the substrate and in the opening, wherein the isolation layer is positioned on the side wall of the bottom structure, and the top surface of the isolation layer is flush with the top surface of the bottom structure.

Optionally, the method for forming the dielectric wall includes: forming a dielectric material layer on the surface of the substrate, wherein the dielectric material layer is also positioned on the side wall and the surface of the initial composite layer and fills the opening and the groove adjacent to the opening; forming a patterned layer on the surface of the dielectric material layer, the patterned layer exposing the substrate surface and the dielectric material layer on the top surface of the initial composite layer; and etching the dielectric material layer by taking the patterning layer as a mask until the top surface of the initial composite layer, the surface of the substrate, the channel layer and the side wall of the sacrificial layer are exposed.

Optionally, the method for forming the gate opening includes: forming a dummy gate on the substrate, wherein the dummy gate is positioned on the side wall and the surface of part of the initial composite layer and positioned at the top of the dielectric wall; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is positioned on the side wall of the pseudo grid and exposes out of the top surface of the pseudo grid; and removing the pseudo grid electrode, and forming the grid opening in the interlayer dielectric layer.

Optionally, the forming process of the groove includes one or a combination of a dry etching process and a wet etching process.

Optionally, the material of the dielectric wall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

Optionally, the substrate includes a first region and a second region, the composite layer being located in the first region, the method further comprising: forming a second composite layer on the second region, the second composite layer including a number of layers of overlapping second gate trenches on the second region and a second channel layer between adjacent second gate trenches; the gate opening is also positioned on part of the side wall and the top surface of the second composite layer; the gate is also located in the second gate trench and surrounds the second channel layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, the initial channel layer is etched to form a groove between two adjacent sacrificial layers, the side wall of the channel layer exposed by the groove is recessed relative to the side wall of the sacrificial layer, after the dielectric wall is formed in the opening and the groove adjacent to the opening, part of the dielectric wall comprises a protruding part extending towards the side wall of the channel layer, and when a uniform grid material layer is formed on the surface of the channel layer, the protruding part provides the grid material layer to fill a redundant space, so that the mutual combination state between the grid material layer and the surface of the channel layer is improved, the control capability of a grid on the channel is favorably improved, and the performance of a device is further improved.

Further, after the gate trench is formed, wet etching is carried out on the dielectric wall, so that a gap is formed between the dielectric wall and the side wall of the channel layer; the grid is also positioned in the gap, so that the grid surrounds the channel layer on four sides, the control capability of the grid on the channel is improved, and the performance of the device is improved.

In the structure of the semiconductor device provided by the technical scheme of the invention, the improvement of the mutual combination state between the grid material layer and the surface of the channel layer is beneficial to improving the control capability of the grid to the channel, thereby improving the performance of the device.

Further, a gap is formed between the dielectric wall and the side wall of the channel layer; the grid is also positioned in the gap, so that the grid surrounds the channel layer on four sides, the control capability of the grid on the channel is improved, and the performance of the device is improved.

Drawings

Fig. 1 to 4 are schematic structural diagrams of a semiconductor structure forming process;

FIGS. 5-13 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention;

fig. 14 to 15 are schematic structural views corresponding to steps in a semiconductor structure forming method according to another embodiment of the invention.

Detailed Description

As described in the background, the performance of semiconductor devices formed in the prior art is subject to improvement. The description will be made with reference to the structure of a semiconductor.

Fig. 1-4 are cross-sectional views illustrating a semiconductor structure formation process.

Referring to fig. 1 and 2, fig. 2 is a top view, and fig. 1 is a schematic cross-sectional view along XY direction of fig. 2, providing an initial substrate (not shown); forming a composite layer (not shown) on the initial substrate, wherein the composite layer comprises a plurality of overlapped initial sacrificial layers (not shown) and an initial channel layer (not shown) positioned between two adjacent initial sacrificial layers; forming a side wall structure on the surface of the composite layer, wherein the side wall structure comprises two side walls 100 which are separated from each other; etching the composite layer and the initial substrate by using the sidewall structure as a mask to form a substrate 101 and two mutually discrete composite layers 102 on the substrate 101, wherein an opening 103 is formed between the two composite layers 102, and the composite layers 102 comprise a bottom structure 104 located on the substrate 101, a plurality of overlapped sacrificial layers 105 located on the bottom structure 104, and a channel layer 106 located between two adjacent sacrificial layers 105; a first isolation structure 107 is formed on the substrate 101 and within the opening 103, a top surface of the first isolation structure 107 being flush with a top surface of the bottom structure 104.

Referring to fig. 3, after the first isolation structure 107 is formed, a dielectric wall 108 is formed in the opening 103.

Referring to fig. 4, the spacers 100 and the sacrificial layer 105 are removed, and a gate trench (not shown) is formed between adjacent channel layers 106; a gate 109 is formed on the substrate, the gate 109 being located in the trench and surrounding the channel layer 104.

The method is used for forming a Forksheet device, the composite layer 102 on the two sides of the dielectric wall 108 is used for forming a PMOS device and an NMOS device respectively, the dielectric wall 108 is used for isolating the NMOS device from the PMOS device, and compared with a surrounding type grid device, the distance between an N-type device and a P-type device can be greatly shortened, and the density of the devices is improved. However, compared to the surrounding gate device in which the gate wraps the channel on four sides, the forkset gate only wraps the channel on three sides, and the surface of the channel layer 104 and the dielectric wall 108 form a corner a (as shown in fig. 4), when the gate trench is filled with a material, the corner a is not favorable for filling the gate material in the gate trench, so that the gate cannot wrap the channel well, and further is not favorable for improving the control capability of the gate on the channel.

In order to solve the above problems, in a method for forming a semiconductor structure provided by the present invention, the initial channel layer is etched to form a groove between two adjacent sacrificial layers, a sidewall of the channel layer exposed by the groove is recessed with respect to a sidewall of the sacrificial layer, after a dielectric wall is formed in the opening and the groove adjacent to the opening, a part of the dielectric wall includes a protruding portion extending toward the sidewall of the channel layer, and when a uniform gate material layer is formed on a surface of the channel layer, the protruding portion provides the gate material layer with a filling redundant space, so that a mutual bonding state between the gate material layer and the surface of the channel layer is improved, which is beneficial to improving the control capability of the gate on the channel, and further improves the performance of the device.

In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.

Fig. 5 to 13 are schematic structural diagrams corresponding to steps in a semiconductor structure forming method according to an embodiment of the invention.

Referring to fig. 5 and fig. 6, fig. 6 is a schematic diagram of a top view structure of fig. 5, fig. 5 is a schematic diagram of a cross-sectional structure along direction DD1 of fig. 6, a substrate 200 and two mutually separated initial composite layers 201 on the substrate 200 are formed, an opening 202 is formed between the two initial composite layers 201, and the initial composite layers 201 include several overlapped sacrificial layers 203 on the substrate 200 and an initial channel layer 204 between two adjacent sacrificial layers 203.

In this embodiment, the initial composite layer 201 further includes a bottom structure 205, and the bottom structure 205 is located at the bottom of the initial composite layer 201.

In this embodiment, the substrate 200 includes a first region I on which the initial composite layer 201 is located and a second region II. The initial composite layer 201 is used to form a composite layer.

The method of forming the initial composite layer 201 includes: providing an initial substrate (not shown) comprising an initial first region (not shown); forming a composite layer (not shown) on the initial substrate, wherein the composite layer comprises a plurality of overlapped sacrificial material layers (not shown) and a channel material layer (not shown) positioned between two adjacent sacrificial material layers; forming a patterned hard mask layer 206 on the composite layer; etching the composite layer and the initial substrate with the hard mask layer 206 as a mask to form the initial composite layer 201 and the opening 202 on the substrate and the substrate, forming the substrate 200 and the bottom structure 205 on the substrate 200 with the initial substrate, forming a first region I with the initial first region, forming the sacrificial layer 203 with the sacrificial material layer on the initial first region, and forming the initial channel layer 204 with the channel material layer on the initial first region.

The material of the sacrificial material layer 203 is different from the material of the initial channel layer 204. On one hand, an etching process with a larger selection ratio between the sacrificial layer 203 and the initial channel layer 204 is convenient to select when the sacrificial layer 203 is etched subsequently, so that the etching damage of the etching process to the initial channel layer 204 is reduced; on the other hand, when the initial channel layer 204 is etched subsequently, an etching process with a larger selection ratio between the initial channel layer 204 and the sacrificial layer 203 is selected, so that the etching damage of the sacrificial layer 203 in the etching process is reduced.

In this embodiment, the sacrificial layer 203 is made of silicon germanium, and the initial channel layer 204 is made of silicon. In other embodiments, the initial channel layer is made of Ge or GeSi, and the initial sacrificial layer is made of ZnS, znSe, beS, gaP, or the like. Subsequently, the initial channel layer 204 is used to form a channel of the device.

In this embodiment, a second initial composite layer 301 on the second zone II is also formed. The second initial composite layer 301 on the second zone II is used for subsequent formation of a second composite layer.

The second initial composite layer 301 comprises a bottom structure 302, several overlapping sacrificial layers 303 on the bottom structure 302, and a second initial channel layer 304 between the two second sacrificial layers 303. Subsequently, the initial second channel layer 304 is used to form a channel of a second region device.

The method of forming the initial second composite layer 301 includes: the initial substrate further comprises an initial second region (not shown); simultaneously with the formation of the initial composite layer 201, a second region II and a second initial composite layer 301 on the second region II are also formed, the second region II is formed with the initial second region, the second sacrificial layer 303 is formed with the sacrificial material layer on the initial second region, and the second initial channel layer 304 is formed with the channel material layer on the initial second region.

Subsequently, etching the sidewall of the initial channel layer 204 to form a channel layer, forming a groove between two adjacent sacrificial layers 203, wherein the sidewall of the channel layer exposed by the groove is recessed relative to the sidewall of the sacrificial layer 203; dielectric walls are formed within the opening 202 and the recess.

In this embodiment, after forming the initial composite layer 201 and before forming the dielectric wall, the method further includes: an isolation layer 207 is formed over the substrate 200 and within the opening, the isolation layer 207 being located on the bottom structure 205 sidewall, and the isolation layer 207 top surface being flush with the bottom structure 205 top surface.

Referring to fig. 7, the view direction of fig. 7 is the same as that of fig. 6, sidewalls of the initial channel layer 204 are etched to form a channel layer 208, a groove 209 is formed between two adjacent sacrificial layers 203, and the sidewalls of the channel layer 208 exposed by the groove 209 are recessed relative to the sidewalls of the sacrificial layers 203.

The forming process of the groove 209 comprises one or a combination of a dry etching process and a wet etching process. In this embodiment, the forming process of the groove 209 is a dry etching process, and the dry etching process is favorable for forming a better etching morphology.

In this embodiment, the sidewalls of the second initial channel layer 304 are also etched to form a second channel layer 305, a second groove 306 is formed between two adjacent second sacrificial layers 303, and the sidewalls of the second channel layer 305 exposed by the second groove 306 are recessed with respect to the sidewalls of the second sacrificial layers 303.

The size of the groove 209 along the direction perpendicular to the sidewall of the opening 202 ranges from 1 nm to 3 nm.

The forming process of the second groove 306 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the groove 209 and the second groove 306 are formed simultaneously in the same process, so as to reduce the number of processes and the production cost.

Subsequently, dielectric walls are formed in the openings 202 and the recesses 209, and the method for forming the dielectric walls is described with reference to fig. 8 to 9.

Referring to fig. 8, the view direction of fig. 8 is the same as that of fig. 6, a dielectric material layer 210 is formed on the surface of the substrate 200, the dielectric material layer 210 is also located on the sidewall and surface of the initial composite layer 201, and fills the opening 202 and the groove 209 adjacent to the opening 202; a patterned layer 211 is formed on the surface of the dielectric material layer 210, and the patterned layer 211 exposes the dielectric material layer 210 on the surface of the substrate 200 and the top surface of the initial composite layer 201.

The material of the dielectric material layer 210 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the dielectric material layer 210 is silicon nitride. The dielectric material layer 210 is used to form dielectric walls.

In this embodiment, the dielectric material layer 210 is also located on the sidewall of the hard mask layer 206 above the opening 202.

In this embodiment, the patterned layer 211 is only located on the surface of the dielectric material layer 210 on the opening 202, and is used as a mask to form the dielectric wall.

Referring to fig. 9, the view direction of fig. 9 is the same as that of fig. 6, and the dielectric material layer 210 is etched using the patterned layer 211 as a mask until the top surface of the initial composite layer 201, the surface of the substrate 200, and the sidewalls of the channel layer 208 and the sacrificial layer 203 are exposed.

In this embodiment, the top surface of the second initial composite layer 301, the second channel layer 305, and the sidewalls of the second sacrificial layer 303 are also exposed.

The material of the dielectric wall 212 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the dielectric wall 212 is made of silicon nitride.

Subsequently, after the dielectric wall 212 is formed, an interlayer dielectric layer and a gate opening in the interlayer dielectric layer are formed on the substrate 200, where the gate opening is located on a portion of the sidewall and the top surface of the initial composite layer 201 and exposes a portion of the sacrificial layer 203.

And subsequently, forming a second composite layer on the second region II, where the second composite layer includes a plurality of overlapping second gate trenches located on the second region II and a second channel layer located between adjacent second gate trenches.

In this embodiment, the gate opening is also located on a portion of the second composite layer sidewall and the top surface. Please refer to fig. 10 to 12 for a method for forming the gate opening.

Referring to fig. 10 and 11, fig. 10 is a schematic top view of fig. 11, fig. 11 is a schematic cross-sectional view taken along direction DD1 in fig. 10, a dummy gate 213 is formed on the substrate 200, and the dummy gate 213 is located on a portion of the sidewall and surface of the initial composite layer 201 and on the top of the dielectric wall 212; an interlayer dielectric layer 214 is formed on the substrate 200, and the interlayer dielectric layer 214 is located on the side wall of the dummy gate 213 and exposes the top surface of the dummy gate 213.

In this embodiment, the dummy gate 213 is also located on the sidewall and surface of the second initial composite layer 301.

The material of the dummy gate 213 includes silicon. In this embodiment, the dummy gate 213 is made of polysilicon. The dummy gate 213 takes up space for the subsequently formed gate.

Referring to fig. 12, the view direction of fig. 12 is the same as that of fig. 11, the dummy gate 213 is removed, and the gate opening 215 is formed in the interlayer dielectric layer 214; the exposed sacrificial layer 203 is removed from the gate opening 215, and a gate trench 216 is formed between the adjacent channel layer 208 and the dielectric wall 212, so that the gate trench 216 and the channel layer 208 form a composite layer.

In this embodiment, the exposed second sacrificial layer 303 in the gate opening 215 is also removed, and a second gate trench 307 is formed between the adjacent second channel layers 305, so that a second composite layer is formed by the second gate trench 307 and the second channel layers 305.

Referring to fig. 13, a gate 217 is formed in the gate opening 215 and the gate trench 216, and the gate 217 surrounds the channel layer 208.

The forming method of the gate 217 comprises the following steps: forming a gate material layer in the gate opening 215, in the gate trench 216 and on the surface of the interlayer dielectric layer 214; the gate material layer is planarized until the surface of the interlayer dielectric layer 214 is exposed.

In this embodiment, the gate 217 is further located in the second gate trench 307 and surrounds the second channel layer 305.

The material of the gate 217 includes a metal.

The partial dielectric wall 212 includes a protrusion extending toward the sidewall of the channel layer 208, and when a uniform gate material layer is formed on the surface of the channel layer 208, the protrusion gives the gate material layer to fill the redundant space, so that the bonding state between the gate material layer and the surface of the channel layer 208 is improved, which is beneficial to improving the control capability of the gate 217 on the channel, and thus, the performance of the device is improved.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 13, including: a substrate 200; two composite layers on the substrate 200 that are discrete from each other and an opening 202 (shown in fig. 7) between the two composite layers, the composite layers including several overlapping gate trenches 216 (shown in fig. 12) on the substrate 200 and a channel layer 208 between adjacent gate trenches 216 and a recess 209 (shown in fig. 9) in sidewalls of the channel layer 208, the recess 209 exposing sidewalls of the channel layer 208 that are recessed relative to sidewalls of the gate trenches 216; a dielectric wall 212 located within the opening 202 and the recess 209 adjacent to the opening 202; an interlevel dielectric layer 214 (shown in FIG. 10) over the substrate 200 and a gate opening 215 (shown in FIG. 12) in the interlevel dielectric layer 214, the gate opening 215 being located at a portion of the composite layer sidewall and top surface; a gate 217 positioned within the gate opening 215 and the gate trench 216, and the gate 217 surrounding the channel layer 208.

In this embodiment, the substrate 200 includes a first zone I and a second zone II, and the composite layer is located in the first zone I; the second region II has thereon a second composite layer including several layers of overlapping second gate trenches 307 on the second region II and second channel layers 305 between adjacent second gate trenches 307.

In this embodiment, the composite layer further includes a bottom structure 205, and the bottom structure 205 is located at the bottom of the composite layer; the second composite layer further includes a second base structure 205, the second base structure 205 being located at the bottom of the second composite layer.

The groove 209 has a dimension in a direction perpendicular to the sidewall of the opening 202 in a range of 1 nm to 3 nm.

In this embodiment, the semiconductor structure further comprises an isolation layer 207 located on the substrate 200 and within the opening 202, the isolation layer 207 is located on the sidewall of the bottom structure 205 and below the dielectric wall 212, and a top surface of the isolation layer 207 is flush with a top surface of the bottom structure 205.

In this embodiment, the gate 217 is further located in the second gate trench 307 and surrounds the second channel layer 305.

Fig. 14 to fig. 15 are schematic structural diagrams corresponding to steps in a semiconductor structure forming method according to another embodiment of the invention.

With reference to fig. 14 with continued reference to fig. 12, the view direction of fig. 14 is the same as that of fig. 12, after the gate trench 216 is formed and before the gate is formed, the dielectric wall 212 is further etched, so that a gap 400 is formed between the dielectric wall 212 and the sidewall of the channel layer 208.

The size of the voids 400 in a direction perpendicular to the sidewalls of the openings 202 may range from 1 nm to 3 nm.

The process of etching the dielectric walls 212 includes a wet etching process.

In this embodiment, the void 400 may allow a subsequently formed gate to surround the channel layer 208 on four sides. In other embodiments, the voids may not be formed.

Referring to fig. 14, a gate 401 is formed in the gate opening 215 and the gate trench 216, and the gate 401 surrounds the channel layer 208.

The forming method of the gate 401 comprises the following steps: forming a gate material layer in the gate opening 215, in the gate trench 216 and on the surface of the interlayer dielectric layer 214; the gate material layer is planarized until the surface of the interlayer dielectric layer 214 is exposed.

In this embodiment, the gate 401 is further located in the second gate trench 307 and surrounds the second channel layer 305.

The material of the gate 401 includes a metal.

The partial dielectric wall 212 includes a protrusion extending toward the sidewall of the channel layer 208, and when a uniform gate material layer is formed on the surface of the channel layer 208, the protrusion provides the gate material layer with a redundant space to improve the bonding state between the gate material layer and the surface of the channel layer, which is beneficial to improving the control capability of the gate on the channel, and thus improving the performance of the device.

In this embodiment, the gate 401 is also located in the gap 400. The gate 401 is also located in the gap 400, so that the channel layer is surrounded by four sides of the gate, which is beneficial to improving the control capability of the gate on the channel, and further improving the performance of the device.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the method, with reference to fig. 15, including: a substrate 200; two composite layers on the substrate 200 that are discrete from each other and an opening 202 (shown in fig. 7) between the two composite layers, the composite layers including several layers of overlapping gate trenches 216 (shown in fig. 12) on the substrate 200 and channel layers 208 between adjacent gate trenches 216 and recesses 209 in sidewalls of the channel layers 208 (shown in fig. 9), the exposed sidewalls of the channel layers 208 in the recesses 209 being recessed relative to the sidewalls of the gate trenches 216; a dielectric wall 212 located within the opening 202 and the recess 209 adjacent to the opening 202; an interlevel dielectric layer 214 (shown in FIG. 10) over the substrate 200 and a gate opening 215 (shown in FIG. 12) in the interlevel dielectric layer 214, the gate opening 215 being located at a portion of the composite layer sidewall and top surface; a gate 401 located within the gate opening 215 and the gate trench 216, and the gate 401 surrounds the channel layer 208.

The improvement of the mutual combination state between the grid material layer and the surface of the channel layer is beneficial to improving the control capability of the grid to the channel, and further improving the performance of the device.

In this embodiment, the substrate 200 includes a first region I and a second region II, and the composite layer is located in the first region I; the second region II has thereon a second composite layer including several layers of overlapping second gate trenches 307 on the second region II and second channel layers 305 between adjacent second gate trenches 307.

In this embodiment, the composite layer further includes a bottom structure 205, and the bottom structure 205 is located at the bottom of the composite layer; the second composite layer further includes a second base structure 205, the second base structure 205 being located at the bottom of the second composite layer.

The dielectric walls 212 and the sidewalls of the channel layer 208 have voids 400 (as shown in fig. 14); the gate 401 is also located in the void 400. The four sides of the gate surround the channel layer, which is beneficial to improving the control capability of the gate 401 on the channel layer 208, and further improving the performance of the device.

The size of the voids 400 in a direction perpendicular to the sidewalls of the openings 202 may range from 1 nm to 3 nm.

The size of the groove 209 along the direction perpendicular to the sidewall of the opening 202 ranges from 1 nm to 3 nm.

In this embodiment, the semiconductor structure further comprises an isolation layer 207 located on the substrate 200 and within the opening 202, the isolation layer 207 is located on the sidewall of the bottom structure 205 and below the dielectric wall 212, and a top surface of the isolation layer 207 is flush with a top surface of the bottom structure 205.

In this embodiment, the gate 401 is further located in the second gate trench 307 and surrounds the second channel layer 305.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims (16)

1. A semiconductor structure, comprising:

a substrate;

the composite layer comprises a plurality of layers of overlapped gate grooves on the substrate, a channel layer between adjacent gate grooves and a groove on the side wall of the channel layer, and the side wall of the channel layer exposed by the groove is sunken relative to the side wall of the gate groove;

a dielectric wall located within the opening and the recess adjacent to the opening;

the gate opening is positioned on the interlayer dielectric layer on the substrate and in the interlayer dielectric layer, and the gate opening is positioned on the side wall and the top surface of part of the composite layer;

and the grid electrode is positioned in the grid opening and the grid groove and surrounds the channel layer.

2. The semiconductor structure of claim 1, wherein the composite layer further comprises a bottom structure at the bottom of the composite layer.

3. The semiconductor structure of claim 1, wherein said dielectric wall has a void with said channel layer sidewall; the gate is also located in the void.

4. The semiconductor structure of claim 3, wherein the voids have a dimension in a direction perpendicular to the sidewalls of the openings in a range from 1 nanometer to 3 nanometers.

5. The semiconductor structure of claim 1, wherein the recess has a dimension in a direction perpendicular to the sidewalls of the opening in a range from 1 nm to 3 nm.

6. The semiconductor structure of claim 1, further comprising an isolation layer on the substrate and within the opening, the isolation layer located on the bottom structure sidewall and below the dielectric wall, and the isolation layer top surface being flush with the bottom structure top surface.

7. A method of forming a semiconductor structure, comprising:

forming a substrate and two initial composite layers which are mutually separated on the substrate, wherein an opening is formed between the two initial composite layers, and each initial composite layer comprises a plurality of overlapped sacrificial layers positioned on the substrate and an initial channel layer positioned between two adjacent sacrificial layers;

etching the side wall of the initial channel layer to form a channel layer, forming a groove between two adjacent sacrificial layers, and enabling the side wall of the channel layer exposed by the groove to be sunken relative to the side wall of the sacrificial layer;

forming a dielectric wall in the opening and the groove;

after the dielectric wall is formed, forming an interlayer dielectric layer and a gate opening in the interlayer dielectric layer on the substrate, wherein the gate opening is positioned on the side wall and the top surface of part of the initial composite layer and exposes part of the sacrificial layer;

removing the exposed sacrificial layer from the gate opening, forming a gate trench between the adjacent channel layers and between the channel layers and the dielectric wall, and forming a composite layer by using the gate trench and the channel layers; and forming a grid electrode in the grid opening and the grid groove, wherein the grid electrode surrounds the channel layer.

8. The method of forming a semiconductor structure according to claim 7, wherein after forming the gate trench and before forming the gate electrode, further comprising: etching the dielectric wall to form a gap between the dielectric wall and the side wall of the channel layer; the gate is also located in the void.

9. The method of claim 8, wherein the etching the dielectric wall comprises a wet etching process.

10. The method of forming a semiconductor structure of claim 7, wherein the initial composite layer further comprises a bottom structure, the bottom structure being located at a bottom of the initial composite layer.

11. The method of forming a semiconductor structure of claim 10, wherein after forming the initial composite layer and before forming the dielectric wall, further comprising: and forming an isolation layer on the substrate and in the opening, wherein the isolation layer is positioned on the side wall of the bottom structure, and the top surface of the isolation layer is flush with the top surface of the bottom structure.

12. The method of forming a semiconductor structure of claim 7, wherein the method of forming the dielectric wall comprises: forming a dielectric material layer on the surface of the substrate, wherein the dielectric material layer is also positioned on the side wall and the surface of the initial composite layer and fills the opening and the groove adjacent to the opening; forming a patterned layer on the surface of the dielectric material layer, the patterned layer exposing the dielectric material layer on the surface of the substrate and the top surface of the initial composite layer; and etching the dielectric material layer by taking the patterning layer as a mask until the top surface of the initial composite layer, the surface of the substrate, the channel layer and the side wall of the sacrificial layer are exposed.

13. The method of forming a semiconductor structure of claim 7, wherein the method of forming the gate opening comprises: forming a dummy gate on the substrate, wherein the dummy gate is positioned on the side wall and the surface of part of the initial composite layer and positioned at the top of the dielectric wall; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is positioned on the side wall of the pseudo grid and exposes the top surface of the pseudo grid; and removing the pseudo grid electrode, and forming the grid opening in the interlayer dielectric layer.

14. The method of claim 7, wherein the recess forming process comprises one or a combination of a dry etching process and a wet etching process.

15. The method of claim 7, wherein the dielectric wall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

16. The method of forming a semiconductor structure of claim 7, wherein the substrate includes a first region and a second region, the composite layer being located at the first region, the method further comprising: forming a second composite layer on the second region, the second composite layer including a plurality of layers of overlapping second gate trenches on the second region and a second channel layer between adjacent second gate trenches; the gate opening is also positioned on part of the side wall and the top surface of the second composite layer; the gate is also located in the second gate trench and surrounds the second channel layer.

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