CN115881542A

CN115881542A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN115881542A
Application number: CN202111145116.0A
Authority: CN
Inventors: 王路广
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2023-03-31

Abstract

The present application relates to a semiconductor structure and a method of fabricating the same. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a semiconductor substrate, a grid structure and a dielectric layer, a drain region and a source region are formed in the semiconductor substrate, the grid structure is positioned between the source region and the drain region, and the dielectric layer covers the grid structure and the semiconductor substrate; forming a contact hole in the substrate, wherein the contact hole penetrates through the dielectric layer to the source region and/or the drain region; forming a semiconductor connecting structure in at least the contact hole, and forming a contact structure which contacts and covers the surface of the semiconductor connecting structure; and forming a conductive structure on the contact structure. The method and the device can reduce the influence of stress generated when the contact structure is formed on the performance of the device.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to integrated circuit technologies, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

In the integrated circuit manufacturing process, metal silicide is widely used for the contact between a source electrode, a drain electrode and metal, and the contact resistance can be effectively reduced. However, when a metal silicide is formed, stress is generated. Stress can change the mobility of semiconductor carriers, which can affect the performance of semiconductor devices. For example, the stress caused by the formation of metal silicide may increase the saturation current of an NMOS device by 20%.

Disclosure of Invention

Accordingly, the embodiment of the application provides a semiconductor structure and a manufacturing method thereof.

A method of fabricating a semiconductor structure, in one embodiment, comprising:

providing a substrate, wherein the substrate comprises a semiconductor substrate, a grid structure and a dielectric layer, a drain region and a source region are formed in the semiconductor substrate, the grid structure is positioned between the source region and the drain region, and the dielectric layer covers the grid structure and the semiconductor substrate;

forming a contact hole in the substrate, wherein the contact hole penetrates through the dielectric layer to the source region and/or the drain region;

forming a semiconductor connecting structure in at least the contact hole, and forming a contact structure which contacts and covers the surface of the semiconductor connecting structure;

and forming a conductive structure on the contact structure.

In one embodiment, the contact structure passes through the inside and outside of the region where the contact hole is located in the direction perpendicular to the extending direction of the contact hole.

In one embodiment, the forming at least a semiconductor connection structure in the contact hole and a contact structure contacting a surface of the semiconductor connection structure includes:

and forming the semiconductor connecting structure in the contact hole and on the surface of the dielectric layer, and forming the contact structure on the surface of the semiconductor connecting structure.

In one embodiment, the semiconductor connection structure includes a first connection structure and a second connection structure, the forming of the semiconductor connection structure in the contact hole and on the surface of the dielectric layer and the forming of the contact structure on the surface of the semiconductor connection structure include:

epitaxially growing the first connection structure inside the contact hole;

forming a second connecting material layer on the surface of the first connecting structure and the surface of the medium layer;

forming a contact material layer on the surface of the second connecting material layer;

and reacting the contact material layer with part of the second connecting material layer through heat treatment to form the contact structure, wherein the rest of the second connecting material layer forms the second connecting structure.

In one embodiment, the epitaxially growing the first connection structure inside the contact hole includes:

epitaxially growing a first connecting material layer on the basis of the semiconductor substrate at the bottom of the contact hole until the first connecting material layer is filled in and exceeds the contact hole;

and carrying out chemical mechanical grinding on the first connecting material layer based on the dielectric layers on the two sides of the contact hole, removing the first connecting material layer outside the contact hole, and forming the first connecting structure by the residual first connecting material layer.

In one embodiment, the thickness of the second connection material layer is 10% to 50% of the thickness of the first connection structure.

In one embodiment, the forming a second connection material layer on the first connection structure surface and the dielectric layer surface includes:

and forming a second connecting material layer on the surface of the first connecting structure and the surface of the medium layer by a chemical vapor deposition method.

In one embodiment, after the reacting the contact material layer with a portion of the second connection material layer to form the contact structure and the remaining second connection material layer constitutes the second connection structure by the heat treatment, the method further includes:

and removing the residual contact material layer.

In one embodiment, the forming the conductive structure on the contact structure includes:

forming a barrier layer on the surface of the contact structure;

and forming a conductive layer on the surface of the barrier layer.

In one of the embodiments, the first and second electrodes are,

forming a semiconductor connecting structure in the contact hole and on the surface of the dielectric layer, and forming a contact structure on the surface of the semiconductor connecting structure, including:

epitaxially growing a semiconductor connecting material layer on the basis of the semiconductor substrate at the bottom of the contact hole until the semiconductor connecting material layer is filled and covers the surface of the medium layer;

planarizing the semiconductor connecting material layer, removing part of the semiconductor connecting material layer outside the contact hole, and forming the semiconductor intermediate material layer by the residual semiconductor connecting material layer;

forming a contact material layer on the surface of the semiconductor intermediate material layer;

and reacting the contact material layer with part of the semiconductor intermediate material layer through heat treatment to form the contact structure, wherein the rest semiconductor intermediate material layer forms the semiconductor connecting structure.

A semiconductor structure, comprising:

the substrate comprises a semiconductor substrate, a grid structure and a dielectric layer, wherein a source region and a drain region are arranged in the semiconductor substrate, the grid structure is positioned between the source region and the drain region, and the dielectric layer covers the grid structure and the semiconductor substrate;

the contact hole is positioned in the substrate and extends from the dielectric layer to the source region and/or the drain region;

the semiconductor connecting structure is at least positioned in the contact hole and is in contact with the source region and/or the drain region;

the contact structure is contacted with and covers the surface of the semiconductor connecting structure;

a conductive structure on the contact structure.

In one embodiment, the semiconductor connection structure is located in the contact hole and on the surface of the dielectric layer, and the contact structure is located on the surface of the semiconductor connection structure.

In one embodiment, the semiconductor connection structure includes:

the first connecting structure is positioned in the contact hole and is in contact with the source region and/or the drain region;

and the second connecting structure is positioned on the surface of the first connecting structure and the surface of the medium layer.

In one embodiment, the first connection structure fills the contact hole.

In one embodiment, the conductive structure comprises:

the barrier layer is positioned on the surface of the contact structure;

and the conductive layer is positioned on the surface of the barrier layer.

In one embodiment, the barrier layer comprises a titanium nitride layer, the conductive layer comprises a metal layer, the semiconductor connection structure comprises a doped polysilicon layer, and the contact structure comprises a metal silicide layer.

According to the semiconductor structure and the manufacturing method thereof, the conductive channels between the contact structure and the source region and the drain region are isolated by the semiconductor connecting structure, so that the influence of stress generated when the contact structure is formed on the performance of a device can be reduced.

Meanwhile, in some embodiments, in the direction perpendicular to the extending direction of the contact hole, the contact structure penetrates through the inside and the outside of the region where the contact hole is located, so that the contact surface of the conductive structure and the contact structure also penetrates through the inside and the outside of the region where the contact hole is located in the direction, the contact area of the contact structure and the conductive structure is greatly increased, the contact resistance between the contact structure and the conductive structure is effectively reduced, and the power consumption of the device is effectively reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings needed to be used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative efforts.

FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;

FIGS. 2-11 are schematic structural diagrams illustrating a semiconductor structure during fabrication in accordance with one embodiment;

fig. 12-18 are schematic structural diagrams illustrating a semiconductor structure during a fabrication process according to another embodiment.

Description of reference numerals:

100-substrate, 110-semiconductor substrate, 111-source region, 112-drain region, 120-gate structure, 121-gate dielectric layer, 122-polysilicon layer, 123-gate barrier layer, 124-gate metal layer, 130-dielectric layer, 100 a-contact hole, 200-semiconductor connection structure, 210-first connection structure, 220-second connection structure, 221-second connection material layer, 201-semiconductor connection material layer, 202-semiconductor intermediate material layer, 300-contact structure, 301-contact material layer, 400-conductive structure, 410-barrier layer, 420-conductive layer.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the terms "spatial relationship" and "spatial relationship" encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" and "including," or "having," and the like, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.

In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, which includes the steps of:

step S100, providing a substrate 100, wherein the substrate includes a semiconductor substrate 110, a gate structure 120 and a dielectric layer 130, a drain region 112 and a source region 111 are formed in the semiconductor substrate 110, the gate structure 120 is located between the source region 111 and the drain region 112, and the dielectric layer 130 covers the gate structure 120 and the semiconductor substrate 110, as shown in fig. 2;

step S200, forming a contact hole 100a in the substrate 100, wherein the contact hole 100a penetrates through the dielectric layer 130 to the source region 111 and/or the drain region 112, please refer to fig. 3;

step S300, forming a semiconductor connection structure 200 at least in the contact hole 100a, and forming a contact structure 300 contacting and covering the surface of the semiconductor connection structure 200, please refer to fig. 8;

in step S400, a conductive structure 400 is formed on the contact structure 300, please refer to fig. 11.

In step S100, the semiconductor substrate 110 may include, but is not limited to, a silicon substrate. Shallow trench isolation structures STI may be formed in the semiconductor substrate 110. The shallow trench isolation structures STI separate the semiconductor substrate 110 into a plurality of active regions. Each active region is used for forming a semiconductor device such as a MOS transistor. The drain region 112 and the source region 111 are formed in the active region. The active region between the source region 111 and the drain region 112 forms a conductive channel.

Gate structure 120 is located between source region 111 and drain region 112.

As an example, the gate structure 120 may be formed over the semiconductor substrate 110 between the source region 111 and the drain region 112.

Specifically, the gate structure 120 may include a gate dielectric layer 121, a polysilicon layer 122, a gate blocking layer 123, a gate metal layer 124, and the like, which are sequentially formed on the semiconductor substrate 110. The gate dielectric layer 121 may be silicon dioxide (SiO) as a material ₂ ) And the like. The material of the gate blocking layer 123 may be titanium nitride (TiN) or the like. The material of the gate metal layer 124 may be metal tungsten (W) or the like.

Of course, the form of the gate structure 120 is not limited thereto. For example, the gate structure 120 may also be a buried gate structure. At this time, a trench is formed in the active region, a gate structure 120 is formed in the trench, and a source region 111 and a drain region 112 are formed at both sides of the trench.

The dielectric layer 130 may include a plurality of insulating dielectric layer films (not shown) covering the gate structure 120 and the semiconductor substrate 110 for insulation protection. Of course, the dielectric layer 130 may also include an insulating dielectric layer, which is not limited herein.

In step S200, a plurality of contact holes 100a may be formed in the substrate 100 by etching or the like.

In step S300, the semiconductor connection structure 200 is formed at least in the contact hole 100a. That is, the semiconductor connecting structure 200 may be formed only in the contact hole 100a, or may be formed in the contact hole 100a and on the surface of the dielectric layer 130 outside the contact hole 100a (see fig. 8).

The semiconductor connection structure 200 is a semiconductor structure that can be doped to conduct electricity well. Which has the same doping type as the source region 111 and the drain region 112. So that good conductive contact can be made with the source region 111 and the drain region 112. As an example, the semiconductor connection structure 200 may use the same material (e.g., silicon) as the semiconductor substrate 110 and have the same doping concentration as the source region 111 and the drain region 112.

The contact structure 300 contacts the surface of the semiconductor connection structure 200 so as to make a good conductive contact therewith. Specifically, the contact structure 300 may be a metal silicide (e.g., cobalt silicide (CoSi)), or the like.

In step S400, the material of the conductive structure 400 may include a metal material (e.g., metal W). The conductive structure 400 and the semiconductor connection structure 200 are connected through the contact structure 300, so that contact resistance can be effectively reduced.

In the present embodiment, since the contact structure 300 is isolated from the conductive channel between the source region 111 and the drain region 112 by the semiconductor connection structure 200, the influence of the stress generated when the contact structure 300 is formed on the device performance can be reduced.

In one embodiment, the contact structure 300 formed in step S300 passes through the inside and outside of the region where the contact hole is located, in a direction perpendicular to the extending direction of the contact hole. At this time, the contact surface of the conductive structure 400 and the contact structure 300 can also pass through the inside and outside of the region where the contact hole is located in the direction, so that the contact area of the contact structure 300 and the conductive structure 400 is greatly increased, the contact resistance between the contact structure 300 and the conductive structure 400 is effectively reduced, and the power consumption of the device is effectively reduced.

In one embodiment, step S300 includes:

in step S300a, a semiconductor connection structure 200 is formed in the contact hole 100a and on the surface of the dielectric layer 130, and a contact structure 300 is formed on the surface of the semiconductor connection structure 200.

At this time, the semiconductor connection structure 200 is simultaneously formed on the surface of the dielectric layer 130 inside the contact hole 100a and outside the contact hole 100a, and the contact structure 300 is formed on the surface of the semiconductor connection structure 200. Therefore, it is possible to increase the contact area of the contact structure 300 and the semiconductor connection structure 200 while increasing the contact area of the contact structure 300 and the conductive structure 400, thereby reducing the contact resistance therebetween.

Therefore, the present embodiment can further reduce the contact resistance between the conductive structure 400 and the semiconductor connection structure 200, thereby further reducing the device power consumption.

In one embodiment, referring to fig. 8, the semiconductor connection structure 200 includes a first connection structure 210 and a second connection structure 220. The first connection structure 210 and the second connection structure 220 are semiconductor structures doped to have good conductivity. The material and the doping concentration of the two materials may be the same or different.

At this time, step S300a includes:

step S311, epitaxially growing a first connection structure 210 in the contact hole 100a, please refer to fig. 5;

step S312, forming a second connecting material layer 221 on the surface of the first connecting structure 210 and the surface of the dielectric layer 130, please refer to fig. 6;

step S313, forming a contact material layer 301 on the surface of the second connecting material layer 221, please refer to fig. 7;

in step S314, the contact material layer 301 and a portion of the second connection material layer 221 are reacted by heat treatment to form the contact structure 300, and the remaining second connection material layer 221 forms the second connection structure 220, as shown in fig. 8.

In step S311, the first connection structure 210 is epitaxially grown on the basis of the semiconductor substrate 110 at the bottom of the contact hole 100a (specifically, on the basis of the source region 111 and the drain region 112 at the bottom of the contact hole 100 a). As an example, when the semiconductor substrate 110 is a silicon substrate, the first connection structure 210 may be grown homogeneously on the basis of the silicon substrate.

In step S312, as an example, the second connection material layer 221 may be formed on the surface of the first connection structure 210 and the surface of the dielectric layer 130 by chemical vapor deposition.

Of course, the second connection material layer 221 may be formed by other methods (such as physical vapor deposition), which is not limited herein.

In step S313, the material of the contact material layer 301 may be metal cobalt (Co), titanium (Ti), or the like. It may also be formed on the surface of the second connection material layer 221 by deposition. The contact material layer 301 may be deposited to a thickness of 5nm to 10nm.

In step S314, the heat treatment may specifically include subjecting the structure after the contact material layer 301 is formed to high temperature annealing at 400 to 800 ℃. At this time, the metal material such as Co diffuses into the second connection material layer 221 to react therewith, thereby forming SiCo, coTi, etc. as the contact structure 300.

Meanwhile, the remaining unreacted second connection material layer 221 constitutes the second connection structure 220.

In the present embodiment, the first connection structure 210 and the second connection structure 220 formed through different steps together form the semiconductor connection structure 200, so that the manufacturing process thereof is simpler.

In one embodiment, step S311 includes:

step S311, epitaxially growing a first connection material layer 211 on the basis of the semiconductor substrate 110 at the bottom of the contact hole 100a until the first connection material layer 211 is filled up and exceeds the contact hole 100a, as shown in fig. 4;

in step S312, based on the dielectric layers 130 on the two sides of the contact hole 100a, the first connection material layer 211 is subjected to a chemical mechanical polishing process to remove the first connection material layer 211 outside the contact hole 100a, and the remaining first connection material layer 211 forms the first connection structure 210, please refer to fig. 5.

In step S311, the first connection material layer 211 is epitaxially grown from the semiconductor substrate 110 (specifically, the source electrode 111 and the drain electrode 112) at the bottom of the contact hole 100a.

In step S312, the top film layer of the dielectric layer 130 on both sides of the contact hole 100a may include a polishing stop layer 131, such as a silicon nitride film layer. At this time, the chemical mechanical polishing may be automatically stopped on the top layer (e.g., the silicon nitride film layer) of the dielectric layer 130, thereby removing the first connecting material layer 211 outside the contact hole 100a. The remaining first connection material layer 211 fills the contact hole 100a, thereby constituting the first connection structure 210.

In the present embodiment, the contact hole 100a may be filled in by the first connection structure 210. Therefore, the second connection material layer 221 and the contact material layer 301 formed in the subsequent steps can be formed on flat surfaces, so that the second connection material layer 221 and the contact material layer 301 have uniform thickness and flat surfaces.

In one embodiment, the thickness of the second connection material layer 221 formed in the step S312 is set to 10% to 50% of the thickness of the first connection structure 210 (i.e., the hole depth of the contact hole 100 a). At this time, after a portion of the second connection material layer 221 reacts with the contact material layer 301 in step S314, on one hand, the second connection structure 220 formed by the remaining second connection material layer 221 has a sufficient thickness, and can form a good conductive contact with the contact structure 300 formed by the reaction, thereby effectively reducing power consumption; on the other hand, the thickness of the remaining second connection material layer 221 is not too high to affect the overall thickness of the device.

In one embodiment, after step S314, the method further includes:

in step S315, the remaining contact material layer 301 is removed, please refer to fig. 9.

At this time, in step S400, a material of the conductive structure may be directly deposited on the surface of the contact structure 300, so as to form the conductive structure 400, thereby ensuring stable and reliable performance of the conductive structure 400.

Of course, in some embodiments, the remaining contact material layer 301 may not be removed after step S314. At this time, a material of the conductive structure may be deposited on the surface of the remaining contact material layer 301, thereby forming the conductive structure 400.

In one embodiment, the conductive structure 400 includes a barrier layer 410 and a conductive layer 420. At this time, step S400 includes:

step S410, forming a barrier layer 410 on the surface of the contact structure 300, please refer to fig. 10;

in step S420, a conductive layer 420 is formed on the surface of the barrier layer 410, please refer to fig. 11.

In step S410, a material such as titanium nitride may be deposited on the surface of the contact structure 300 by chemical vapor deposition, so as to form the barrier layer 410.

In step S420, a metal material (e.g., W) may be deposited on the surface of the barrier layer 410 by chemical vapor deposition or sputtering, so as to form the conductive layer 420.

In the present embodiment, by forming the barrier layer 410 between the conductive layer 420 and the contact structure 300, metal atoms in the conductive layer can be effectively prevented from diffusing into the contact structure 300 and affecting the performance thereof.

In one embodiment, step S300a includes:

step S321, epitaxially growing a semiconductor connection material layer 201 on the basis of the semiconductor substrate 110 at the bottom of the contact hole 100a until the semiconductor connection material layer 201 is filled up and covers the surface of the dielectric layer 130, as shown in fig. 12;

step S322, planarizing the semiconductor connection material layer 201, removing a portion of the semiconductor connection material layer 201 outside the contact hole 100a, and forming a semiconductor intermediate material layer 202 by the remaining semiconductor connection material layer 201, please refer to fig. 13;

step S323, forming a contact material layer 301 on the surface of the semiconductor intermediate material layer 202, as shown in fig. 14;

in step S324, the contact material layer 301 is reacted with a portion of the semiconductor intermediate material layer 202 by a thermal process to form the contact structure 300, and the remaining semiconductor intermediate material layer 202 constitutes the semiconductor connection structure 200, as shown in fig. 15.

In step S321, the epitaxially grown semiconductor connecting material layer 201 further extends to the surface of the dielectric layer 130 and covers the surface of the dielectric layer 130.

In step S322, the semiconductor connecting material layer 201 outside the contact hole 100a is only partially removed, and another portion remains on the surface of the dielectric layer 130.

In step S323, a contact material layer 301 is formed on the planarized surface.

In step S324, the remaining semiconductor intermediate material layer 202 includes the semiconductor intermediate material layer 202 located inside the contact hole 100a and the unreacted semiconductor intermediate material layer 202 outside the contact hole 100a.

The semiconductor connection structure 200 formed in the present embodiment is formed by the same process film layer, and thus has good uniformity.

It is understood that the remaining contact material layer 301 may be removed after step S324, please refer to fig. 16. Meanwhile, the subsequent step S400 may include:

step S410, forming a barrier layer 410 on the surface of the contact structure 300, please refer to fig. 17;

in step S420, a conductive layer 420 is formed on the surface of the barrier layer 410, as shown in fig. 18.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in a strict order unless explicitly stated herein, and may be performed in other orders. Moreover, at least a portion of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least a portion of the steps or stages in other steps.

In one embodiment, a semiconductor structure is also provided, including a substrate 100, a contact hole 100a, a semiconductor connection structure 200, a contact structure 300, and a conductive structure 400.

Substrate 100 includes a semiconductor substrate 110, a gate structure 120, and a dielectric layer 130. The semiconductor substrate 110 has a source region 111 and a drain region 112 therein. Gate structure 120 is located between source region 111 and drain region 112. Dielectric layer 130 covers gate structure 120 and semiconductor substrate 110. Contact holes 100a are located in the substrate 100 and extend from the dielectric layer 130 to the source region 111 and/or the drain region 112. The semiconductor connection structure 200 is at least located in the contact hole 100a and contacts the source region 111 and/or the drain region 112.

The contact structure 300 contacts and covers the surface of the semiconductor connection structure 200.

The conductive structure 400 is located on the contact structure 300.

In one embodiment, the semiconductor connection structure 200 is located in the contact hole 100a and on the surface of the dielectric layer 130, and the contact structure 300 is located on the surface of the semiconductor connection structure 200.

In one embodiment, the semiconductor connection structure 200 includes a first connection structure 210 and a second connection structure 220. The first connection structure 210 is located within the contact hole 100a and contacts the source region 111 and/or the drain region 112. The second connection structure 220 is located on the surface of the first connection structure 210 and the surface of the dielectric layer 130.

In one embodiment, the first connection structure 210 fills the contact hole 100a.

In one embodiment, conductive structure 400 includes a barrier layer 410 and a conductive layer 420. Barrier layer 410 is located on the surface of contact structure 300. The conductive layer 420 is located on the surface of the barrier layer 410.

In one embodiment, barrier layer 410 comprises a titanium nitride layer. The conductive layer 420 includes a metal layer. The semiconductor connection structure 200 comprises a doped polysilicon layer. The contact structure 300 includes a metal silicide layer.

For the specific definition of the semiconductor structure, reference may be made to the above definition of the manufacturing method of the semiconductor structure, and details are not described herein.

In the description herein, references to the description of "one embodiment," "some embodiments," "an ideal embodiment," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

All possible combinations of the technical features of the embodiments described above are not described for brevity, but should be considered as within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor structure, comprising:

and forming a conductive structure on the contact structure.

2. The method as claimed in claim 1, wherein the contact structure passes through the contact hole in a direction perpendicular to the extension direction of the contact hole.

3. The method of claim 2, wherein forming a semiconductor interconnect structure within at least the contact hole and forming a contact structure contacting a surface of the semiconductor interconnect structure comprises:

4. The method of claim 3, wherein the semiconductor connection structure comprises a first connection structure and a second connection structure, and wherein forming the semiconductor connection structure in the contact hole and on the surface of the dielectric layer and forming the contact structure on the surface of the semiconductor connection structure comprises:

epitaxially growing the first connecting structure in the contact hole;

5. The method as claimed in claim 4, wherein the epitaxially growing the first connection structure inside the contact hole comprises:

and based on the dielectric layers on the two sides of the contact hole, carrying out chemical mechanical grinding on the first connecting material layer, removing the first connecting material layer outside the contact hole, and forming the first connecting structure by the residual first connecting material layer.

6. The method as claimed in claim 5, wherein the thickness of the second connection material layer is 10% to 50% of the thickness of the first connection structure.

7. The method as claimed in any of claims 4 to 6, wherein forming a second connection material layer on the surface of the first connection structure and the surface of the dielectric layer comprises:

and forming a second connecting material layer on the surface of the first connecting structure and the surface of the dielectric layer by a chemical vapor deposition method.

8. The method for fabricating a semiconductor structure according to claim 4, wherein the step of reacting the contact material layer with a portion of the second connection material layer to form the contact structure by heat treatment, and the step of forming the second connection structure by the remaining second connection material layer further comprises:

and removing the residual contact material layer.

9. The method of claim 1, wherein the conductive structure comprises a barrier layer and a conductive layer, and wherein forming a conductive structure on the contact structure comprises:

forming a barrier layer on the surface of the contact structure;

and forming a conductive layer on the surface of the barrier layer.

10. The method of claim 3, wherein the step of forming the semiconductor structure comprises,

epitaxially growing a semiconductor connecting material layer on the basis of the semiconductor substrate at the bottom of the contact hole until the semiconductor connecting material layer fills the contact hole and covers the surface of the medium layer;

11. A semiconductor structure, comprising:

a conductive structure on the contact structure.

12. The semiconductor structure of claim 11, wherein the semiconductor connection structure is located within the contact hole and on a surface of the dielectric layer, and wherein the contact structure is located on a surface of the semiconductor connection structure.

13. The semiconductor structure of claim 12, wherein the semiconductor connection structure comprises:

14. The semiconductor structure of claim 13, wherein the first connection structure fills in the contact hole.

15. The semiconductor structure of claim 11, wherein the conductive structure comprises:

the barrier layer is positioned on the surface of the contact structure;

and the conductive layer is positioned on the surface of the barrier layer.

16. The semiconductor structure of claim 15, wherein the barrier layer comprises a titanium nitride layer, the conductive layer comprises a metal layer, the semiconductor connection structure comprises a doped polysilicon layer, and the contact structure comprises a metal silicide layer.