CN115878558A - Universal SDR platform supporting mixed granularity reconstruction - Google Patents
Universal SDR platform supporting mixed granularity reconstruction Download PDFInfo
- Publication number
- CN115878558A CN115878558A CN202211506363.3A CN202211506363A CN115878558A CN 115878558 A CN115878558 A CN 115878558A CN 202211506363 A CN202211506363 A CN 202211506363A CN 115878558 A CN115878558 A CN 115878558A
- Authority
- CN
- China
- Prior art keywords
- granularity
- cgra
- fpga
- block
- mixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 claims abstract description 44
- 230000006870 function Effects 0.000 claims description 8
- 238000011161 development Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Logic Circuits (AREA)
Abstract
The invention relates to a mixed granularity reconfigurable digital signal processing module which comprises a bottom layer and an intermediate layer, wherein the bottom layer is a fine-granularity FPGA basic processing unit, the intermediate layer is a coarse-granularity CGRA basic processing unit, and the coarse-granularity CGRA basic processing unit comprises an FPGA basic unit FPGABlock, a CGRA basic unit CGRABlock and a DSP engine basic unit which are sequentially increased in granularity, and an SRAM. The invention uses the programmable logic resource with FPGA fine granularity and the DSP resource to physically realize the mixed-granularity reconfigurable digital signal processing and accelerate the reconfigurable capability of the system.
Description
Technical Field
The invention relates to the technical field of SDR (software defined disc) platforms, in particular to a general SDR platform supporting mixed granularity reconstruction.
Background
In a conventional FPGA development model, a user generally models an application scenario using a Hardware Description Language (HDL), and then maps the hardware scenario onto an FPGA through a specific FPGA development tool, thereby finally generating an FPGA image that can be run. This traditional FPGA development model causes hardware resources to be idle for a large portion of the time. In order to improve the development efficiency of the FPGA and better utilize the logic resources of the FPGA, a top-level user does not need to pay much attention to the implementation mode and details of the FPGA hardware logic. Thus, the FPGA virtualization technology is produced. Briefly, an FPGA Overlay (virtualization) is a virtual programmable architecture located on top of the FPGA hardware layer and connected to top-level applications.
The CGRA (Coarse-Grained Reconfigurable Array) as a programmable processing unit supporting a higher-level programming model can implement the FPGA virtualization technology, and is a Coarse-Grained Reconfigurable architecture. It improves efficiency by building modules internally, reducing interconnections. And the driving of the data stream is realized by configuring different functional areas. And when the next moment, the unit can be quickly configured with different functions, and the data flow is driven again, which is a data driving and dynamic reconstruction calculation mode, so that the data is high-speed parallel, the layout, wiring and compiling speed is high, and the system performance can be improved.
Software Defined Radio (SDR) is a Radio broadcast communication technology that is based on Software Defined wireless communication protocols rather than being implemented by hardwire. The frequency bands, air interface protocols and functions may be upgraded by software downloads and updates without complete hardware replacement. A software defined radio is a system and architecture that must have the ability to be reprogrammable and reconfigurable to enable devices to be used with a variety of standards, a variety of frequency bands and to perform a variety of functions, and that will not only use programmable devices to implement baseband digital signal processing, but will also program and reconfigure the analog circuitry for radio and intermediate frequencies. The requirements of the functionality of software defined radio include: the ability to reprogram and reset, the ability to provide and change services, the ability to support multiple standards, and the ability to intelligently utilize spectrum, among other things. It should be appreciated that SDR is not a stand alone technology, but a common platform that can be used for all technologies.
SDR baseband processing typically requires a processor for system control and configuration and an FPGA to implement the data path and control of the large computational signal processing, minimizing the delay of the system. The SDR system developed based on the FPGA platform has strong real-time processing capability, but has high development difficulty and high development cost.
Disclosure of Invention
The invention aims to solve the technical problem of providing a general SDR platform supporting mixed granularity reconfiguration, which uses programmable logic resources and DSP resources of FPGA fine granularity to physically realize mixed granularity reconfigurable digital signal processing and accelerate the system reconfigurable capability.
The technical scheme adopted by the invention for solving the technical problem is as follows: the mixed-granularity reconfigurable digital signal processing module comprises a bottom layer and an intermediate layer, wherein the bottom layer is a fine-granularity FPGA basic processing unit, the intermediate layer is a coarse-granularity CGRA basic processing unit, and the coarse-granularity CGRA basic processing unit comprises an FPGA basic unit FPGA Block, a CGRA basic unit CGRA Block and a DSP engine basic unit, and SRAM, wherein the sizes of the FPGA basic unit FPGA Block, the CGRA basic unit CGRA Block and the DSP engine basic unit are sequentially increased.
The FPGA basic unit FPGA Block comprises a Block random access memory BRAM and a configurable logic Block CLB.
The CGRA basic unit CGRA Block comprises a multiplied by b computing units PE which are arranged according to an array, two adjacent computing units PE are interconnected to form a grid structure, and the CGRA basic unit CGRA Block achieves different functions through the computing units PE with different connection architectures.
The DSP engine basic unit comprises a plurality of DSPu, and the DSPu is realized through a configurable logic block CLB and a DSP48Slice in the bottom layer.
The fine-grained FPGA basic processing unit comprises a configurable logic block CLB, an input/output port IO, a block random access memory BRAM and a DSP48Slice, wherein the block random access memory BRAM and the DSP48Slice are both surrounded by different configurable logic blocks CLB.
The technical scheme adopted by the invention for solving the technical problem is as follows: there is provided a general purpose SDR platform comprising hardware logic including a mixed-granularity reconfigurable digital signal processing module as described above.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention uses the programmable logic resource and DSP resource of FPGA fine grain to realize the mixed grain reconfigurable digital signal processing physically, and quickens the system reconfigurable ability; the user of the invention can use C language with higher flexibility to process digital signal, and then the invention is assisted by HDL which describes hardware more accurately, thereby the invention is more convenient for the user to use and the circuit design is more accurate.
Drawings
FIG. 1 is an overall architecture diagram of a generic SDR platform supporting mixed-granularity reconfigurability according to an embodiment of the invention;
FIG. 2 is a block diagram of a mixed-granularity reconfigurable digital signal processing module according to an embodiment of the present invention;
fig. 3 is a signal processing flow diagram of a mixed-granularity reconfigurable digital signal processing module according to an embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention can be made by those skilled in the art after reading the teaching of the present invention, and these equivalents also fall within the scope of the claims appended to the present application.
The embodiment of the invention relates to a mixed granularity reconfigurable digital signal processing module which can be applied to a general SDR platform, and the embodiment is described in detail as follows:
as shown in fig. 1, the figure depicts the overall architecture of a general SDR platform supporting mixed-granularity reconfigurability, which includes two parts, a processing system and hardware logic. The processing system comprises an Application Processing Unit (APU), a real-time processing unit (RPU), a Graphic Processing Unit (GPU), a platform management unit, a DDR controller, a system control unit, a first high-speed connection, a general connection and the like; the hardware logic includes the key points of the embodiment, i.e., a mixed-granularity reconfigurable digital signal processing module (MGR-DSP), a digital-to-analog conversion unit, a second high-speed connection, a general I/O interface, and the like. When different RF analog signals enter and exit the SDR platform from the peripheral interface, the specific RF signal processing is completed by hardware logic including MGR-DSP, and the protocol stack is partially completed by the processing system including APU and RPU. The first high-speed connection mainly comprises connection interfaces such as USB, PCle and SATA, the universal connection mainly comprises universal connection interfaces such as UART, SPI, NAND and GigE, and the second high-speed connection mainly comprises interfaces such as Ethernet MAC and PCle.
As shown in fig. 2, the figure describes a specific architecture of a mixed-granularity reconfigurable digital signal processing module in a general SDR platform, and the architecture is composed of two layers, including a bottom layer and a middle layer, wherein the middle layer is mapped to the bottom layer through a mapping tool. The basic processing unit of the FPGA with the fine granularity at the bottom layer comprises a Configurable Logic Block (CLB), an input/output port (IO), a Block Random Access Memory (BRAM), a DSP48Slice and some interconnections. The intermediate layer comprises a fine-grained FPGA basic unit (FPGA Block), a coarse-grained CGRA basic unit (CGRABlock), a coarser-grained DSP engine basic unit and an SRAM (static random access memory), wherein the fine-grained FPGA basic unit FPGABlock comprises a Block random access memory BRAM and a configurable logic Block CLB; the coarse-grained CGRA basic units CGRABlock comprise a multiplied by b computing units PE arranged in an array, two adjacent computing units PE are interconnected to form a grid structure, and the coarse-grained CGRA basic units CGRABlock realize different functions through the computing units PE with different connection architectures; the basic unit in the DSP engine is physically realized by the programmable logic unit CLB of the bottom layer FPGA and DSP48Slice resources, wherein a simple realization mode is to utilize DSP extension in a RISC-V instruction set.
As shown in fig. 3, the flow chart describes the process of controlling signal processing based on the hardware logic area of mixed-granularity reconfigurable digital signal processing module (MGR-DSP), which includes control program, used languages C and HDL, MGR-DSP, ADC/DAC and RF Block. The control program controls MGR-DSP jointly through UHD library and HDL in C language. Parameters such as sampling frequency of signals, gain of transmitting or receiving signals, clock frequency and the like can be modified through the UHD library, wherein specific functions are written by HDL with higher description accuracy. The two languages are converted to each other through a certain language conversion, so that a user can modify different signal parameters by calling the written function without more finely writing hardware, only needs to transfer some work (such as register operation) to the HDL (hardware description language), and is simple to develop and easy to master. The processed digital signal is processed by digital-to-analog conversion (ADC/DAC) and other devices to obtain a radio frequency signal.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (6)
1. The mixed-granularity reconfigurable digital signal processing module is characterized by comprising a bottom layer and an intermediate layer, wherein the bottom layer is a fine-granularity FPGA basic processing unit, the intermediate layer is a coarse-granularity CGRA basic processing unit, and the coarse-granularity CGRA basic processing unit comprises an FPGA basic unit FPGABlock, a CGRA basic unit CGRA Block and a DSP engine basic unit which are sequentially increased in granularity, and an SRAM.
2. The mixed-granularity reconfigurable digital signal processing module according to claim 1, characterized in that the FPGA basic unit FPGA Block comprises a Block random access memory BRAM and a configurable logic Block CLB.
3. The mixed-granularity reconfigurable digital signal processing module according to claim 1, wherein the CGRA basic unit CGRA Block includes a × b arithmetic units PE arranged in an array, two adjacent arithmetic units PE are interconnected to form a grid structure, and the CGRA basic unit CGRA Block implements different functions through arithmetic units PE of different connection architectures.
4. The mixed-granularity reconfigurable digital signal processing module according to claim 1, wherein the DSP engine basic unit comprises a plurality of DSPu's implemented by configurable logic blocks CLB and DSP48Slice in an underlying layer.
5. The mixed-granularity reconfigurable digital signal processing module according to claim 1, wherein the fine-granularity FPGA basic processing unit comprises a configurable logic block CLB, an input/output port IO, a block random access memory BRAM, and a DSP48Slice, wherein each bit of the block random access memory BRAM and the DSP48Slice is surrounded by a different configurable logic block CLB.
6. A general purpose SDR platform comprising hardware logic comprising the mixed granularity reconfigurable digital signal processing module of any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211506363.3A CN115878558A (en) | 2022-11-29 | 2022-11-29 | Universal SDR platform supporting mixed granularity reconstruction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211506363.3A CN115878558A (en) | 2022-11-29 | 2022-11-29 | Universal SDR platform supporting mixed granularity reconstruction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115878558A true CN115878558A (en) | 2023-03-31 |
Family
ID=85764431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211506363.3A Pending CN115878558A (en) | 2022-11-29 | 2022-11-29 | Universal SDR platform supporting mixed granularity reconstruction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115878558A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060211387A1 (en) * | 2005-02-17 | 2006-09-21 | Samsung Electronics Co., Ltd. | Multistandard SDR architecture using context-based operation reconfigurable instruction set processors |
| CN112084139A (en) * | 2020-08-25 | 2020-12-15 | 上海交通大学 | Multi-emission mixed granularity reconfigurable array processor based on data flow driving |
| CN214045680U (en) * | 2020-12-29 | 2021-08-24 | 上海瀚芯实业发展合伙企业(有限合伙) | Coarse-grained reconfigurable OFDM transmitting end, receiving end and communication system |
| CN113468102A (en) * | 2021-07-22 | 2021-10-01 | 无锡沐创集成电路设计有限公司 | Mixed-granularity computing circuit module and computing system |
-
2022
- 2022-11-29 CN CN202211506363.3A patent/CN115878558A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060211387A1 (en) * | 2005-02-17 | 2006-09-21 | Samsung Electronics Co., Ltd. | Multistandard SDR architecture using context-based operation reconfigurable instruction set processors |
| CN112084139A (en) * | 2020-08-25 | 2020-12-15 | 上海交通大学 | Multi-emission mixed granularity reconfigurable array processor based on data flow driving |
| CN214045680U (en) * | 2020-12-29 | 2021-08-24 | 上海瀚芯实业发展合伙企业(有限合伙) | Coarse-grained reconfigurable OFDM transmitting end, receiving end and communication system |
| CN113468102A (en) * | 2021-07-22 | 2021-10-01 | 无锡沐创集成电路设计有限公司 | Mixed-granularity computing circuit module and computing system |
Non-Patent Citations (2)
| Title |
|---|
| 邹晨 等: "基于FPGA的动态可重配置方法研究", 《航空计算技术》, vol. 42, no. 3, 31 May 2012 (2012-05-31), pages 125 - 129 * |
| 郭彪: "面向可重构SoC的软件无线电架构与调度算法设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》, no. 9, 15 September 2022 (2022-09-15), pages 136 - 66 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10634722B1 (en) | Combined analog architecture and functionality in a mixed-signal array | |
| Majer et al. | The Erlangen Slot Machine: A dynamically reconfigurable FPGA-based computer | |
| US7895416B2 (en) | Reconfigurable integrated circuit | |
| US20170177536A1 (en) | Microcontroller programmable system on a chip | |
| US10210914B2 (en) | Programmable logic accelerator in system on chip | |
| EP1220108A2 (en) | Programmable circuit | |
| KR20030096283A (en) | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements | |
| KR20220157377A (en) | Scalable Array Architecture for In-Memory Computing | |
| EP1556760A2 (en) | Common interface framework for developing field programmable based applications independent of target circuit board | |
| CN107092577B (en) | Integrated circuit device with programmable block and analog circuit control | |
| JP2018530040A (en) | Self-adaptive chip and placement method | |
| Ramacher et al. | Architecture and implementation of a Software-Defined Radio baseband processor | |
| EP1290546B1 (en) | Programmable single-chip device and related development environment | |
| CN115878558A (en) | Universal SDR platform supporting mixed granularity reconstruction | |
| US20060101232A1 (en) | Semiconductor integrated circuit | |
| US7620678B1 (en) | Method and system for reducing the time-to-market concerns for embedded system design | |
| CN111209246B (en) | Miniature programmable on-chip computer based on multi-chip packaging technology | |
| CN114722001A (en) | Software-defined analog-digital hybrid SoC chip architecture | |
| KR102253414B1 (en) | Method for design accelerator of cnn-rnn architecture conversion type | |
| Baskaran et al. | A hardware operating system based approach for run-time reconfigurable platform of embedded devices | |
| Kaneko et al. | An integrated machine code monitor for a RISC-V processor on an FPGA | |
| CN117391035A (en) | Chip with self-defined pin function and implementation method | |
| CN116303215A (en) | Master-slave type multi-DSP processing system, method, equipment and storage medium | |
| Mar et al. | An architecture for a programmable mixed-signal device | |
| Li et al. | Research on Reconfigurable Technology and a Design of Application |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |