CN115878368A - ECC error injection function verification method - Google Patents
ECC error injection function verification method Download PDFInfo
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- CN115878368A CN115878368A CN202211194946.7A CN202211194946A CN115878368A CN 115878368 A CN115878368 A CN 115878368A CN 202211194946 A CN202211194946 A CN 202211194946A CN 115878368 A CN115878368 A CN 115878368A
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Abstract
The invention discloses an ECC error injection function verification method, which comprises the following steps: establishing a verification platform based on a design function to be tested, wherein the design to be tested is a module needing function verification; acquiring address and data information of the design to be tested after ECC check bits are added; setting error random constraint conditions, calling a script to generate error injection test vectors meeting the constraint conditions, and randomly selecting error injection from the error injection test vectors; and testing the ECC function according to the error injection number of the tested error injection vector. Compared with the traditional directional error injection method, the error injection method has the advantages that the error injection positions can be randomly selected at any time by acquiring the information of the ECC check bits added inside, and the randomness and the comprehensiveness of ECC function verification are effectively improved. Meanwhile, by monitoring the time when data enters the storage module, the error injection time can be randomly selected, and the method is more controllable compared with the traditional directional error injection method.
Description
Technical Field
The invention relates to the field of information communication, in particular to the field of ECC error injection function verification.
Background
ECC (Error Correcting Code) is a technique that can both check and correct errors. In the process of designing and developing a System On Chip (SOC) chip, in order to meet different design requirements, a storage module is designed in the chip to store corresponding information, and the error correction and detection functions of ECC can improve the stability and reliability of data information to a certain extent.
Because the ECC function exists in the memory module, the data information added with the ECC check bits is an internal signal of the memory module, and no error data occurs in a normal simulation environment, error injection is needed when the ECC function is verified. The traditional ECC error injection needs to modify data with check bits added inside, only can directionally inject errors to partial data bits, cannot randomly select the injection errors, and has limitation on the time for injecting the errors.
Disclosure of Invention
The invention aims to provide a method for verifying an ECC (error correction code) error injection function, which can effectively improve the flexibility and comprehensiveness of ECC function verification.
In order to achieve the purpose, the invention is realized by the following technical scheme:
an ECC error injection function verification method comprises the following steps:
s1, establishing a verification platform based on a design to be tested, wherein the design to be tested is a module needing function verification;
s2, acquiring address and data information of the design to be tested after ECC check bits are added;
s3, setting error random constraint conditions, calling a script to generate error vectors meeting the constraint conditions, and randomly selecting error injection from the error vectors;
and S4, testing the ECC function according to the number of errors in the error injection test vector.
Further, the constraint conditions include the number of errors and the position of the error injection.
Furthermore, according to the error injection position marked by the selected error injection test vector, negating the corresponding position in the original data to realize error injection.
Further, step S4 further includes:
s4.1, judging the number of injection errors;
and S4.2, comparing the ECC verification result of the address information matched with the corresponding data information with the output result of the design to be tested.
Further, step S4.1 further includes:
and obtaining the error injection position by XOR with the original data which is not injected with errors, and calculating the number of the error injection.
If the number of the injection errors is more than 1, outputting data after the injection errors, and simultaneously setting an ECC error bit; otherwise step S4.2 is performed.
Further, step S4.1 further includes:
if the number of the injection errors is equal to 0, outputting the data without injection errors, and not positioning the ECC check error mark.
If the number of the injected errors is equal to 1, the ECC function can correct the errors normally, and output the data without the injected errors without positioning the ECC check error mark.
Further, the verification platform comprises:
the monitor monitors the state of the data after the ECC check bits are added, and simultaneously transmits the monitored address and data information to the reference model;
the error generation module calls the configuration script to randomly generate an error vector;
the excitation generator is used for negating the error injection position generated by the error generation module to realize error injection;
the reference model compares the data information after error injection with the original information without error injection according to the address information, and calculates the number of error injection;
the scoreboard compares the result after ECC (error correction code) verification of the design to be tested with the verification result obtained by the reference model;
the fault generation module, the excitation generator, the reference model and the scoreboard have information transmission in sequence, the design to be tested and the excitation generator and the scoreboard have information transmission, and the monitor and the design to be tested, the fault generation module and the reference model all have information transmission.
Further, step S4 further includes:
and comparing the result after ECC verification of the design to be tested with the verification result obtained by the reference model, if the output is consistent, proving that the ECC verification function is normal, otherwise, failing the verification, and printing error information.
The invention has the beneficial effects that: compared with the traditional directional error injection method, the error injection method has the advantages that the error injection positions can be randomly selected at any time by acquiring the information of the ECC check bits added inside, and the randomness and the comprehensiveness of ECC function verification are effectively improved. Meanwhile, by monitoring the time when data enters the storage module, the error injection time can be randomly selected, and the method is more controllable compared with the traditional directional error injection method.
Drawings
FIG. 1 is a flow chart illustrating ECC error injection function verification according to the present invention;
FIG. 2 is a diagram illustrating a connection relationship between verification platforms according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
The invention discloses an ECC error injection function verification method, and the specific flow refers to FIG. 1, including the steps:
s1, establishing a verification platform based on the function of the design to be tested, wherein the design to be tested is a module needing function verification. The ECC error injection function verification platform architecture may refer to fig. 2, where the monitor is configured to monitor a state of data after ECC check bits are added, and transmit monitored address and data information to the reference model. The error generation module sets random constraint conditions including error injection number, error injection position and the like according to the bit width of the stored data, and randomly generates various error injection test vectors by calling the script file. And the excitation generation module is used for negating the error injection position generated by the error generation module, so that error injection is realized, and the data information after error injection is sent to the interior of the design to be tested. And comparing the data information after error injection with the original information without error injection by the reference model according to the address information, and calculating the number of the injected errors so as to judge whether the errors can be corrected or detected. And the scoreboard compares the result of the ECC check of the design to be tested with the check result obtained by the reference model, and judges the ECC check function according to the comparison result.
S2, the monitoring module acquires the address and data information of the design to be tested after the ECC check bits are added.
And S3, the error generation module sets random constraint conditions (error injection number and injection position) according to the data bit width, and by taking the data bit width as N bits as an example, the error injection module can inject errors into 0- (N-1) bits of the internal data information added with check bits, so that the error injection number can be constrained to be 0-N. Meanwhile, the position of the fault injection can be restrained, and continuous fault injection or non-continuous fault injection can be randomly selected. A random error generation number may be set so that error vectors satisfying the set number are generated by calling a script, and when the stimulus generator generates error-filled data, error filling may be randomly selected from the generated error vectors.
And S4, monitoring the data information added with the ECC check bits through the interface, and acquiring whether data enters the storage module at any time, so that whether the data information is wrongly annotated or not can be selected at any time after the data information is monitored, and the ECC function is tested.
Meanwhile, the method can be set to carry out error injection on the data by configuring the number of the error injection to be 0. When the reference model carries out error analysis, the error injection position is obtained through XOR with original data which are not injected with errors, the number of the error injection is calculated, the calculation result corresponds to the address information of the data, and the ECC verification result is sent to the scoreboard. If the number of the error injection is 0, the data information is not injected with the error, the reference model outputs the data which is not injected with the error, and an ECC check error mark is not set; if the number of the injected errors is 1, the errors can be corrected, the output data of the reference model is the data without the injected errors, and an ECC check error bit cannot be set; if the number of the injection errors is larger than 1, the errors cannot be corrected, the reference model outputs the data after the injection errors, and meanwhile, an ECC error bit is set. And matching the ECC verification result of the corresponding data information with the output result of the design to be tested through the address information in the scoreboard, and verifying the ECC verification function through result comparison. If the verification result is consistent with the output of the design to be tested, it indicates that the ECC can normally correct and detect errors, and the ECC of the memory module is normal in function.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. An ECC error injection function verification method, comprising the steps of:
s1, establishing a verification platform based on a design to be tested, wherein the design to be tested is a module needing function verification;
s2, acquiring address and data information of the design to be tested after ECC check bits are added;
s3, setting the number and the injection positions of error injection, calling a script to generate error vectors meeting the set number, and randomly selecting error injection from the error vectors;
and S4, testing the ECC function according to the number of errors in the error injection test vector.
2. The method of claim 1, wherein the constraints include a number of errors and a location of an error injection.
3. An ECC error injection method according to claim 1, wherein the error injection is implemented by inverting the corresponding bit marked by the error vector in the original data according to the selected error injection test vector.
4. The method for verifying ECC error injection function of claim 1, wherein the step S4 further comprises:
s4.1, judging the number of injection errors;
and S4.2, comparing the ECC verification result of the address information matched with the corresponding data information with the output result of the design to be tested.
5. The ECC error injection function verification method of claim 4, wherein the step S4.1 further comprises:
obtaining error injection positions through XOR with original data which are not injected with errors, and calculating error injection numbers;
and if the number of the injection errors is more than 1, outputting the data after the injection errors, and simultaneously setting an ECC error bit.
6. The ECC error injection function verification method of claim 5, wherein the step S4.1 further comprises:
if the number of the injection errors is equal to 0, outputting data which are not injected with errors, and not positioning an ECC (error correction code) check error mark;
if the number of the injected errors is equal to 1, the ECC function can correct the errors normally, and output the data without the injected errors without positioning the ECC check error mark.
7. An ECC error injection function verification method according to any one of claims 1 to 6, wherein the verification platform comprises:
the monitor monitors the state of the data after the ECC check bits are added, and simultaneously transmits the monitored address and data information to the reference model;
the error generation module calls the configuration script to randomly generate an error vector;
the excitation generator is used for negating the error injection position generated by the error generation module to realize error injection;
the reference model compares the data information after error injection with the original information without error injection according to the address information and calculates the number of error injection;
the scoreboard is used for comparing the result subjected to ECC (error correction code) verification of the design to be tested with the verification result obtained by the reference model;
the device comprises an error generation module, an excitation generator, a reference model and a scoreboard, wherein the error generation module, the excitation generator, the reference model and the scoreboard are sequentially in information transmission, the design to be tested and the excitation generator and the scoreboard are in information transmission, and the monitor and the design to be tested, the error generation module and the reference model are in information transmission.
8. The method of claim 7, wherein step S4 further comprises:
and comparing the result after the ECC check of the design to be tested with the check result obtained by the reference model, if the output is consistent, the ECC check function is proved to be normal, otherwise, the check fails, and error information is printed.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116467131A (en) * | 2023-06-19 | 2023-07-21 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
| CN117498991A (en) * | 2023-11-14 | 2024-02-02 | 无锡众星微系统技术有限公司 | Testability fault injection method and device based on retransmission function prototype device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116467131A (en) * | 2023-06-19 | 2023-07-21 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
| CN116467131B (en) * | 2023-06-19 | 2023-08-25 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
| CN117498991A (en) * | 2023-11-14 | 2024-02-02 | 无锡众星微系统技术有限公司 | Testability fault injection method and device based on retransmission function prototype device |
| CN117498991B (en) * | 2023-11-14 | 2024-05-28 | 无锡众星微系统技术有限公司 | Testability fault injection method and device based on retransmission function prototype device |
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