CN115877617A - Array substrate, liquid crystal display panel, driving method and liquid crystal display device - Google Patents
Array substrate, liquid crystal display panel, driving method and liquid crystal display device Download PDFInfo
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Abstract
The application provides an array substrate, a liquid crystal display panel, a driving method and a liquid crystal display device, and relates to the technical field of liquid crystal display, wherein the array substrate comprises public electrodes and pixel electrodes, each row of the pixel electrodes and the public electrodes of corresponding rows are arranged in a staggered mode in the row direction, the projection area of each pixel electrode on a substrate of the array substrate is partially overlapped with the projection area of two corresponding adjacent public electrodes on the substrate in the row direction, the pixel units of the array substrate corresponding to each overlapped area are different, each row of the public electrodes and the pixel electrodes of the corresponding rows share one data line, each pixel electrode and one corresponding public-related electrode share one combination switch, each combination switch comprises a driving thin film transistor and a signal selection unit, and the signal selection unit is used for controlling the data lines to transmit signals to the public electrodes or the pixel electrodes. The technical scheme that this application provided can reduce the influence to the aperture opening ratio when promoting resolution ratio.
Description
Technical Field
The application relates to the technical field of liquid crystal display, in particular to an array substrate, a liquid crystal display panel, a driving method and a liquid crystal display device.
Background
With the continuous maturity of Liquid Crystal Display technology, liquid Crystal Display devices such as Thin Film Transistor Liquid Crystal displays (TFT-LCDs) are increasingly widely used in various fields.
For the TFT-LCD, the resolution is improved to significantly improve the definition of the displayed image, and at present, the area of the pixel units in the display is usually reduced to increase the number of the pixel units in the display, so as to improve the resolution.
However, in order to ensure the charging rate, devices and wires in the pixel unit occupy a certain area, which limits the area reduction of the pixel unit, and the resolution also reaches a bottleneck, so how to improve the resolution of the liquid crystal display device is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present disclosure provides an array substrate, a liquid crystal display panel, a driving method thereof, and a liquid crystal display device, so as to improve the resolution of the liquid crystal display device.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides an array substrate, including: the pixel array comprises a public electrode layer and a pixel electrode layer, wherein the public electrode layer comprises a plurality of public electrodes arranged in an array, the pixel electrode layer comprises a plurality of pixel electrodes arranged in an array, each column of public electrodes corresponds to each column of pixel electrodes one by one, and each column of pixel electrodes and the public electrodes of the corresponding columns are arranged in a staggered manner in the column direction;
the projection area of each pixel electrode on the substrate of the array substrate is partially overlapped with the projection areas of two corresponding adjacent public electrodes on the substrate in the column direction, and the pixel unit of the array substrate corresponding to each overlapping area is different;
each column of common electrodes and the pixel electrodes of the corresponding column share one data line, each pixel electrode and the corresponding common electrode share one combination switch, each combination switch comprises a driving thin film transistor and a signal selection unit, and the signal selection unit is used for controlling the data lines to transmit data signals to the common electrodes or the pixel electrodes when the driving thin film transistors are conducted.
As an optional implementation manner of the embodiment of the present application, the signal selection unit includes a first unidirectional conductive element, a second unidirectional conductive element, a third unidirectional conductive element, and a fourth unidirectional conductive element;
the control end of the driving thin film transistor is electrically connected with the gate line, the input end of the driving thin film transistor is electrically connected with the data line, and the output end of the driving thin film transistor is respectively electrically connected with the anode of the first unidirectional conducting element and the cathode of the third unidirectional conducting element;
the cathode of the first unidirectional conduction element is electrically connected with the common electrode and the anode of the second unidirectional conduction element respectively, and the cathode of the second unidirectional conduction element is electrically connected with the first reset signal line;
and the anode of the third unidirectional conduction element is electrically connected with the pixel electrode and the cathode of the fourth unidirectional conduction element respectively, and the anode of the fourth unidirectional conduction element is electrically connected with the second reset signal line.
As an optional implementation manner of this embodiment, in the column direction, a light shielding unit is disposed between adjacent common electrodes.
As an optional implementation manner of this embodiment, in the column direction, a projection of a center line between boundaries of adjacent common electrodes on the substrate of the array substrate overlaps a projection of a center line of a corresponding pixel electrode in the row direction on the substrate.
As an optional implementation manner of the embodiment of the present application, the array substrate includes: the pixel electrode comprises a substrate base plate, a first metal layer, a common electrode layer, a first PN junction layer, an insulating layer, a semiconductor layer, a second metal layer, a first passivation layer, a third metal layer, a second passivation layer, a pixel electrode layer, a second PN junction layer, a third passivation layer and a first oxide conducting layer;
the first metal layer and the common electrode layer are positioned above the substrate base plate, the first metal layer comprises a plurality of gate lines and metal spacing units, the metal spacing units are positioned above the substrate base plate and the common electrode layer, and the first PN junction layer is positioned above the common electrode layer;
the insulating layer is positioned above the substrate base plate, the first metal layer, the common electrode layer and the first PN junction layer, the semiconductor layer is positioned above the insulating layer, and the second metal layer is positioned above the semiconductor layer and the insulating layer;
the first passivation layer is positioned above the insulating layer, the semiconductor layer and the second metal layer, the third metal layer is positioned above the first passivation layer, the third metal layer comprises a plurality of reset signal lines, and the second passivation layer is positioned above the first passivation layer and the third metal layer;
the pixel electrode layer is positioned above the second passivation layer, and each pixel electrode in the pixel electrode layer is in contact with the second metal layer and the metal spacing unit through a through hole;
the second PN junction layer is located above the pixel electrode layer, the third passivation layer is located above the second passivation layer, the pixel electrode layer and the second PN junction layer, and the first oxide conducting layer is located above the third passivation layer.
In a second aspect, an embodiment of the present application provides a liquid crystal display panel, including a color film substrate, an array substrate according to the first aspect or any one of the first aspects, and a liquid crystal layer located between the array substrate and the color film substrate, where the color film substrate and the array substrate are arranged in an opposite direction.
As an optional implementation manner of this embodiment, a second oxide conductive layer is disposed below the color filter substrate, the second oxide conductive layer is disposed in a divisional manner, and the patterns of the first oxide conductive layer and the second oxide conductive layer of the array substrate are the same.
In a third aspect, an embodiment of the present application provides a liquid crystal display panel driving method, applied to the liquid crystal display panel according to the second aspect or any one of the second aspects, the method including:
for each pixel unit in the liquid crystal display panel, determining a second voltage of a second electrode corresponding to the pixel unit according to a pre-display gray scale of the pixel unit and a first voltage of a first electrode corresponding to the pixel unit; the first electrode is a common electrode, the second electrode is a pixel electrode, or the first electrode is a pixel electrode, and the second electrode is a common electrode;
outputting the second voltage to the second electrode.
As an optional implementation manner of this embodiment of the present application, the determining a second voltage of a second electrode corresponding to the pixel unit according to the pre-display gray scale of the pixel unit and the first voltage of the first electrode corresponding to the pixel unit includes:
determining the absolute value of the voltage difference between the first electrode and the second electrode according to the pre-display gray scale of the pixel unit;
determining the sum of the first voltage and the absolute value of the voltage difference as the second voltage when the first electrode is a common electrode;
and when the first electrode is a pixel electrode, determining the difference between the first voltage and the absolute value of the voltage difference as the second voltage.
In a fourth aspect, an embodiment of the present application provides a liquid crystal display device, which includes a backlight source and the liquid crystal display panel according to the second aspect or any one of the second aspects, where the backlight source is located on a side of the array substrate away from the color filter substrate.
The technical scheme provided by the embodiment of the application comprises a public electrode layer and a pixel electrode layer, wherein the public electrode layer comprises a plurality of public electrodes arranged in an array, the pixel electrode layer comprises a plurality of pixel electrodes arranged in an array, each row of the public electrodes corresponds to each row of the pixel electrodes one by one, and each row of the pixel electrodes and the public electrodes of the corresponding rows are arranged in a staggered manner in the row direction; the projection area of each pixel electrode on the substrate of the array substrate is partially overlapped with the projection areas of two corresponding adjacent public electrodes on the substrate in the column direction, and the pixel unit of the array substrate corresponding to each overlapping area is different; each column of common electrodes and the pixel electrodes of the corresponding columns share one data line, each pixel electrode and the corresponding common electrode share one combination switch, each combination switch comprises a driving thin film transistor and a signal selection unit, and the signal selection unit is used for controlling the data lines to transmit data signals to the common electrodes or the pixel electrodes when the driving thin film transistors are conducted. In the above technical solution, each row of pixel electrodes and the corresponding row of common electrodes are arranged in a staggered manner in the column direction, so that a horizontal electric field can be formed between one pixel electrode and two corresponding adjacent common electrodes in the column direction, and if different voltages are output to the two adjacent common electrodes, the display areas corresponding to the two horizontal electric fields can display different gray scales, that is, the display area corresponding to one pixel electrode can display two different gray scales in the column direction, compared with the case that only one gray scale can be displayed in the column direction in the display area corresponding to one pixel electrode at present, the present solution can increase the resolution by one time in the column direction of the liquid crystal display device; in addition, each row of common electrodes and the corresponding row of pixel electrodes share one data line, and each pixel electrode and the corresponding common electrode share one combination switch, so that new data lines and driving thin film transistors do not need to be added, and the influence on the aperture opening ratio of the liquid crystal display device can be reduced.
Drawings
Fig. 1 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present disclosure;
fig. 2 is a schematic arrangement diagram of a common electrode and a pixel electrode in a column direction according to an embodiment of the present disclosure;
fig. 3 is a circuit schematic diagram of a combination switch provided in an embodiment of the present application;
fig. 4 is a top view of an array substrate provided in an embodiment of the present application in a column direction;
FIG. 5 isbase:Sub>A cross-sectional view of the array substrate taken along line A-A' according to an embodiment of the present disclosure;
FIG. 6 is a cross-sectional view of the array substrate taken along line B-B' according to the present embodiment;
fig. 7 is a schematic view of a first oxide conductive layer provided in an embodiment of the present application;
fig. 8 is a schematic relationship diagram of a common electrode and a pixel electrode in any column in an array substrate provided in this embodiment of the present application;
fig. 9 is a timing diagram of a reset signal and a gate driving signal according to an embodiment of the present disclosure.
Description of the reference numerals:
1-a backlight source; 2-a color film substrate;
3-an array substrate; 4-a liquid crystal layer;
311-substrate base plate; 312-a first metal layer;
313-a common electrode layer; 314-a first PN junction layer;
315-an insulating layer; 316-a semiconductor layer;
317-second metal layer; 318-first passivation layer;
319-third metal layer; 320-a second passivation layer;
321-a pixel electrode layer; 322-a second PN junction layer;
323-a third passivation layer; 324-a first oxide conductive layer;
325-via hole;
3121-gate lines; 3122-metal spacer unit.
Detailed Description
The embodiments of the present application will be described below with reference to the drawings. The terminology used in the description of the embodiments of the examples herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a schematic structural diagram of a liquid crystal display device provided in an embodiment of the present application, and as shown in fig. 1, the liquid crystal display device provided in the embodiment of the present application may include a liquid crystal display panel and a backlight 1.
The liquid crystal display panel may be an In-Plane Switching (IPS) display panel, or may be another type of display panel, and the example of the liquid crystal display panel In the embodiment is described as an IPS display panel.
The liquid crystal display panel may include: a color film substrate 2, an array substrate 3 and a liquid crystal layer 4.
The array substrate 3 and the color film substrate 2 are arranged oppositely, and the liquid crystal layer 4 is located between the array substrate 3 and the color film substrate 2.
The backlight source 1 is located on one side of the array substrate 3, which is away from the color film substrate 2, and the backlight source is used for providing a backlight source for the liquid crystal display panel.
The array substrate 3 may include a common electrode layer and a pixel electrode layer, the common electrode layer may include a plurality of common electrodes arranged in an array, the pixel electrode layer may include a plurality of pixel electrodes arranged in an array, the number of columns of the common electrodes and the number of columns of the pixel electrodes are the same, each column of the common electrodes corresponds to one column of the pixel electrodes, and each column of the common electrodes corresponds to different columns of the pixel electrodes.
Fig. 2 is a schematic arrangement diagram of common electrodes and pixel electrodes provided in an embodiment of the present application in a column direction, as shown in fig. 2, each column of pixel electrodes and the corresponding column of common electrodes are arranged in a staggered manner, a projection area of each pixel electrode on a substrate of an array substrate 3 and a projection area of two corresponding adjacent common electrodes (a first common electrode and a second common electrode) on the substrate are partially overlapped in the column direction, each overlapping area corresponds to one pixel unit of the array substrate 3, and the pixel units corresponding to each overlapping area are different. Therefore, a pixel electrode can form a horizontal electric field with two corresponding adjacent common electrodes in the column direction, and if different voltages are output to the two adjacent common electrodes, the display areas (namely the first pixel unit and the second pixel unit) corresponding to the two horizontal electric fields can display different gray scales, so that the display area corresponding to one pixel electrode can display two different gray scales in the column direction.
A projection of a center line between boundaries of adjacent common electrodes on the substrate of the array substrate 3 may overlap a projection of a center line of a corresponding pixel electrode in the row direction on the substrate. Therefore, the lengths of the two horizontal electric fields corresponding to one pixel electrode in the column direction are equal, namely the areas of the first display area and the second display area corresponding to one pixel electrode are equal, and therefore the display effect of the liquid crystal display device is improved.
Each column of the common electrodes and the corresponding column of the pixel electrodes may share one data line, and each pixel electrode may share one combination switch with a corresponding one of the common electrodes. The combination switch may include a thin film transistor (which is a thin film transistor corresponding to the pixel electrode and is not a newly added thin film transistor) and a signal selection unit for controlling the data line to transmit the data signal to the common electrode or the pixel electrode when the thin film transistor is turned on. Thus, the data lines and the thin film transistors of the pixel electrodes corresponding to the common electrodes can be multiplexed, and the data lines and the thin film transistors do not need to be added for the common electrodes, so that the influence on the aperture ratio of the liquid crystal display device can be reduced.
Each pixel electrode may share one combination switch with the corresponding first common electrode, and may also share one combination switch with the corresponding second common electrode, and this embodiment will be exemplified by taking an example that each pixel electrode shares one combination switch with the corresponding first common electrode.
The signal selection unit may be a circuit element that conducts in one direction, such as a diode, a thyristor, etc. In the following description, the signal selection unit is taken as an example of a diode for exemplary explanation.
Fig. 3 is a circuit schematic diagram of a combination switch provided in the embodiment of the present application, and as shown in fig. 3, the signal selection unit may include a first diode P1, a second diode P2, a third diode P3, and a fourth diode P4.
The control end of the thin film transistor T1 is electrically connected to the gate line Scan, the input end of the thin film transistor T1 is electrically connected to the Data line Data, and the output end of the thin film transistor T1 is electrically connected to the input end of the first diode P1 and the output end of the third diode P3, respectively.
The output end of the first diode P1 is electrically connected to the common electrode of the liquid crystal capacitor Cst and the input end of the second diode P2, respectively, and the output end of the second diode P2 is electrically connected to the first reset signal line; an input terminal of the third diode P3 is electrically connected to the pixel electrode of the liquid crystal capacitor Cst and an output terminal of the fourth diode P4, respectively, and an input terminal of the fourth diode P4 is electrically connected to the second reset signal line.
When the scanning line transmits a scanning signal, the thin film transistor T1 is turned on, and at this time, if the potential of the Data signal transmitted by the Data line Data is higher than the potential at the pixel electrode, the first diode P1 is turned on, and the Data signal transmitted by the Data line Data charges the pixel electrode, and due to the presence of the second diode P2, most of the current flows to the pixel electrode during charging, and at this time, the potential of the first reset signal line is high, and the second diode P2 is turned off, so as to reduce the influence of the first reset signal line on the potential at the pixel electrode. It is understood that when the potential of the data signal is higher than the potential at the common electrode, the third diode P3 is turned off, and the data signal is not charged to the common electrode.
If the potential of the Data signal transmitted by the Data line Data is lower than the potential of the common electrode, the third diode P3 is turned on, the Data signal charges the common electrode, most of the current flows to the common electrode during charging due to the fourth diode P4, the potential of the second reset signal line is low, and the fourth diode P4 is turned off, so that the influence of the second reset signal line on the potential of the common electrode is reduced. It is understood that when the potential of the data signal is lower than the potential at the pixel electrode, the first diode P1 is turned off, and the data signal is not charged to the pixel electrode.
The first reset signal line is used for resetting the potential of the pixel electrode, the second reset signal line is used for resetting the potential of the common electrode, and the first reset signal line can be electrically connected with the first peripheral reset signal line through a first switch tube T2; the first reset signal line may be electrically connected to the second peripheral reset signal line through the second switching tube T3.
The first and second switching tubes T2 and T3 may be disposed in a non-display area of the array substrate 3 to save an in-plane space.
The diodes can also reduce off-state leakage currents of the thin film transistor T1, the first switch tube T2 and the second switch tube T3, and further block the leakage currents so as to reduce the influence of the leakage currents on the common electrode and the pixel electrode.
Fig. 4 is a top view of an array substrate provided in an embodiment of the present application in a column direction, as shown in fig. 4,
the array substrate 3 may include a plurality of gate lines extending in a row direction, and a plurality of data lines extending in a column direction.
In the column direction, a shading unit can be arranged between the adjacent common electrodes to reduce the influence of liquid crystal disorder between the horizontal electric fields corresponding to the adjacent common electrodes on the display effect; a shading unit can be arranged between the adjacent pixel electrodes to reduce the influence of liquid crystal disorder between the horizontal electric fields corresponding to the adjacent pixel electrodes on the display effect.
In the column direction, the projection of the central line between the boundaries of the adjacent common electrodes on the substrate of the array substrate 3 can be located in the projection area of the corresponding gate line and the reset signal line of the array substrate 3 on the substrate, that is, the gate line and the reset signal line are located in the spacing area of the adjacent common electrodes in the column direction, and since the spacing area of the adjacent common electrodes does not emit light (is shielded by the corresponding light shielding units), the gate line and the reset signal line cannot shield light, and the loss of the aperture ratio of the liquid crystal display device caused by the gate line and the reset signal line is reduced.
Fig. 5 isbase:Sub>A cross-sectional view of the array substrate 3 taken alongbase:Sub>A-base:Sub>A 'according to an embodiment of the present disclosure, and fig. 6 isbase:Sub>A cross-sectional view of the array substrate 3 taken along B-B' according to an embodiment of the present disclosure, and as shown in fig. 5 and 6, the array substrate 3 may include: a substrate 311, a first metal layer 312, a common electrode layer 313, a first PN junction layer 314, an insulating layer 315, a semiconductor layer 316, a second metal layer 317, a first passivation layer 318, a third metal layer 319, a second passivation layer 320, a pixel electrode layer 321, a second PN junction layer 322, a third passivation layer 323, and a first oxide conductive layer 324.
The substrate 311 may be quartz, glass, organic polymer, silicon, metal, or other semiconductor material.
The first metal layer 312 and the common electrode layer 313 are located above the substrate base 311, the first metal layer 312 may include a plurality of gate lines 3121 and metal spacing units 3122, the metal spacing units 3122 are located above the substrate base 311 and the common electrode layer 313, the first metal layer 312 may be formed by a sputtering process, the first metal layer 312 may be one or more of aluminum, molybdenum, copper, and silver, and the first metal layer 312 formed by the above materials may achieve low impedance and high adhesion.
The common electrode layer 313 may be formed by forming a metal film over the substrate base 311 by a sputtering process, and then exposing and developing the metal film.
The first PN junction layer 314 is located above the common electrode layer 313, and the first PN junction layer 314 may include a plurality of PN junctions arranged at intervals.
The insulating layer 315 is disposed over the substrate base 311, the first metal layer 312, the common electrode layer 313, and the first PN junction layer 314, and the insulating layer 315 may be formed using a plasma enhanced chemical vapor deposition process.
The semiconductor layer 316 is located above the insulating layer 315, and the material of the semiconductor layer 316 may be phosphine-doped hydrogenated amorphous silicon or other semiconductor materials, and forming the semiconductor layer 316 using the above materials can form good contact between the semiconductor layer 316 and the metal electrode of the second metal layer 317, reduce contact resistance between the semiconductor layer 316 and the second metal layer 317, and improve the electron transfer rate.
The second metal layer 317 is positioned over the semiconductor layer 316 and the insulating layer 315, and the first metal layer 312 may include a drain and a source. The second metal layer 317 may be formed by a sputtering process, and the material of the second metal layer 317 may include one or more of aluminum, molybdenum, copper, and silver, and the second metal layer 317 formed by the above materials can achieve the effects of low resistance and high adhesion.
A first passivation layer 318 is disposed over the insulating layer 315, the semiconductor layer 316, and the second metal layer 317, and the first passivation layer 318 may be formed using a plasma enhanced chemical vapor deposition process, and the first passivation layer 318 is used to protect the insulating layer 315, the semiconductor layer 316, and the second metal layer 317.
The third metal layer 319 is positioned above the first passivation layer 318, and the third metal layer 319 may include a plurality of reset signal lines, each of which is bridged with a corresponding pixel electrode or common electrode by a via 325. The material of the third metal layer 319 may include one or more of aluminum, molybdenum, copper, and silver.
The second passivation layer 320 is positioned over the first passivation layer 318 and the third metal layer 319, and the second passivation layer 320 may be formed using a plasma enhanced chemical vapor deposition process.
The pixel electrode layer 321 is located above the second passivation layer 320, and each pixel electrode in the pixel electrode layer 321 is in contact with the second metal layer 317 and the metal spacing unit 3122 through the via 325. In this way, the common electrode and the corresponding pixel electrode are bridged by the via 325, and the high and low potential data signals output from the data line are transmitted to the common electrode and the high potential data signals output from the data line are transmitted to the pixel electrode through the selective PN junction, thereby forming a voltage difference between the common electrode and the corresponding pixel electrode.
The second PN junction layer 322 is located above the pixel electrode layer 321, and the first PN junction layer 314 may include a plurality of PN junctions arranged at intervals.
The third passivation layer 323 is positioned over the second passivation layer 320, the pixel electrode layer 321, and the second PN junction layer 322, and the third passivation layer 323 may be formed using a plasma enhanced chemical vapor deposition process. The third passivation layer 323 may be provided as a thin layer to reduce the influence of the inversion of the liquid crystal in the normally open region.
The first oxide conductive layer 324 is over the third passivation layer 323, and a material of the first oxide conductive layer 324 may be indium tin oxide or the like. The first oxide conductive layer 324 is used to hold the potential of the corresponding reset signal line.
Specifically, a dc signal may be applied to the first oxide conductive layer 324, so that a holding capacitance is formed between the first oxide conductive layer 324 and the reset signal line, and the potential of the reset signal line signal is held.
Fig. 7 is a schematic view of the first oxide conductive layer provided in this embodiment of the application, as shown in fig. 7, the first oxide conductive layer may be disposed in a plurality of partitions, each partition may be in a grid shape, and each partition may be connected to a pin through one wire, so as to connect to a Printed Circuit Board (PCB).
The wiring connected to the pin can cover the data line, so that the electrode formed by the first oxide conductive layer can not form a chaotic electric field with the opening area to influence the liquid crystal inversion.
A second oxide conducting layer may be disposed below the color filter substrate, the second oxide conducting layer may be in accordance with the pattern of the first oxide conducting layer to form a plurality of grid-shaped partitions, and the same signal as that of the corresponding partition of the first oxide conducting layer may be supplied to each partition. Therefore, after a user touches the display panel by a finger, capacitance is formed between the finger and the second oxide conducting layer, so that an electric signal of a partition corresponding to the second oxide conducting layer changes, and due to the capacitive coupling effect between the first oxide conducting layer and the second oxide conducting layer, the electric signal of the partition corresponding to the second oxide conducting layer also changes, so that the change of a partial electric signal corresponding to the second oxide conducting layer can be identified through an IC (integrated circuit) of a PCB (printed circuit board) connected with the partition corresponding to the second oxide conducting layer through pins, the tracking of a touch signal is realized, and a touch function is formed on the display panel.
The following describes a driving method of a liquid crystal display panel provided in an embodiment of the present application.
When the liquid crystal display panel is driven to display, a progressive scanning mode can be adopted. When scanning to the Nth row and the Mth column of the liquid crystal display panel, determining a second voltage of a second electrode corresponding to the pixel unit according to a pre-display gray scale of the pixel unit in the Nth row and the Mth column of the liquid crystal display panel and a first voltage of a first electrode corresponding to the pixel unit, wherein M and N are positive integers; the first electrode is a common electrode and the second electrode is a pixel electrode, or the first electrode is a pixel electrode and the second electrode is a common electrode.
After determining the second voltage of the second electrode, the second voltage may be output to the second electrode.
Fig. 8 is a schematic diagram of a relationship between a common electrode and a pixel electrode in any column in an array substrate provided in this embodiment of the application, and as shown in fig. 8, a pixel unit P 2n-3 Corresponding pixel electrode PXL n-1 And a common electrode COM n-2 Pixel unit P 2n-2 Corresponding pixel electrode PXL n-1 And a common electrode COM n-1 Pixel unit P 2n-1 Corresponding pixel electrode PXL n And a common electrode COM n-1 Pixel unit P 2n Corresponding pixel electrode PXL n And a common electrode COM n Pixel unit P 2n+1 Corresponding pixel electrode PXL n+1 And a common electrode COM n Pixel unit P 2n+2 Corresponding pixel electrode PXL n+1 And a common electrode COM n+1 。
When scanning to the n-1 th row, the gate line G n-1 Can be a high level signal, the pixel electrode PXL n-1 And a common electrode COM n-1 Is turned on, and then the corresponding TFT is turned on according to the pixel unit P 2n-3 Determining corresponding pressure difference according to the pre-displayed gray scale, and then according to the pressure difference sumCommon electrode COM n-1 Voltage (data line already towards common electrode COM when scanning the upper row n-1 Output data signal), the pixel electrode PXL is determined n-1 Then to the pixel electrode PXL through the data line n-1 Output corresponding data signal, at the time of common electrode COM n-2 And pixel electrode PXL n-1 The liquid crystal between the overlapping regions is inverted, and the pixel unit P 2n-3 Displaying the corresponding gray scale.
Then may be based on the pixel cell P 2n-2 The corresponding voltage difference is determined according to the pre-display gray scale, and then the pixel electrode PXL is connected with the voltage difference n-1 Determines the common electrode COM n-1 Then through the data line to the common electrode COM n-1 Outputting corresponding data signal when the pixel electrode PXL n-1 And a common electrode COM n-1 The liquid crystal between the overlapping regions is inverted, and the pixel unit P 2n-2 Displaying the corresponding gray scale.
When scanning to the n-th row, the gate line G n Can be a high level signal, the pixel electrode PXL n And a common electrode COM n Is turned on, and then the corresponding TFT is turned on according to the pixel unit P 2n-1 The corresponding voltage difference is determined according to the pre-display gray scale, and then the common electrode COM is connected with the voltage difference n Determines the pixel electrode PXL n Then to the pixel electrode PXL through the data line n Output corresponding data signal, at the time of common electrode COM n-1 And a pixel electrode PXL n The liquid crystal between the overlapping regions is inverted, and the pixel unit P 2n-1 Displaying the corresponding gray scale.
Then may be based on the pixel cell P 2n The corresponding voltage difference is determined according to the pre-display gray scale, and then the pixel electrode PXL is connected with the voltage difference n Determines the common electrode COM n Then through the data line to the common electrode COM n Outputting corresponding data signal when the pixel electrode PXL n And a common electrode COM n The liquid crystal between the overlapping regions is inverted, and the pixel unit P 2n Displaying the corresponding gray scale.
And so on, the liquid crystal display panel is lighted line by line.
In addition, since the liquid crystal inversion degree is related to the absolute value of the voltage difference, and is independent of the direction, when the voltage of the corresponding pixel electrode is determined according to the voltage of the common electrode and the voltage difference, the sum of the voltage difference and the voltage of the common electrode can be determined as the voltage of the pixel electrode; when the voltage of the corresponding common electrode is determined according to the voltage of the pixel electrode and the voltage difference, a difference between the voltage of the pixel electrode and the voltage difference may be determined as the voltage of the common electrode. Therefore, the voltages of the pixel electrode and the common electrode of each row of the display device can be maintained not to be too high.
When scanning in the above mode, the potential of the common electrode of each row is always smaller than that of the pixel electrode. Fig. 9 is a timing chart of the reset signal and the gate driving signal when scanning as described above, and as shown in fig. 9, the signal when the reset signal 1 output from the first reset signal line is at the valley, and the signal obtained by combining the signal of the previous row of common electrodes with the signal of the previous row of common electrodes at that time may be the lowest potential signal of the previous row of common electrodes, and the duration of the combined signal may be 1/2H (specifically, H may be adjusted according to the refresh rate and resolution of the display device). The signal of the reset signal 1 at the other time is the highest potential signal inputted to the pixel electrode corresponding to the present row.
The signal of the reset signal 2 output by the second reset signal line at the peak time and the signal combined with the signal of the common electrode in the previous row at that time are the highest potential signals of the pixel electrodes in the current row, and the duration of the combined signal may be 1/2H. The signal of the reset signal 2 at the other time is the lowest potential signal of the pixel electrode corresponding to the present row.
The first reset signal line and the second reset signal line may input a signal when the present row of gate driving signals is turned on, and may hold the signal when the present row of gate driving signals is not turned on.
The data line signal may charge a high potential signal to the pixel electrode at the first 1/2H of each H and a low potential signal to the common electrode at the second half frame of the last 1/2H.
The technical scheme provided by the embodiment of the application comprises a public electrode layer and a pixel electrode layer, wherein the public electrode layer comprises a plurality of public electrodes arranged in an array manner, the pixel electrode layer comprises a plurality of pixel electrodes arranged in an array manner, each row of public electrodes corresponds to each row of pixel electrodes one by one, and each row of pixel electrodes and the public electrodes of the corresponding rows are arranged in a staggered manner in a row direction; the projection area of each pixel electrode on the substrate base plate of the array base plate is partially overlapped with the projection areas of two corresponding adjacent public electrodes on the substrate base plate in the column direction, and the pixel units of the array base plate corresponding to each overlapped area are different; each column of common electrodes and the pixel electrodes of the corresponding columns share one data line, each pixel electrode and the corresponding common electrode share one combination switch, each combination switch comprises a driving thin film transistor and a signal selection unit, and the signal selection unit is used for controlling the data lines to transmit data signals to the common electrodes or the pixel electrodes when the driving thin film transistors are conducted. In the above technical solution, each row of pixel electrodes and the corresponding row of common electrodes are arranged in a staggered manner in the column direction, so that a horizontal electric field can be formed between one pixel electrode and two corresponding adjacent common electrodes in the column direction, and if different voltages are output to the two adjacent common electrodes, the display areas corresponding to the two horizontal electric fields can display different gray scales, that is, the display area corresponding to one pixel electrode can display two different gray scales in the column direction, compared with the case that only one gray scale can be displayed in the column direction in the display area corresponding to one pixel electrode at present, the present solution can increase the resolution by one time in the column direction of the liquid crystal display device; in addition, each row of common electrodes and the corresponding row of pixel electrodes share one data line, and each pixel electrode and the corresponding common electrode share one combination switch, so that new data lines and driving thin film transistors are not needed to be added, and the influence on the aperture opening ratio of the liquid crystal display device can be reduced.
In the above embodiments, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described or recited in any embodiment.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/device and method may be implemented in other ways. For example, the above-described apparatus/device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In the description of the present application, a "/" indicates a relationship in which the objects associated before and after are an "or", for example, a/B may indicate a or B; in the present application, "and/or" is only an association relationship describing an association object, and means that there may be three relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural.
Also, in the description of the present application, "a plurality" means two or more than two unless otherwise specified. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be implemented in other sequences than those illustrated or described herein.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. An array substrate, comprising: the pixel electrode layer comprises a plurality of pixel electrodes which are arranged in an array, each column of common electrodes corresponds to each column of pixel electrodes one by one, and each column of pixel electrodes and the common electrodes of the corresponding columns are arranged in a staggered mode in the column direction;
the projection area of each pixel electrode on the substrate base plate of the array base plate is partially overlapped with the projection areas of two corresponding adjacent public electrodes on the substrate base plate in the column direction, and the pixel units of the array base plate corresponding to each overlapped area are different;
each column of common electrodes and the pixel electrodes of the corresponding column share one data line, each pixel electrode and the corresponding common electrode share one combination switch, each combination switch comprises a driving thin film transistor and a signal selection unit, and the signal selection unit is used for controlling the data lines to transmit data signals to the common electrodes or the pixel electrodes when the driving thin film transistors are conducted.
2. The array substrate of claim 1, wherein the signal selection unit comprises a first one-way conduction element, a second one-way conduction element, a third one-way conduction element and a fourth one-way conduction element;
the control end of the driving thin film transistor is electrically connected with the gate line, the input end of the driving thin film transistor is electrically connected with the data line, and the output end of the driving thin film transistor is respectively electrically connected with the anode of the first one-way conduction element and the cathode of the third one-way conduction element;
the cathode of the first unidirectional conduction element is electrically connected with the common electrode and the anode of the second unidirectional conduction element respectively, and the cathode of the second unidirectional conduction element is electrically connected with the first reset signal line;
and the anode of the third unidirectional conduction element is electrically connected with the pixel electrode and the cathode of the fourth unidirectional conduction element respectively, and the anode of the fourth unidirectional conduction element is electrically connected with the second reset signal line.
3. The array substrate of claim 1, wherein a light shielding unit is disposed between adjacent common electrodes in the column direction.
4. The array substrate of claim 1, wherein in a column direction, a projection of a center line between boundaries of adjacent common electrodes on a substrate of the array substrate overlaps with a projection of a center line of a corresponding pixel electrode on the substrate in a row direction.
5. The array substrate of any one of claims 1-4, wherein the array substrate comprises: the pixel electrode comprises a substrate base plate, a first metal layer, a common electrode layer, a first PN junction layer, an insulating layer, a semiconductor layer, a second metal layer, a first passivation layer, a third metal layer, a second passivation layer, a pixel electrode layer, a second PN junction layer, a third passivation layer and a first oxide conducting layer;
the first metal layer and the common electrode layer are positioned above the substrate base plate, the first metal layer comprises a plurality of gate lines and metal spacing units, the metal spacing units are positioned above the substrate base plate and the common electrode layer, and the first PN junction layer is positioned above the common electrode layer;
the insulating layer is positioned above the substrate base plate, the first metal layer, the common electrode layer and the first PN junction layer, the semiconductor layer is positioned above the insulating layer, and the second metal layer is positioned above the semiconductor layer and the insulating layer;
the first passivation layer is positioned above the insulating layer, the semiconductor layer and the second metal layer, the third metal layer is positioned above the first passivation layer, the third metal layer comprises a plurality of reset signal lines, and the second passivation layer is positioned above the first passivation layer and the third metal layer;
the pixel electrode layer is positioned above the second passivation layer, and each pixel electrode in the pixel electrode layer is in contact with the second metal layer and the metal spacing unit through a through hole;
the second PN junction layer is located above the pixel electrode layer, the third passivation layer is located above the second passivation layer, the pixel electrode layer and the second PN junction layer, and the first oxide conducting layer is located above the third passivation layer.
6. A liquid crystal display panel, comprising a color filter substrate, the array substrate according to any one of claims 1 to 5, and a liquid crystal layer between the array substrate and the color filter substrate, wherein the color filter substrate and the array substrate are arranged in an opposite direction.
7. The liquid crystal display panel according to claim 6, wherein a second oxide conductive layer is disposed below the color filter substrate, the second oxide conductive layer is disposed in a divisional manner, and the first oxide conductive layer and the second oxide conductive layer of the array substrate have the same pattern.
8. A liquid crystal display panel driving method applied to the liquid crystal display panel according to claim 6 or 7, the method comprising:
for each pixel unit in the liquid crystal display panel, determining a second voltage of a second electrode corresponding to the pixel unit according to a pre-display gray scale of the pixel unit and a first voltage of a first electrode corresponding to the pixel unit; the first electrode is a common electrode, the second electrode is a pixel electrode, or the first electrode is a pixel electrode, and the second electrode is a common electrode;
outputting the second voltage to the second electrode.
9. The method according to claim 8, wherein determining the second voltage of the second electrode corresponding to the pixel unit according to the pre-display gray scale of the pixel unit and the first voltage of the first electrode corresponding to the pixel unit comprises:
determining the absolute value of the voltage difference between the first electrode and the second electrode according to the pre-display gray scale of the pixel unit;
when the first electrode is a common electrode, determining the sum of the first voltage and the absolute value of the voltage difference as the second voltage;
and when the first electrode is a pixel electrode, determining the difference between the first voltage and the absolute value of the voltage difference as the second voltage.
10. A liquid crystal display device is characterized by comprising a backlight source and the liquid crystal display panel as claimed in claim 6 or 7, wherein the backlight source is positioned on one side of the array substrate, which is far away from the color film substrate.
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