CN115877614A - Display panel and display device - Google Patents

Abstract

The embodiment of the disclosure provides a display panel and a display device. The display panel comprises a first substrate and a second substrate which are oppositely arranged, wherein a first spacer on the first substrate faces the second substrate, the second substrate comprises a second base and a thin film transistor, the display panel also comprises an organic material layer positioned on the thin film transistor, the surface of the organic material layer comprises a boss part and a flat part, the area where the boss part is positioned comprises the area where the thin film transistor is positioned, and the orthographic projection of the upper end surface of the boss part and the lower end surface of the first spacer on the second base is at least partially overlapped; the second substrate further comprises a supporting part located on the surface of the flat part, the supporting part is arranged along at least part of the periphery of the boss part, and the outer edge of the orthographic projection of the supporting part on the second substrate is located on the periphery of the orthographic projection of the end face, close to the boss part, of the first spacer on the second substrate. The DNU and black Gap defects caused by uneven stress of the first spacer can be improved.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

The Liquid Crystal Display panel (LCD) includes a Display panel and a color filter substrate which are oppositely disposed, and a Liquid Crystal filled between the Display panel and the color filter substrate. In the process of manufacturing the LCD, the brightness and the transmittance of the LCD in a power-on state are controlled by controlling the liquid crystal quantity between the display panel and the color film substrate and adjusting the Cell thickness (Cell Gap) between the two substrates.

In the related art, in order to maintain uniformity of the cell thickness, a Post Spacer (PS) is disposed between the display panel and the color filter substrate. When the display panel or the color filter substrate is pressed by an external force, the display panel is prone to have Dark unevenness (DNU) and local black failure (black Gap).

Disclosure of Invention

The disclosed embodiments provide a display panel and a display device to solve or alleviate one or more technical problems in the prior art.

As a first aspect of embodiments of the present disclosure, embodiments of the present disclosure provide a display panel including:

the first substrate comprises a first base and a plurality of first shock insulators arranged on one side of the first base;

the second substrate is arranged opposite to the first substrate, the first spacer faces the second substrate, the second substrate comprises a second base and a thin film transistor arranged on one side, facing the first substrate, of the second base, the second substrate further comprises an organic material layer located on one side, facing the first base, of the thin film transistor, the surface, far away from the second base, of the organic material layer comprises a plurality of boss portions and flat portions located outside the boss portions, the orthographic projection of the boss portions on the second base comprises the orthographic projection of the thin film transistor on the second base, and the orthographic projection of the end faces, facing the first substrate, of the boss portions on the second base at least partially overlaps with the orthographic projection of the end faces, facing the second substrate, of the first spacer on the second base;

the second substrate further comprises an auxiliary layer, the auxiliary layer is located on the surface of the flat portion, the auxiliary layer comprises a supporting portion, the orthographic projection of the supporting portion on the second substrate is arranged along at least part of the periphery of the orthographic projection of the boss portion on the second substrate, and the outer edge of the orthographic projection of the supporting portion on the second substrate is located on the periphery of the orthographic projection of the end face, facing the second substrate, of the first spacer on the second substrate.

In an embodiment, a distance between a boundary of the support portion on a side close to the boss portion and the boss portion is less than or equal to 6 μm.

In one embodiment, the thickness of the support portion is less than or equal to a step between the boss portion and the flat portion.

In one embodiment, the second substrate is provided with a via hole, and a distance between an orthographic projection boundary of the support portion on the second base and an orthographic projection boundary of the via hole on the second base is greater than or equal to 5 μm.

In one embodiment, the second substrate has a light-shielding region corresponding to the black matrix, and the orthographic projection of the auxiliary layer on the second substrate is located in the light-shielding region.

In one embodiment, the black matrix is arranged on one side of the first substrate facing the second substrate, the first spacer is arranged on one side of the black matrix facing the second substrate, an orthographic projection of the first spacer on the first substrate is located in an orthographic projection range of the black matrix on the first substrate, the orthographic projection of the black matrix on the second substrate is a light shielding area, and a distance between an orthographic projection boundary of the auxiliary layer on the second substrate and a boundary of the light shielding area is greater than or equal to 2 μm.

In one embodiment, the number of the boss portions is plural, the number of the support portions is plural, and the support portions correspond to the boss portions one to one, the second substrate further includes a plurality of gate lines extending along a first direction, the auxiliary layer further includes a first connection portion, and two support portions adjacent to each other in the first direction are connected by the first connection portion.

In one embodiment, the second substrate further includes a plurality of data lines extending along a second direction, the auxiliary layer further includes a second connection portion, two support portions adjacent to each other in the second direction are connected by the second connection portion, an orthogonal projection of the second connection portion on the second base is located within an orthogonal projection range of the data line on the second base, and the second direction is perpendicular to the first direction.

In one embodiment, the material of the auxiliary layer includes a conductive material, and the auxiliary layer is in signal connection with a common electrode of the display panel.

In one embodiment, the second substrate further includes a first insulating layer, a first electrode layer, and a first alignment film, the first insulating layer is located on a side of the organic material layer and the auxiliary layer facing away from the second base, the first electrode layer is located on a side of the first insulating layer facing away from the second base, and the first alignment film is located on a side of the first electrode layer facing away from the second base.

In one embodiment, the material of the active layer of the thin film transistor comprises an oxide.

As a second aspect of the embodiments of the present disclosure, embodiments of the present disclosure provide a display device including the display panel in the embodiments of the present disclosure.

According to the technical scheme of the embodiment of the disclosure, when the display panel is pressed by external force to deform, even if the first spacer moves and deforms in a staggered manner, the relatively flat surface of the region where the boss part and the supporting part are located also can sufficiently support the first spacer, so that the first spacer can uniformly fall on the section difference stable region, the box thickness of the display panel can be effectively supported by the first spacer, and the defects of DNU and black Gap caused by uneven stress of the first spacer are improved.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference characters designate like or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

FIG. 1 is a schematic cross-sectional view of a related art LCD panel;

FIG. 2A is a schematic plan view of an array substrate using oxide TFTs;

FIG. 2B isbase:Sub>A schematic cross-sectional view taken along line A-A of the display panel shown in FIG. 2A;

FIG. 2C is a sectional difference distribution of the surface of a bump and its surrounding area relative to the surface of a pixel opening area in an array substrate using an oxide TFT;

FIG. 3A is a schematic plan view of an array substrate in a display panel according to an embodiment of the present disclosure;

FIG. 3B is a schematic plan view of an array substrate in a display panel according to another embodiment of the present disclosure;

FIG. 4 is a schematic cross-sectional view B-B of the display panel of FIG. 3A in one embodiment;

FIG. 5 is a schematic cross-sectional view of a display panel corresponding to FIG. 3A in another embodiment taken along line B-B.

Description of the reference numerals:

20. a first substrate; 21. a first substrate; 22. a color film; 23. a black matrix; 30. a second substrate; 31. a second substrate; 32. a thin film transistor; 33. an organic material layer; 331. a flat portion; 332. a boss portion; 34. auxiliary components; 341. a support portion; 342. a first connection portion; 342. a second connecting portion; 35. a first insulating layer; 36. a via hole; 411. a gate electrode; 412. a gate line; 42. a second insulating layer; 43. an active layer; 441. a source electrode; 442. a drain electrode; 443. a data line; 45. a third insulating layer; 48. a first electrode layer.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, and different embodiments may be combined arbitrarily without departing from the spirit or scope of the disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

Herein, the standing position of the spacer is a contact position of the end surface of the spacer facing the opposite substrate on the opposite substrate, and the standing position area of the spacer is an orthographic projection of the end surface of the spacer facing the opposite substrate on the opposite substrate.

Spacers (PS), bumps (hillow), width/space ratio (W/S), DNU, PS Mura, and black Gap are included in the LCD, and certain terms are explained below to facilitate a better understanding of the present disclosure.

PS: photo Spacer, spacer. In the related art, the PS is disposed on a surface of the color filter substrate facing the display panel, and the spacer is made of a resin having a certain elasticity, so as to stably support the thickness of the LCD box.

And (3) Pilow: and (4) a boss. Typically, the lands are located on the surface of the array substrate. In the direction perpendicular to the substrate, PS corresponds to the position of the boss, and the position of the PS is located on the boss surface. The difference in height of the land surface relative to the pixel opening area is referred to as a land level difference. When the display panel or the color film substrate is subjected to dislocation deformation, the higher the Pilow height is, the lower the possibility that the PS scratches the opposite side alignment film is; the larger the pilot area is, the more stable the PS station is, and the better the stability of the liquid crystal cell thickness between the display panel and the color film substrate is.

W/S: the width/gap ratio, the effective ratio of the tft switching device, is directly related to the pixel charging rate. The larger the W/S, the higher the charging rate. The chargeability of the Oxide thin film transistor is about 20 times higher than that of the amorphous silicon (a-Si) thin film transistor, so that the W/S of the Oxide thin film transistor device can be smaller than that of the amorphous silicon thin film transistor device. For example, an a-Si thin film transistor generally adopts a U-shaped TFT device, the channel of the TFT device adopts a U-shaped structure, and the W/S is 30/5; the Oxide thin film transistor adopts an I-shaped TFT device, the channel of the Oxide thin film transistor adopts an I-shaped structure, and the W/S is 10/5.

DNU: dark Not Uniformity. DNU refers to a phenomenon of uneven black state of the liquid crystal display panel under external pressure. When the display panel is pressed by external force, and the color film substrate or the display panel is dislocated, the spacer PS with the function of supporting the box thickness moves and cannot be quickly restored to an initial stable region, so that the local box thickness support and liquid crystal alignment are abnormal, and local abnormal and non-uniform brightness in a dark state is caused.

PS Mura: when the liquid crystal display panel is pressed by a violent external force, the dislocated PS scratches the alignment film on the opposite substrate, and the liquid crystal alignment is abnormal, so that the liquid crystal alignment in a black state is abnormal. Once the scratch area invades into the opening area for displaying, PS Mura defect obviously appears, liquid crystal alignment is abnormal, and blue-green-red bright spots appear. At present, due to the limitation of materials and processes, the scratch area of the alignment film can be physically shielded by widening the width and the size of a local black matrix near the PS position, and the mode causes the effective aperture opening ratio of a pixel to be reduced, the product transmittance and the specification to be obviously reduced, and the competitiveness to be reduced.

Black Gap: the liquid crystal display panel effectively supports the cell thickness by a spacer (PS) having elasticity. The spacer includes a Main spacer (Main PS) and a Sub spacer (Sub PS). When the liquid crystal display panel is pressed by a violent external force, the Main PS is gradually compressed to play a supporting role firstly; as the pressure increases, the cell thickness continues to decrease, and the Sub PS gradually comes up to support, continuously stabilizing the cell thickness and protecting the Main PS. If Main PS is over-compressed and can not be quickly restored to an initial state, the thickness of a liquid crystal box in a pressing area is low, and partial blackening can be caused.

In the related art, the spacer is disposed on the black matrix of the color filter substrate. After the color film substrate and the array substrate are arranged in a box-to-box mode, the spacer is located between the array substrate and the color film substrate. The spacer comprises a Main spacer (Main PS) and a Sub spacer (Sub PS). Normally, the main spacer is in a certain compression state to keep the uniformity of the box thickness, and a certain distance is reserved between the auxiliary spacer and the array substrate. When the panel is pressed by a vertical external force or is in a low-temperature condition, the box thickness of the panel is reduced, and the color film substrate is close to the array substrate, so that enough support cannot be provided when the main spacer is excessively pressed. At this time, the sub spacer gradually approaches the array substrate along with the color film substrate and contacts the array substrate, so as to provide enough support to maintain the uniformity of the box thickness.

In the related art, the spacer is disposed on the black matrix, and in order to avoid display defects caused by the spacer, the width of the black matrix around the spacer needs to be widened, so that the orthographic projection of the spacer on the color film substrate is located in the black matrix. The increase in the width of the black matrix reduces the aperture ratio and the transmittance. In order to maintain sufficient aperture ratio and transmittance, the main spacer may be disposed at the position of the thin film transistor, that is, the orthographic projection of the main spacer on the array substrate is disposed in the area where the thin film transistor is located, so that the standing position of the main spacer is located on the surface of the area where the thin film transistor is located, and the surface of the area where the thin film transistor is located supports the spacer. In the array substrate, the protrusion formed in the area where the thin film transistor is located can be called a boss or a boss part, and the height of the boss is larger than that of the pixel opening area, so that even if the main spacer moves in a staggered mode relative to the boss, a certain distance still exists between the main spacer and the alignment film on the surface of the pixel opening area of the array substrate, and the alignment film is not easily scratched by the main spacer. In this way, even if the width of the black matrix is additionally increased, the misalignment movement of the spacer does not need to be additionally considered, and thus, the aperture ratio is not greatly influenced. It is understood that the light transmission region of the pixel region is a pixel opening region.

Fig. 1 is a schematic cross-sectional view of a related art LCD panel. The LCD display panel includes a color film substrate 11 and an array substrate 12 which are oppositely disposed. In the related art, the array substrate 12 includes a second base 121, a thin film transistor 122 disposed on the second base 121, and an organic material layer disposed on the thin film transistor 122. The upper surface of the organic material layer has a boss 125 formed at the position of the thin film transistor 122, and a flat portion 124 is formed in a region other than the boss 125. The color filter substrate 11 includes a first substrate 111, a color filter 112 and a black matrix 113 disposed on a side of the first substrate 111 facing the array substrate 12, and a first spacer 114 disposed on a side of the black matrix 113 facing the second substrate 12. The first spacer 114 may also be referred to as a primary spacer. The thin film transistor 122 is an a-Si TFT, which generally has a "U" shape, and the channel of the TFT has a U-shape, so that the area of the boss 125 is relatively large compared to the area of the first spacer 114, and the first spacer 114 stands on the array substrate 12 and is located on the upper end surface of the boss 125. The first spacer 114 does not easily move out of the boss portion 125.

Fig. 2A is a schematic plan view of an array substrate using oxide TFTs, and fig. 2 shows a standing region of a first spacer on the array substrate; fig. 2B isbase:Sub>A schematic sectional view of the display panelbase:Sub>A-base:Sub>A corresponding to fig. 2A, and fig. 2C isbase:Sub>A step distribution of the surface of the bump and the surrounding area of the array substrate using the oxide TFT relative to the surface of the pixel opening area. For an oxide TFT, the mobility of the oxide TFT device is significantly improved by 10 to 20 times compared to the mobility of the a-Si TFT device, so that the oxide TFT adopts an "I" type structure, and its channel adopts an "I" type structure, as shown in fig. 2A. The W/S of the oxide TFT adopting the I-type structure is smaller than that of the a-Si TFT, so that the aperture opening ratio can be effectively improved. The step d1 of the mesa 125 formed by the TFT device of the "I" type structure with respect to the surface of the pixel opening area of the array substrate 20 is generally 0.2 μm to 0.5 μm. The effective uniform size of the upper end surface of the boss portion 125 is 8 μm to 9 μm, the size of the end surface of the first spacer 114 facing the array substrate 20 is 8 μm to 15 μm, and the size of the boss portion 125 is significantly small relative to the size of the first spacer 114. Therefore, although the first spacer 114 is located on the upper end surface of the boss 125, the standing area of the first spacer 114 exceeds the area of the upper end surface of the boss 125, the boss 332 cannot support the entire lower end surface of the first spacer 24, and the effective supporting area of the boss 332 on the first spacer 24 is small, so that the effective supporting area of the array substrate on the first spacer 114 is reduced, and the first spacer 24 cannot be sufficiently supported, as shown in fig. 2A and 2B.

The size of the end face of the corresponding boss portion 125 in fig. 2C is about 8 μm, and as can be seen from fig. 2C, the step d1 of the boss portion 125 and the pixel opening area is about 0.2 μm, and the change in the step of the area surface around the boss portion 125 and the pixel opening area is large, and therefore, the step of the area around the boss portion 125 is not uniform. The standing area of the first spacer 114 exceeds the area of the upper end surface of the boss portion 125, so that the uniformity and the evenness of the surface of the array substrate corresponding to the standing area of the first spacer 114 are significantly reduced. When the array substrate 20 or the color filter substrate 10 is pressed by an external force, the substrate deforms, so that the first spacer 114 is unevenly stressed, the first spacer 114 is easily displaced and moved, and even breaks away from the end surface of the boss portion 125, so that the first spacer cannot be quickly restored, and Dark unevenness (DNU) and local black defect (black Gap) are caused.

In another related art, the position of the first spacer on the array substrate is changed, and the position of the first spacer is moved from the position of the thin film transistor to the position of the relatively flat single-layer metal, but this method requires an additional increase in the width of the black matrix, which results in a decrease in the aperture ratio, and a decrease in the transmittance and product competitiveness.

In one embodiment, the display panel may further include a second spacer, and the first spacer may be called a Main spacer (Main PS) and the second spacer may be called a Sub-spacer (Sub PS). The sum of the heights of the first spacer and the boss part is greater than the height of the second spacer. Under normal conditions, the cell thickness of the display panel is supported by means of the first spacer. When the display panel is pressed by a vertical external force or is in a low-temperature condition, the box thickness of the display panel is reduced, the first substrate approaches the second substrate, so that the first spacer is excessively pressed and cannot provide enough support, or a boss part is marked in a standing area of the first spacer, and the first spacer does not contact the second substrate and cannot provide enough support. At this time, the second spacers come closer to and contact the second substrate gradually, providing sufficient support to maintain uniformity of cell thickness.

Fig. 3A is a schematic plan view of an array substrate in a display panel according to an embodiment of the disclosure, and fig. 3B is a schematic plan view of an array substrate in a display panel according to another embodiment of the disclosure; FIG. 4 is a schematic cross-sectional view B-B of the display panel of FIG. 3A in one embodiment; FIG. 5 is a schematic cross-sectional view of the display panel shown in FIG. 3A in another embodiment taken along line B-B. It should be noted that fig. 3A and 3B show one first spacer 24 and one boss portion 332, but do not represent that the number of the first spacer 24 and the boss portion 332 is one, and the number of the first spacer 24 and the boss portion 332 may be set as needed. As shown in fig. 3A and 4, the display panel may include a first substrate 20 and a second substrate 30 that are oppositely disposed.

As shown in fig. 3A and 4, the first substrate 20 includes a first base 21 and a plurality of first spacers 24 disposed on one side of the first base 21. The first spacers 24 face the second substrate 30.

As shown in fig. 3A and 4, the second substrate 30 includes a second base 31 and a thin film transistor 32 disposed on a side of the second base 31 facing the first substrate 20. The second substrate 30 further comprises an organic material layer 33 on the side of the thin film transistor 32 facing the first substrate 20, that is, the organic material layer 33 is on the side of the thin film transistor 32 facing away from the second base 31. Since the thin film transistor 32 includes the gate electrode 411, the active layer 43, the source electrode 441, and the drain electrode 442, the height of the region where the thin film transistor 32 is located is high, and thus the surface of the organic material layer 33 in the region where the thin film transistor 32 is located is high.

As shown in fig. 4, a surface of the organic material layer 33 on a side away from the second substrate 31 includes a plurality of boss portions 332 and flat portions 331 located outside the boss portions 332. The orthographic projection of the boss portion 332 on the second substrate 31 includes the orthographic projection of the thin film transistor 32 on the second substrate 31. An orthographic projection of an end face of the boss portion 332 facing the first substrate side (an upper end face of the boss portion 332 in the embodiment of fig. 4) on the second substrate 31 at least partially overlaps an orthographic projection of an end face of the first spacer 24 facing the second substrate 30 side (a lower end face of the first spacer 24 in the embodiment of fig. 4) on the second substrate 31, that is, an orthographic projection of an upper end face of the boss portion 332 on the second substrate 31 at least partially overlaps an orthographic projection of a lower end face of the first spacer 24 on the second substrate 31. Thus, the boss portion 332 can support the first spacer 24, and the standing position of the first spacer 24 is located on the upper end surface of the boss portion 332.

The orthographic projection of the upper end face of the boss portion 332 on the second substrate 31 at least partially overlaps with the orthographic projection of the lower end face of the first spacer 24 on the second substrate 31, it being understood that in the case where the orthographic area of the upper end face of the boss portion 332 on the second substrate 31 is smaller than the orthographic area of the lower end face of the first spacer 24 on the second substrate 31, all or a part of the orthographic projection of the upper end face of the boss portion 332 on the second substrate 31 overlaps with a part of the orthographic projection of the lower end face of the first spacer 24 on the second substrate 31; in the case where the area of the orthographic projection of the upper end surface of the boss portion 332 on the second substrate 31 is equal to or larger than the area of the orthographic projection of the lower end surface of the first spacer 24 on the second substrate 31, a part of the orthographic projection of the upper end surface of the boss portion 332 on the second substrate 31 overlaps a part of the orthographic projection of the lower end surface of the first spacer 24 on the second substrate 31.

An orthographic projection of the upper end surface of the boss portion 332 on the second substrate 31 at least partially overlaps with an orthographic projection of the lower end surface of the first spacer 24 on the second substrate 31, it can also be understood that an orthographic area of the upper end surface of the boss portion 332 on the second substrate 31 is equal to or larger than an orthographic area of the lower end surface of the first spacer 24 on the second substrate 31, and the orthographic projection of the lower end surface of the first spacer 24 on the second substrate 31 is located within an orthographic projection range of the upper end surface of the boss portion 332 on the second substrate 31.

As shown in fig. 3A, 3B and 4, the second substrate 30 further includes an auxiliary layer 34, and the auxiliary layer 34 is located on the surface of the flat portion 331. The auxiliary layer 34 includes a support portion 341, and an orthogonal projection of the support portion 341 on the second substrate 31 is provided along at least a partial periphery of an orthogonal projection of the boss portion 332 on the second substrate 31. Illustratively, the support portion 341 may be disposed around the entire periphery of the boss portion 332, or the support portion 341 may be disposed around a partial periphery of the boss portion 332.

In one embodiment, as shown in fig. 3A, 3B and 4, the outer edge of the orthographic projection of the supporting portion 341 on the second base 31 is located at the periphery of the orthographic projection of the end surface of the first spacer 24 on the side facing the second substrate 30 on the second base 31. This allows an orthographic projection of the lower end face of the first spacer 24 on the second substrate 31 to be located within the area defined by the outer edge of the support portion 341, and the standing position of the first spacer 24 to be located within the area defined by the outer edge of the support portion 341.

It is to be understood that the flat portion 331, although called a flat portion, does not mean that the surface of the flat portion 331 on the side away from the second substrate 31 is absolutely flat, and the surface of the flat portion 331 is a relatively flat surface.

In the display panel of the embodiment of the present disclosure, by providing the supporting portion 341 around the boss portion 332, the structure around the boss portion 332 is optimized, the step difference between the surface of the area around the boss portion 332 and the surface of the pixel opening area is improved, the step difference between the boss portion 332 and the area around the boss portion is reduced, the uniformity of the step difference between the boss portion 332 and the area around the boss portion is improved, the planarization of the standing area of the first spacer 24 is improved, and the surface uniformity and the flatness of the standing area of the first spacer 24 are improved; the effective supporting area of the second substrate 30 to the first spacer 24 is increased. Therefore, when the display panel is pressed by external force to deform, even if the first spacer 24 is displaced, moved and deformed, the relatively flat surface of the region where the boss portion 332 and the supporting portion 341 are located is enough to support the first spacer 24, so that the first spacer 24 can uniformly fall on the section difference stable region, the box thickness of the display panel can be effectively supported by the first spacer 24, and the defects of DNU and black Gap caused by uneven stress on the first spacer 24 are improved. Moreover, after the external force is removed, the relatively flat surfaces of the regions where the boss portions 332 and the supporting portions 341 are located facilitate the first spacer 24 to quickly return to the initial stable state, improving the performance of the display panel.

Exemplarily, an orthographic projection of an end face of the boss portion 332 facing the first substrate 20 side (an upper end face of the boss portion 332 in the embodiment of fig. 4) on the second base 31 overlaps with an orthographic projection of an end face of the first spacer 24 facing the second substrate 30 side (a lower end face of the first spacer 24 in the embodiment of fig. 4) on the second base 31.

In the embodiment of fig. 3A and 3B, the orthographic projection of the upper end surface of the boss portion 332 on the second substrate 31 is located within the orthographic projection range of the lower end surface of the first spacer 24 on the second substrate 31. Since the orthographic projection area of the upper end surface of the boss portion 332 on the second substrate 31 is smaller than the orthographic projection of the lower end surface of the first spacer 24 on the second substrate 31, the upper end surface of the boss portion 332 abuts against a part of the lower end surface of the first spacer 24, that is, a part of the lower end surface of the first spacer 24 abuts against the upper end surface of the boss portion 332, so that the boss portion 332 can support the first spacer 24.

In other embodiments, a part of the orthographic projection of the upper end surface of the boss portion 332 on the second substrate 31 is located within the orthographic projection range of the lower end surface of the first spacer 24 on the second substrate 31.

In one embodiment, the first substrate 20 may be a color filter substrate, and the second substrate 30 may be an array substrate.

Illustratively, the material of the first substrate 21 may include glass, organic material, or the like. For example, the material of the first substrate 21 may be glass. The material of the second substrate 31 may include glass or organic material. For example, the material of the second substrate 31 may be glass.

It is understood that the flat portion 331, although referred to as the flat portion 331, does not represent that the surface of the flat portion 331 on the side away from the second substrate 31 is absolutely flat, and the flat portion 331 is provided to obtain a relatively flat surface.

In one embodiment, as shown in fig. 3A and 3B, a distance w1 between a boundary of the supporting portion 341 on a side close to the boss portion 332 and the boss portion 332 is less than or equal to 6 μm. It is understood that in the prior art, the size of the lower end surface of the first spacer 24 is generally 8 μm to 15 μm. The distance w1 between the boss portion 332 and the boundary of the support portion 341 on the side close to the boss portion 332 is set to be less than or equal to 6 μm, so that the first spacer 24 can be supported by the support portion 341 while the first spacer 24 is displaced and detached from the boss portion 332, so that the first spacer 24 can fall on a stable region with uniform level difference, uneven stress on the first spacer 24 is avoided, and the DNU and black Gap defects of the display panel are further improved. In addition, the support portion 341 supports the first spacer 24, so that the lower end surface of the first spacer 24 is still limited to a height close to the upper end surface of the boss portion 332, which is beneficial for the first spacer 24 to rapidly return to the initial stable state after the external force is eliminated.

Illustratively, the distance w1 between the boundary of the supporting portion 341 on the side close to the boss portion 332 and the boss portion 332 may be 5 μm to 6 μm (inclusive). By adopting the arrangement mode, the area of the flat surface of the area around the boss part 332 can be increased to the maximum extent, and a wider range of support can be provided for the first spacer 24, so that the first spacer 24 always falls in the step difference stable area when the first spacer 24 is displaced.

In one embodiment, the thickness of the support portion 341 is less than or equal to the step difference d2 between the boss portion 332 and the flat portion 331. Illustratively, the step difference d2 is 0.2 μm to 0.5 μm (inclusive), for example, the step difference d2 is 0.2 μm. If the thickness of the support portion 341 is greater than the step d2 between the boss portion 332 and the flat portion 331, the height of the region where the support portion 341 is located may be greater than the height of the boss portion 332, and if the first spacer 24 is displaced due to deformation, the support portion 341 may restrict the movement of the first spacer 24, possibly damaging the first spacer 24. The thickness of the support portion 341 is set to be less than or equal to the step difference d2 between the boss portion 332 and the flat portion 331 so that the height of the area around the boss portion 332 is less than or equal to the height of the boss portion 332. Therefore, when the display panel is pressed by pressure to deform the first spacer 24, the first spacer 24 can be displaced to the region outside the boss portion 332, and the risk of excessive deformation and damage of the first spacer 24 due to failure to move is reduced.

In one embodiment, as shown in fig. 5, a boundary of the support portion 341 on a side close to the boss portion 332 and a boundary of the boss portion 332 may coincide. Therefore, when the thickness of the supporting portion 341 is equal to the step d2 between the boss portion 332 and the flat portion 331, the upper surface of the supporting portion 341 and the upper surface of the boss portion 332 can be connected to form a flat surface, which further reduces the step between the boss portion 332 and the surrounding area, improves the uniformity of the step between the boss portion 332 and the surrounding area, improves the flatness of the standing area of the first spacer 24, increases the effective supporting area of the array substrate on the first spacer 24, and better improves DNU and black Gap defects of the first spacer 24 caused by uneven stress.

In one embodiment, as shown in fig. 3A and 3B, the second substrate 30 is provided with the via hole 36, and an orthogonal projection of the support portion 341 on the second base 31 does not overlap an orthogonal projection of the via hole 36 on the second base 31, so that the support portion 341 may escape from the via hole 36. It can be understood that, at the position of the via hole 36, the surface of the flat portion 331 may have a certain degree of concavity, and if the supporting portion 341 is located at the position of the via hole 36, the supporting portion 341 at the position of the via hole 36 may not play a role of compensating for the step difference due to the concavity. By making the supporting portion 341 escape from the via hole 36, material can be saved.

In one embodiment, as shown in fig. 3, a distance d3 between an orthographic projection boundary of the support 341 on the second substrate 31 and an orthographic projection boundary of the via hole 36 on the second substrate 31 is greater than or equal to 5 μm. With such an arrangement, the supporting portion 341 can be well retracted from the via hole 36, and the film layer of the supporting portion 341 does not affect the film layer structure at the position of the via hole 36. Illustratively, the via hole 36 may include a first via hole 361 penetrating the flat portion 331, and the pixel electrode may be connected with the thin film transistor 32 through the first via hole 361. A distance d3 between an orthographic projection boundary of the support portion 341 on the second substrate 31 and an orthographic projection boundary of the first via 361 on the second substrate 31 is set to be greater than or equal to 5 μm so that the support portion 341 does not affect a signal of the conductive film layer of the first via 361.

In one embodiment, as shown in fig. 3A and 3B, the second substrate 30 has a light-shielding region 231 corresponding to the black matrix 23, and a boundary of the light-shielding region 231 is shown in fig. 3A and 3B. The orthographic projection of the auxiliary layer 34 on the second substrate 31 is located within the light-shielding region. The boundaries of the light-shielding regions are shown in fig. 3A and 3B. As can be seen from fig. 3, an orthographic projection of the supporting portion 341 on the second substrate 31 is located within the light shielding region 231. By disposing the orthographic projection of the auxiliary layer 34 on the second substrate 31 in the light shielding region 231, the auxiliary layer 34 can be prevented from affecting the aperture ratio and transmittance of the display panel.

In one embodiment, the black matrix 23 is disposed on the first substrate 20, and as shown in fig. 4, the black matrix 23 is disposed on a side of the first base 21 facing the second substrate 30. The first spacer 24 is disposed on a side of the black matrix 23 facing the second substrate 30. The orthographic projection of the first spacer 24 on the first substrate 21 is within the orthographic projection range of the black matrix 23 on the first substrate 21. The light shielding region 231 on the second substrate 30 is an orthographic projection region of the black matrix 23 on the second substrate 31. The distance d4 between the orthographic projection boundary of the auxiliary layer 34 on the second substrate 31 and the boundary of the light-shielding region is greater than or equal to 2 μm. Exemplarily, a distance d4 between a front projection boundary of the support 341 on the second substrate 31 and a boundary of the light shielding region is greater than or equal to 2 μm. Setting d4 to be greater than or equal to 2 μm can meet the process requirements, avoid the supporting portion 341 exceeding the shading area due to errors in the preparation process, and ensure that the supporting portion 341 does not affect the aperture ratio and the transmittance.

In the embodiment shown in fig. 4, the black matrix 23 is disposed on the first substrate 20. In other embodiments, the black matrix 23 may be disposed therein, for example, the black matrix 23 is disposed between the array substrate and the organic material layer 33. When the black matrix 23 is disposed in the second substrate 30, the region where the black matrix 23 is located is the light-shielding region.

In one embodiment, as shown in fig. 4, the second substrate 30 may further include a first insulating layer 35, and the first insulating layer 35 is located on a side of the organic material layer 33 and the auxiliary layer 34 facing away from the second base 31. Thus, the first insulating layer 35 may be covered with the organic material layer 33 and the auxiliary layer 34, and the station of the first spacer 24 is located on the surface of the first insulating layer 35. The first insulating layer 35 can fill up the Gap between the boss portion 332 and the support portion 341, thereby further improving the flatness of the region where the boss portion 332 and the support portion 341 are located, and further improving DNU and black Gap defects of the display panel.

In one embodiment, the number of the boss portions 332 is plural, the number of the support portions 341 is plural, and the support portions 341 correspond to the boss portions 332 one to one.

In one embodiment, as shown in fig. 3A and 3B, the second substrate 30 further includes a plurality of gate lines 412, and the gate lines 412 extend along the first direction X. The auxiliary layer 34 further includes first connection portions 342, and two support portions 341 adjacent in the first direction are connected by the first connection portions 342.

In one embodiment, as shown in fig. 3A and 3B, the second substrate 30 further includes a plurality of data lines 443, and the data lines 443 generally extend along the second direction Y. The auxiliary layer 34 further includes a second connection portion 343, and two support portions 341 adjacent in the second direction Y are connected by the second connection portion 343. The orthographic projection of the second connecting portion 343 on the second substrate 31 is within the range of the orthographic projection of the data line 443 on the second substrate 31, and the second direction Y is perpendicular to the first direction X.

It should be noted that only the light-shielding region 231 along the first direction X is shown in fig. 3A and 3B, and it is understood that the second substrate 30 further includes a light-shielding region generally along the second direction Y, and the data line 443 and the second connection portion 343 in the second substrate may be located in the light-shielding region along the second direction Y.

In this way, the orthographic projection of the first connecting portion 342 on the second substrate 31 is located in the light shielding region 231, and the orthographic projection of the second connecting portion 343 on the second substrate 31 is also located in the light shielding region 231. Neither the first connection portion 342 nor the second connection portion 343 affects the aperture ratio and the transmittance of the display panel.

With this structure, the supporting portions 341 are connected to each other by the first and second connecting portions 342 and 343, so that the auxiliary layer 34 has a grid shape, as shown in fig. 3A.

In one embodiment, the material of the auxiliary layer 34 may include a conductive material. Illustratively, the material of the auxiliary layer 34 may include a metal, such as copper or aluminum. The auxiliary layer 34 may be in signal connection with a common electrode of the display panel. The auxiliary layer 34 has a mesh structure over the entire surface, and the auxiliary layer 34 is connected to the common electrode signal, so that the in-plane uniformity of the common signal can be improved, and the signal crosstalk can be improved.

In one embodiment, as shown in fig. 3A, 3B and 4, the second substrate 30 may further include a first electrode layer 48 and a first alignment film. The first electrode layer 48 is located on a side of the first insulating layer 35 facing away from the second substrate 31, and the first alignment film is located on a side of the first electrode layer 48 facing away from the second substrate 31. Illustratively, the first electrode layer 48 may be a pixel electrode, and the pixel electrode may be connected to the thin film transistor 32 through a first via hole.

In one embodiment, as shown in fig. 4, the thin film transistor 32 may include a gate electrode 411, an active layer 43, a source electrode 441, and a drain electrode 442. Illustratively, the material of the active layer 43 may include an oxide. For example, the material of the active layer 43 may include an indium gallium zinc oxide material (IGZO) or an amorphous indium gallium zinc oxide material (a-IGZO). The channel region of the active layer 43 may be of an "I" type as shown in fig. 3A and 3B, that is, the channel region of the active layer 43 has a stripe structure.

The technical solution of the embodiment of the present disclosure is further explained by the manufacturing process of the second substrate 30 shown in fig. 4. It is to be understood that "patterning" as used herein includes processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. when the material to be patterned is an inorganic material or a metal, and includes processes of mask exposure, development, etc. when the material to be patterned is an organic material, and evaporation, deposition, coating, etc. as used herein are well-known in the relevant art.

The thin film transistor 32 is fabricated on one side of the second substrate 31. Illustratively, this step may include: a first metal layer, a second insulating layer 42, an active layer 43, a second metal layer, and a third insulating layer 45 are sequentially formed on one side of the second substrate 31, as shown in fig. 4. Wherein the first metal layer includes a gate electrode 411 and a gate line 412. The second insulating layer 42 may also be called a gate insulating layer (GI). The second metal layer includes a source electrode 441, a drain electrode 442, a connection line (not shown) connected to the drain electrode 442, and a data line 443. The third insulating layer 45 may be called a first passivation layer (PVX 1).

The organic material layer 33 is formed by coating on the side of the third insulating layer 45 away from the second substrate 31, and since the thin film transistor 32 includes the gate electrode 411, the active layer 43, the source electrode 441, and the drain electrode 442, the surface of the organic material layer 33 on the side away from the second substrate 31 includes the convex portion 332 and the flat portion 331 located outside the convex portion 332. The orthographic projection of the boss portion 332 on the second substrate 31 includes the orthographic projection of the thin film transistor 32 on the second substrate 31, as shown in fig. 4.

The auxiliary layer 34 is formed on the surface of the flat portion 331 of the organic material layer 33, and the auxiliary layer 34 includes a support portion 341, as shown in fig. 4. Illustratively, an auxiliary film may be deposited on a side of the organic material layer 33 facing away from the second substrate 31, and the auxiliary film may be patterned to form the auxiliary layer 34.

A first insulating layer 35 is deposited on the side of the auxiliary layer 34 facing away from the second substrate 31, and the first insulating layer 35 may be patterned to form the required vias. The first insulating layer 35 may be called a second passivation layer (PVX 2).

A first electrode layer 48 is formed on a side of the first insulating layer 35 facing away from the second substrate 31, and the first electrode layer 48 may include a pixel electrode, and the pixel electrode may be connected to the corresponding thin film transistor 32 through a via hole. For example, the material of the first electrode layer 48 may include a transparent conductive material, and for example, the material of the first electrode layer 48 may include Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like.

A first alignment film is coated on the side of the first electrode layer 48 facing away from the second substrate 31. The material of the first alignment film may include Polyimide (PI).

In an exemplary embodiment, the first, second, and third insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The gate electrode, the source electrode, and the drain electrode may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, or the like.

Based on the inventive concept of the foregoing embodiments, the embodiments of the present disclosure further provide a display device. The display device includes the display panel of the foregoing embodiment, and may further include a liquid crystal between the first substrate and the second substrate.

The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the description of the present specification, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, are used based on the orientations and positional relationships shown in the drawings, and are used merely for convenience of description and simplicity of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be considered as limiting the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood as a specific case by a person of ordinary skill in the art.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.

While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (12)

1. A display panel, comprising:

the first substrate comprises a first base and a plurality of first shock insulators arranged on one side of the first base;

a second substrate disposed opposite to the first substrate, the first spacer facing the second substrate, the second substrate including a second base and a thin film transistor disposed on a side of the second base facing the first substrate, the second substrate further including an organic material layer on a side of the thin film transistor facing the first substrate, a surface of the organic material layer on a side facing away from the second base including a plurality of boss portions and a flat portion outside the boss portions, an orthographic projection of the boss portions on the second base including an orthographic projection of the thin film transistor on the second base, an orthographic projection of an end face of the boss portion on a side facing the first substrate on the second base at least partially overlapping an orthographic projection of an end face of the first spacer on a side facing the second substrate on the second base;

the second substrate further comprises an auxiliary layer located on the flat surface, the auxiliary layer comprises a supporting portion, the orthographic projection of the supporting portion on the second substrate is arranged along at least part of the periphery of the orthographic projection of the boss portion on the second substrate, and the outer edge of the orthographic projection of the supporting portion on the second substrate is located on the periphery of the orthographic projection of the end face, facing the second substrate, of the first spacer on the second substrate.

2. The display panel according to claim 1, wherein a distance between a boundary of the support portion on a side close to the boss portion and the boss portion is less than or equal to 6 μm.

3. The display panel according to claim 1, wherein a thickness of the supporting portion is smaller than or equal to a step difference between the boss portion and the flat portion.

4. The display panel according to claim 1, wherein the second substrate is provided with a via, and a distance between an orthographic projection boundary of the support portion on the second base and an orthographic projection boundary of the via on the second base is greater than or equal to 5 μm.

5. The display panel according to claim 1, wherein the second substrate has a light-shielding region corresponding to a black matrix, and an orthogonal projection of the auxiliary layer on the second substrate is located in the light-shielding region.

6. The display panel according to claim 5, wherein the black matrix is disposed on a side of the first substrate facing the second substrate, the first spacer is disposed on a side of the black matrix facing the second substrate, an orthogonal projection of the first spacer on the first substrate is within an orthogonal projection range of the black matrix on the first substrate, the orthogonal projection of the black matrix on the second substrate is the light shielding region, and a distance between an orthogonal projection boundary of the auxiliary layer on the second substrate and a boundary of the light shielding region is greater than or equal to 2 μm.

7. The display panel according to claim 1, wherein the number of the boss portions is plural, the number of the support portions is plural, and the support portions correspond to the boss portions one to one, wherein the second substrate further includes a plurality of gate lines extending in a first direction, wherein the auxiliary layer further includes first connection portions, and wherein two of the support portions adjacent to each other in the first direction are connected by the first connection portions.

8. The display panel according to claim 7, wherein the second substrate further includes a plurality of data lines extending in a second direction, wherein the auxiliary layer further includes a second connection portion through which two adjacent support portions in the second direction are connected, wherein an orthogonal projection of the second connection portion on the second substrate is within an orthogonal projection range of the data lines on the second substrate, and wherein the second direction is perpendicular to the first direction.

9. The display panel according to claim 7, wherein the material of the auxiliary layer comprises a conductive material, and the auxiliary layer is in signal connection with a common electrode of the display panel.

10. The display panel according to claim 1, wherein the second substrate further comprises a first insulating layer, a first electrode layer, and a first alignment film, the first insulating layer is located on a side of the organic material layer and the auxiliary layer facing away from the second substrate, the first electrode layer is located on a side of the first insulating layer facing away from the second substrate, and the first alignment film is located on a side of the first electrode layer facing away from the second substrate.

11. The display panel according to claim 1, wherein a material of the active layer of the thin film transistor comprises an oxide.

12. A display device characterized by comprising the display panel according to any one of claims 1 to 11.

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