CN115877185B - Flexible comparison method and device suitable for chip detection - Google Patents
Flexible comparison method and device suitable for chip detection Download PDFInfo
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Abstract
The application provides a flexible comparison method and device suitable for chip detection, comprising the following steps: the detection circuit board comprises a data processing module, a comparison module and at least one chip interface to be detected, wherein the data processing module, the comparison module and the at least one chip interface to be detected are connected with the storage module; the method comprises the following steps: the comparison module is pre-provided with a calculation threshold value, and selects a comparison place and a comparison mechanism of output data of the chip to be tested according to the current calculation value; and/or the comparison module is preset with an accuracy threshold value, and the comparison module selects a comparison place and a comparison mechanism of the output data of the chip to be tested according to the input accuracy value. According to the current calculated force value and the set precision value of the comparison module, different comparison places are selected, when the comparison module of the detection circuit board is used for comparison, the output data of the chip to be detected is not required to be transmitted to an external computer, the reduction of comparison efficiency caused by the limitation of the transmission rate of wires or interfaces is avoided, and the detection of the chip to be detected is more flexible.
Description
Technical Field
The application relates to the field of chip detection, in particular to a flexible comparison method and device suitable for chip detection.
Background
In recent decades, as the performance of chips is continuously improved, the limit of moore's law is approached, and the higher the performance, the more difficult the chips are to be produced due to the production process, the lower the yield, and in order to ensure the yield of the chips from the factory, the chips need to be detected after the production is completed.
In the traditional chip detection technology, a comprehensive verification code is compiled by constructing a software function test platform, the design is needed according to an implementation block diagram of the software function test platform, an external computer inputs detection data to a chip to be detected, the operation detection data of the chip to be detected obtain output data, the output data is transmitted to the external computer and is compared with the known verification data, and finally, a set of system platform capable of carrying out hardware function test on the chip is completed.
The traditional chip detection technology has the defects that after the design is finished, the chip detection mode is too single, and when the chip is detected, the verification data is compared with the output data of the chip to be detected by an external system, so that the comparison mode is not flexible.
Disclosure of Invention
The embodiment of the application aims to provide a flexible comparison method and device suitable for chip detection, which are used for realizing the technical effect of flexible comparison of chips to be detected.
The embodiment of the application provides a flexible comparison method suitable for chip detection, which comprises the following steps: the detection circuit board comprises a data processing module, a comparison module and at least one chip interface to be detected, wherein the data processing module is connected with a storage module, the storage module is used for storing detection data transmitted by the data processing module, the data processing module is connected with an external computer, and verification data is preset in the comparison module and connected with the chip interface to be detected; the method comprises the following steps: the comparison module is pre-provided with a calculation threshold value, and selects a comparison place and a comparison mechanism of output data of the chip to be tested according to the current calculation value; and/or the comparison module is preset with an accuracy threshold value, and the comparison module selects a comparison place and a comparison mechanism of the output data of the chip to be tested according to the input accuracy value; and the comparison place of the output data of the chip to be tested is the detection circuit board or an external computer.
In the implementation process, the detection circuit board comprises a data processing module, a comparison module and at least one chip interface to be detected, wherein the data processing module is connected with the storage module, the data processing module can be a Central Processing Unit (CPU), and an operating system is arranged in the data processing module to generate detection data. The storage module is used for storing the detection data transmitted by the data processing module, the comparison module can be a chip, verification data is preset in the comparison module, and the comparison module is connected with the chip interface to be tested. After the detection data is transmitted to the chip to be detected from the storage module, the chip to be detected runs the detection data and outputs the data, and the comparison module compares the verification data with the output data of the chip to be detected. The comparison module is internally preset with a calculation force threshold value, can detect the current calculation force value in real time through an internal calculation force calculation module, and selects a comparison place and a comparison mechanism of output data of the chip to be tested when the comparison module detects that the current calculation force value is higher than the calculation force threshold value or lower than the calculation force threshold value. The comparison module is preset with an accuracy threshold value, and according to the currently set accuracy value, the comparison module selects a comparison place and a comparison mechanism of the output data of the chip to be tested. The comparison place is a detection circuit board or an external computer, and when the comparison place is selected on the detection circuit board, the verification data preset in the comparison module is compared with the output data of the chip to be detected on the detection circuit board; when the comparison place is selected in the external computer, verification data are preset in the external computer, the output data of the chip to be tested are transmitted to the external computer through the data processing module, and the verification data of the external computer are compared with the output data of the chip to be tested. According to the current calculated force value and the set precision value of the comparison module, different comparison places are selected, and when the comparison module of the detection circuit board is used for comparison, the output data of the chip to be detected is not required to be transmitted to an external computer, so that the reduction of the comparison efficiency caused by the limitation of the transmission rate of wires or interfaces is avoided. By selecting different comparison places, the chip to be detected can be detected more flexibly.
In one possible implementation, the alignment mechanism includes: the first comparison mechanism is used for comparing the verification data with the output data of the chip to be tested and recording all comparison results; the second comparison mechanism is used for comparing the verification data with the output data of the chip to be tested in a low-bit mode, and recording all comparison results when the low-bit or high-bit or formed bit is inconsistent; the third comparison mechanism is used for comparing the verification data with the output data of the chip to be tested, recording all inconsistent comparison results, and sending a comparison consistent signal to the data processing module if the comparison results are completely consistent; a fourth comparison mechanism, wherein the comparison module compares the verification data with the output data of the chip to be tested in a low bit position, and when the low bit position or the high bit position or the bit positions formed by the low bit position or the high bit position are inconsistent, all the comparison inconsistent results are recorded; and the fifth comparison mechanism is used for transmitting the output data of the chip to be tested to an external computer, wherein the external computer is preset with verification data, and the external computer is used for comparing the verification data with the output data of the chip to be tested and recording all comparison results.
In the implementation process, the comparison mechanism comprises five types, wherein the comparison points of the first comparison mechanism, the second comparison mechanism, the third comparison mechanism and the fourth comparison mechanism are on the detection circuit board, the first comparison mechanism is used for comparing the verification data with the output data of the chip to be tested in the four comparison mechanisms, all comparison results are recorded and comprise complete consistency and complete inconsistency, the comparison accuracy of the first comparison mechanism is the highest, and the corresponding consumption calculation force is the largest. The third comparison mechanism is used for comparing the verification data with the output data of the chip to be tested, recording all inconsistent comparison results, if the comparison results are completely consistent, the comparison module sends a comparison consistent signal to the data processing module, the comparison module only records inconsistent comparison results, the consumed calculation force is correspondingly reduced, the consumed calculation force is lower than that of the first comparison mechanism, and the precision is lower than that of the first comparison mechanism. The second comparison mechanism is used for comparing the verification data with the output data of the chip to be tested in a low bit mode, when any one of the low bit, the high bit and the bit formed by a plurality of components is inconsistent, the three components comprise the low bit or the high bit or the bit formed by the components is inconsistent, namely, a preliminary inconsistent result is obtained, all comparison results are recorded, the second comparison mechanism can extract the low bit data in the output data of the chip to be tested, quick comparison is carried out, and due to the extracted result, a conclusion that the chip to be tested has no problem can not be obtained when the comparison results are consistent, only the preliminary consistency of comparison can be obtained for data backtracking and analysis, if the fact that the chip to be tested has no problem is required to be confirmed, the first comparison mechanism is required to be detected again, or the consumed calculation force is lower than that of the third comparison mechanism through the transmission of the data processing module to an external computer, and the precision is lower than that of the third comparison mechanism. The fourth comparison mechanism compares the verification data with the output data of the chip to be tested in a low bit mode, when any one of the low bit, the high bit or a plurality of bit inconsistencies occurs, the three comprise the low bit, the high bit or the bit inconsistencies, a preliminary inconsistence conclusion is obtained, all comparison inconsistence results are recorded, and due to the fact that the result is the extraction result, when the comparison results are consistent, a conclusion that the chip to be tested has no problem can not be obtained, only the preliminary consistency of comparison can be obtained, and due to the fact that the extraction result is the extraction result and only the comparison inconsistence results are recorded, the consumption of calculation force is minimum, and the precision is minimum. The fifth comparison mechanism is used for transmitting the output data of the chip to be tested to an external computer, the external computer is preset with verification data, the external computer compares the verification data with the output data of the chip to be tested and records all comparison results, the fifth comparison mechanism does not need to be used for comparison, and when the comparison module is deficient in current calculation force due to overhigh temperature, the comparison module can be stopped and is converted into the comparison of the external computer, so that the comparison is always in a high-speed comparison state. By setting five different comparison mechanisms, different comparison mechanisms can be selected according to different requirements, and the device is more flexible and rapid to use.
In one possible implementation manner, the comparison module detects that the current calculation force value is lower than the calculation force threshold value, and the comparison location of the output data of the chip to be tested is converted into an external computer by the detection circuit board; and/or the comparison module detects that the currently input precision value is higher than the precision threshold value, and the comparison location of the output data of the chip to be tested is converted into an external computer by the detection circuit board.
In the implementation process, the comparison module detects that the current calculated force value is lower than the calculated force threshold value, and the comparison place of the output data of the chip to be tested is converted into an external computer by the detection circuit board. When the comparison module is too high in operation temperature and the calculation force is reduced, the comparison site is converted into an external computer, so that a high-efficiency comparison state is maintained, and when the comparison module is stopped to operate for a period of time and is cooled, the comparison site can be converted into the comparison module again. The comparison module detects that the currently input precision value is higher than the precision threshold value, and the comparison place of the output data of the chip to be tested is converted into an external computer by the detection circuit board. When higher comparison precision is needed, a precision value higher than a precision threshold value can be input, and a comparison place is converted into an external computer from the detection circuit board, so that higher-precision comparison is performed. By setting the force calculation threshold and the precision threshold, the comparison place can be flexibly selected according to different requirements, and the use is more convenient.
In one possible implementation manner, the comparison module defaults to the third comparison mechanism, and after the comparison module runs out of the third comparison mechanism, the comparison module detects a current calculated force value; when the current calculated force value of the comparison module is lower than a calculated force threshold value, the fifth comparison mechanism is adopted by the comparison module; and when the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison module adopts the first comparison mechanism or the second comparison mechanism for comparison again.
In the implementation process, in order to save the calculation force of the comparison module, a third comparison mechanism is adopted by the comparison module by default, after the comparison module runs out of the third comparison mechanism, a preliminary conclusion is obtained, such as the comparison is consistent, a small amount of inconsistencies, a large amount of inconsistencies and the like, the comparison module detects the current calculation force value, and when the current calculation force value of the comparison module is lower than the calculation force threshold value, a fifth comparison mechanism is adopted to keep the high-speed comparison of the chip to be tested, and the comparison place is converted into an external computer. When the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison can be performed again by adopting a first comparison mechanism or a second comparison mechanism, and the comparison result precision is higher through twice comparison. Different comparison mechanisms are selected by comparing the current calculated force values of the comparison modules, so that the comparison is more flexible and flexible.
In one possible implementation manner, the comparison module defaults to the fourth comparison mechanism, and after the comparison module runs out of the fourth comparison mechanism, the comparison module detects a current calculated force value; when the current calculated force value of the comparison module is lower than the calculated force threshold value, the comparison module adopts the fifth comparison mechanism for comparison again; and when the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison module adopts the first comparison mechanism or the second comparison mechanism for comparison again.
In the implementation process, in order to save the calculation force of the comparison module, a fourth comparison mechanism is adopted by the comparison module by default, after the comparison module runs out of the fourth comparison mechanism, a preliminary conclusion is obtained, such as the comparison is consistent, a small amount of inconsistencies, a large amount of inconsistencies and the like, the comparison module detects the current calculation force value, and when the current calculation force value of the comparison module is lower than the calculation force threshold value, a fifth comparison mechanism is adopted in order to keep the high-speed comparison of the chip to be tested, and the comparison place is converted into an external computer. When the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison can be performed again by adopting a first comparison mechanism or a second comparison mechanism, and the comparison result precision is higher through twice comparison. Different comparison mechanisms are selected by comparing the current calculated force values of the comparison modules, so that the comparison is more flexible and flexible.
In one possible implementation manner, the comparison module defaults to the first comparison mechanism, and after the comparison module runs out of the first comparison mechanism, if the accuracy value of the detection input of the comparison module is lower than the accuracy threshold, the comparison module adopts the third comparison mechanism or the fourth comparison mechanism to compare again.
In the implementation process, in order to maintain high-precision comparison, the comparison module defaults to a first comparison mechanism. After the comparison module runs the first comparison mechanism, if the comparison module detects that the input precision value is lower than the precision threshold value, the comparison module is converted into a third comparison mechanism or a fourth comparison mechanism; the operation time can be preset, and the verification data is consistent with the output data of the chip to be tested in the preset operation time, so that the chip to be tested has no error for a long time, the quality of the chip is high, and the comparison module is converted into a third comparison mechanism or a fourth comparison mechanism, so that the calculation force is saved. Different comparison mechanisms are selected by setting different precision values, so that the comparison is more flexible.
In one possible implementation manner, the comparison module defaults to the second comparison mechanism, and after the comparison module runs out of the second comparison mechanism, if the accuracy value of the detection input of the comparison module is lower than the accuracy threshold, the comparison module adopts the third comparison mechanism or the fourth comparison mechanism to compare again.
In the implementation process, in order to maintain high-precision comparison, the comparison module defaults to a second comparison mechanism. After the comparison module runs the second comparison mechanism, if the comparison module detects that the input precision value is lower than the precision threshold value, the comparison module is converted into a third comparison mechanism or a fourth comparison mechanism; the operation time can be preset, and the verification data is consistent with the output data of the chip to be tested in the preset operation time, so that the chip to be tested has no error for a long time, the quality of the chip is high, and the comparison module is converted into a third comparison mechanism or a fourth comparison mechanism, so that the calculation force is saved. Different comparison mechanisms are selected by setting different precision values, so that the comparison is more flexible.
In one possible implementation manner, the comparison module is preset with an error rate threshold, the comparison module detects that the current error rate is higher than the error rate threshold, and the comparison module continues to compare by adopting the first comparison mechanism or the second comparison mechanism.
In the implementation process, the comparison module is preset with an error rate threshold value, and can detect the error rate in real time in the comparison process, and the error rate is calculated in the following manner: when the current error rate is higher than the error rate threshold value, the error rate of the chip to be tested is higher, and the comparison module adopts a first comparison mechanism or a second comparison mechanism to carry out high-precision comparison. The proper comparison mechanism is selected by calculating the error rate in real time, so that the method is more flexible to use.
In one possible implementation manner, the external computer obtains the average error rate of the chip to be tested in the past, and when the average error rate is lower than an error rate threshold, the comparison module adopts the third comparison mechanism or the fourth comparison mechanism; and when the average error rate is higher than an error rate threshold, the comparison module continues to compare by adopting the first comparison mechanism or the second comparison mechanism.
In the implementation process, the external computer can acquire the average error rate of the chip to be tested of the model through the internet, or calculate the average error rate through the test result of the chip in the past, and the calculation mode of the average error rate is as follows: the sum of all chip error rates/total chip. When the average error rate is lower than the error rate threshold, the chip error rate is lower, and the comparison module adopts a third comparison mechanism or a fourth comparison mechanism to save calculation force. When the average error rate is higher than the error rate threshold, the chip error rate is higher, and the comparison module adopts a first comparison mechanism or a second comparison mechanism to maintain high-precision comparison. The average error rate of the chip is obtained, so that a comparison mechanism can be selected more flexibly, and the use is more convenient and accurate.
In a second aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the method according to any one of the first aspects when executing the computer program.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a flexible comparison method suitable for chip detection provided in an embodiment of the present application;
fig. 2 is a structural diagram of a detection circuit board provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, an embodiment of the present application provides a flexible comparison method suitable for chip detection, please refer to fig. 1 and fig. 2, including: based on a detection circuit board, the detection circuit board comprises a data processing module, a comparison module and at least one chip interface to be detected, wherein the data processing module is connected with a storage module; the method comprises the following steps: the comparison module is pre-provided with a calculation threshold value, and selects a comparison place and a comparison mechanism of the output data of the chip to be tested according to the current calculation value; the comparison module is pre-provided with an accuracy threshold value, and selects a comparison place and a comparison mechanism of output data of the chip to be tested according to the input accuracy value; the comparison place of the output data of the chip to be tested is a detection circuit board or an external computer.
In one possible implementation, the method includes: the comparison module is pre-provided with a calculation threshold value, and selects a comparison place and a comparison mechanism of the output data of the chip to be tested according to the current calculation value; the comparison place of the output data of the chip to be tested is a detection circuit board or an external computer.
In one possible implementation, the method includes: the comparison module is pre-provided with an accuracy threshold value, and selects a comparison place and a comparison mechanism of output data of the chip to be tested according to the input accuracy value; the comparison place of the output data of the chip to be tested is a detection circuit board or an external computer.
In the implementation process, the detection circuit board comprises a data processing module, a comparison module and at least one chip interface to be detected, wherein the data processing module is connected with the storage module, the data processing module can be a Central Processing Unit (CPU), and an operating system is arranged in the data processing module to generate detection data. The storage module is used for storing the detection data transmitted by the data processing module, the comparison module can be a chip, verification data is preset in the comparison module, and the comparison module is connected with the chip interface to be tested. After the detection data is transmitted to the chip to be detected from the storage module, the chip to be detected runs the detection data and outputs the data, and the comparison module compares the verification data with the output data of the chip to be detected. The comparison module is internally preset with a calculation threshold value and can detect the current calculation force value in real time through an internal calculation force calculation module, and the calculation force is used for measuring the calculation capacity of a chip and is generally divided into TOPS, FLOPS, MACS, DMIPIS calculation force units. TOPS represents the number of operations that can be completed per second. 1TOPS indicates that 1 trillion operations are performed per second. Corresponding to this, GOPS (Giga Operations Per Second), MOPS (Million Operation PerSecond) units of force are also provided. 1GOPS represents a billion operations per second of the processor, 1MOPS represents a million operations per second of the processor, and TOPS, which can be converted from GOPS and MOPS, both represent the number of times per second that can be processed. When the comparison module detects that the current calculated force value is higher than the calculated force threshold value or lower than the calculated force threshold value, the comparison module selects a comparison place and a comparison mechanism of the output data of the chip to be tested. The comparison module is preset with an accuracy threshold value, and according to the currently set accuracy value, the comparison module selects a comparison place and a comparison mechanism of the output data of the chip to be tested. Precision is used to measure how fine a chip computes, typically as int4, int8, int16, fp8, fp16, fp32, fp64 and fp128.Int8 generally refers to a fixed point number with a bit width of 8 bits, and definition of Int4 and Int16 is similar to that, wherein Int8 is the most commonly used precision of a computing chip. fp8 generally refers to a floating point number of 8 bits in bit width, fp16, fp32, fp64 and fp128 being defined similarly. Floating point numbers are digital representations of numbers belonging to a particular subset of rational numbers, used in a computer to approximate any real number. In particular, this real number is obtained by multiplying an integer or fixed point number (i.e. mantissa) by the integer power of a certain radix (usually 2 in a computer), this representation being similar to the scientific counting method with a radix of 10. In general, floating point number precision of the same bit width is higher than fixed point number, and floating point number calculation cost is larger. The comparison place is a detection circuit board or an external computer, and when the comparison place is selected on the detection circuit board, the verification data preset in the comparison module is compared with the output data of the chip to be detected on the detection circuit board; when the comparison place is selected in the external computer, verification data are preset in the external computer, the output data of the chip to be tested are transmitted to the external computer through the data processing module, and the verification data of the external computer are compared with the output data of the chip to be tested. According to the current calculated force value and the set precision value of the comparison module, different comparison places are selected, and when the comparison module of the detection circuit board is used for comparison, the output data of the chip to be detected is not required to be transmitted to an external computer, so that the reduction of the comparison efficiency caused by the limitation of the transmission rate of wires or interfaces is avoided. By selecting different comparison places, the chip to be detected can be detected more flexibly.
In one possible implementation, the alignment mechanism includes: the first comparison mechanism is used for comparing the verification data with the output data of the chip to be tested and recording all comparison results; the second comparison mechanism is used for comparing the verification data with the output data of the chip to be tested in a low bit mode, and when any one of the low bit, the high bit and the bit formed by the high bit is inconsistent, the three bits comprise the low bit or the high bit or the bit formed by the high bit is inconsistent, and all comparison results are recorded; the third comparison mechanism compares the verification data with the output data of the chip to be tested, records all inconsistent comparison results, and if the comparison results are completely consistent, the comparison module sends a comparison consistent signal to the data processing module; a fourth comparison mechanism, wherein the comparison module compares the verification data with the output data of the chip to be tested in low bit position, and when any one of the low bit position, the high bit position and the bit position inconsistency formed by the high bit position and the high bit position is formed by the low bit position, the high bit position and the bit position inconsistency formed by the high bit position and the high bit position, and records all the results of the comparison inconsistency; and the fifth comparison mechanism is used for transmitting the output data of the chip to be tested to an external computer, the external computer is preset with verification data, and the external computer is used for comparing the verification data with the output data of the chip to be tested and recording all comparison results.
In the implementation process, the comparison mechanism comprises five types, wherein the comparison points of the first comparison mechanism, the second comparison mechanism, the third comparison mechanism and the fourth comparison mechanism are on the detection circuit board, the first comparison mechanism is used for comparing the verification data with the output data of the chip to be tested in the four comparison mechanisms, all comparison results are recorded and comprise complete consistency and complete inconsistency, the comparison accuracy of the first comparison mechanism is the highest, and the corresponding consumption calculation force is the largest. The third comparison mechanism is used for comparing the verification data with the output data of the chip to be tested, recording all inconsistent comparison results, if the comparison results are completely consistent, the comparison module sends a comparison consistent signal to the data processing module, the comparison module only records inconsistent comparison results, the consumed calculation force is correspondingly reduced, the consumed calculation force is lower than that of the first comparison mechanism, and the precision is lower than that of the first comparison mechanism. The second comparison mechanism is used for comparing the verification data with the output data of the chip to be tested in a low bit mode, when any one of the low bit, the high bit and the bit formed by a plurality of components is inconsistent, the three components comprise the low bit or the high bit or the bit formed by the components is inconsistent, namely, a preliminary inconsistent result is obtained, all comparison results are recorded, the second comparison mechanism can extract the low bit data in the output data of the chip to be tested, quick comparison is carried out, and due to the extracted result, a conclusion that the chip to be tested has no problem can not be obtained when the comparison results are consistent, only the preliminary consistency of comparison can be obtained for data backtracking and analysis, if the fact that the chip to be tested has no problem is required to be confirmed, the first comparison mechanism is required to be detected again, or the consumed calculation force is lower than that of the third comparison mechanism through the transmission of the data processing module to an external computer, and the precision is lower than that of the third comparison mechanism. The fourth comparison mechanism compares the verification data with the output data of the chip to be tested in a low bit mode, when any one of the low bit, the high bit and the bit formed by a plurality of components is inconsistent, the three components comprise the low bit or the high bit or the bit formed by the components is inconsistent, a preliminary inconsistent conclusion is obtained, all inconsistent comparison results are recorded, and due to the fact that the result is the extraction result, when the comparison results are consistent, a conclusion that the chip to be tested has no problem can not be obtained, only the preliminary consistency of comparison can be obtained, and due to the fact that the extraction result and only the inconsistent comparison results are recorded, the consumption of calculation force is minimum, and the precision is minimum. The fifth comparison mechanism is used for transmitting the output data of the chip to be tested to an external computer, the external computer is preset with verification data, the external computer compares the verification data with the output data of the chip to be tested and records all comparison results, the fifth comparison mechanism does not need to be used for comparison, and when the comparison module is deficient in current calculation force due to overhigh temperature, the comparison module can be stopped and is converted into the comparison of the external computer, so that the comparison is always in a high-speed comparison state. By setting five different comparison mechanisms, different comparison mechanisms can be selected according to different requirements, and the device is more flexible and rapid to use.
In one possible implementation manner, the comparison module detects that the current calculation force value is lower than the calculation force threshold value, and the comparison place of the output data of the chip to be tested is converted into an external computer by the detection circuit board; the comparison module detects that the currently input precision value is higher than the precision threshold value, and the comparison place of the output data of the chip to be tested is converted into an external computer by the detection circuit board.
In one possible implementation, the comparison module detects that the current calculation force value is lower than the calculation force threshold value, and the comparison place of the output data of the chip to be tested is converted into an external computer by the detection circuit board.
In one possible implementation, the comparison module detects that the currently input precision value is higher than the precision threshold, and the comparison place of the output data of the chip to be tested is converted into an external computer by the detection circuit board.
In the implementation process, the comparison module detects that the current calculated force value is lower than the calculated force threshold value, and the comparison place of the output data of the chip to be tested is converted into an external computer by the detection circuit board. When the comparison module is too high in operation temperature and the calculation force is reduced, the comparison site is converted into an external computer, so that a high-efficiency comparison state is maintained, and when the comparison module is stopped to operate for a period of time and is cooled, the comparison site can be converted into the comparison module again. The comparison module detects that the currently input precision value is higher than the precision threshold value, and the comparison place of the output data of the chip to be tested is converted into an external computer by the detection circuit board. When higher comparison precision is needed, a precision value higher than a precision threshold value can be input, and a comparison place is converted into an external computer from the detection circuit board, so that higher-precision comparison is performed. By setting the force calculation threshold and the precision threshold, the comparison place can be flexibly selected according to different requirements, and the use is more convenient.
In one possible implementation, the comparison module defaults to a third comparison mechanism, and detects the current calculated force value after the comparison module runs out of the third comparison mechanism; when the current calculated force value of the comparison module is lower than the calculated force threshold value, the comparison module adopts a fifth comparison mechanism; when the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison module adopts a first comparison mechanism or a second comparison mechanism for comparison again.
In the implementation process, in order to save the calculation force of the comparison module, a third comparison mechanism is adopted by the comparison module by default, after the comparison module runs out of the third comparison mechanism, a preliminary conclusion is obtained, such as the comparison is consistent, a small amount of inconsistencies, a large amount of inconsistencies and the like, the comparison module detects the current calculation force value, and when the current calculation force value of the comparison module is lower than the calculation force threshold value, a fifth comparison mechanism is adopted to keep the high-speed comparison of the chip to be tested, and the comparison place is converted into an external computer. When the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison can be performed again by adopting a first comparison mechanism or a second comparison mechanism, and the comparison result precision is higher through twice comparison. Different comparison mechanisms are selected by comparing the current calculated force values of the comparison modules, so that the comparison is more flexible and flexible.
In one possible implementation, the comparison module defaults to a fourth comparison mechanism, and detects the current calculated force value after the comparison module runs out of the fourth comparison mechanism; when the current calculated force value of the comparison module is lower than the calculated force threshold value, the comparison module adopts a fifth comparison mechanism for comparison again; when the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison module adopts a first comparison mechanism or a second comparison mechanism for comparison again.
In the implementation process, in order to save the calculation force of the comparison module, a fourth comparison mechanism is adopted by the comparison module by default, after the comparison module runs out of the fourth comparison mechanism, a preliminary conclusion is obtained, such as the comparison is consistent, a small amount of inconsistencies, a large amount of inconsistencies and the like, the comparison module detects the current calculation force value, and when the current calculation force value of the comparison module is lower than the calculation force threshold value, a fifth comparison mechanism is adopted in order to keep the high-speed comparison of the chip to be tested, and the comparison place is converted into an external computer. When the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison can be performed again by adopting a first comparison mechanism or a second comparison mechanism, and the comparison result precision is higher through twice comparison. Different comparison mechanisms are selected by comparing the current calculated force values of the comparison modules, so that the comparison is more flexible and flexible.
In one possible implementation manner, the comparison module adopts a first comparison mechanism by default, and after the comparison module runs out of the first comparison mechanism, if the accuracy value of the detection input of the comparison module is lower than the accuracy threshold value, the comparison module adopts a third comparison mechanism or a fourth comparison mechanism for comparison again.
In the implementation process, in order to maintain high-precision comparison, the comparison module defaults to a first comparison mechanism. After the comparison module runs the first comparison mechanism, if the comparison module detects that the input precision value is lower than the precision threshold value, the comparison module is converted into a third comparison mechanism or a fourth comparison mechanism; the operation time can be preset, and the verification data is consistent with the output data of the chip to be tested in the preset operation time, so that the chip to be tested has no error for a long time, the quality of the chip is high, and the comparison module is converted into a third comparison mechanism or a fourth comparison mechanism, so that the calculation force is saved. Different comparison mechanisms are selected by setting different precision values, so that the comparison is more flexible.
In one possible implementation, the comparison module defaults to adopt a second comparison mechanism, and after the comparison module runs out of the second comparison mechanism, if the accuracy value of the detection input of the comparison module is lower than the accuracy threshold value, the comparison module adopts a third comparison mechanism or a fourth comparison mechanism for comparison again.
In the implementation process, in order to maintain high-precision comparison, the comparison module defaults to a second comparison mechanism. After the comparison module runs the second comparison mechanism, if the comparison module detects that the input precision value is lower than the precision threshold value, the comparison module is converted into a third comparison mechanism or a fourth comparison mechanism; the operation time can be preset, and the verification data is consistent with the output data of the chip to be tested in the preset operation time, so that the chip to be tested has no error for a long time, the quality of the chip is high, and the comparison module is converted into a third comparison mechanism or a fourth comparison mechanism, so that the calculation force is saved. Different comparison mechanisms are selected by setting different precision values, so that the comparison is more flexible.
In one possible implementation, the comparison module is preset with an error rate threshold, and the comparison module detects that the current error rate is higher than the error rate threshold, and the comparison module adopts a first comparison mechanism or a second comparison mechanism to continue the comparison.
In the implementation process, the comparison module is preset with an error rate threshold value, and can detect the error rate in real time in the comparison process, and the error rate is calculated in the following manner: when the current error rate is higher than the error rate threshold value, the error rate of the chip to be tested is higher, and the comparison module adopts a first comparison mechanism or a second comparison mechanism to carry out high-precision comparison. The proper comparison mechanism is selected by calculating the error rate in real time, so that the method is more flexible to use.
In one possible implementation manner, the external computer obtains the average error rate of the chip to be tested in the past, and when the average error rate is lower than the error rate threshold, the comparison module adopts a third comparison mechanism or a fourth comparison mechanism; when the average error rate is higher than the error rate threshold, the comparison module adopts a first comparison mechanism or a second comparison mechanism to continue the comparison.
In the implementation process, the external computer can acquire the average error rate of the chip to be tested of the model through the internet, or calculate the average error rate through the test result of the chip in the past, and the calculation mode of the average error rate is as follows: the sum of all chip error rates/total chip. When the average error rate is lower than the error rate threshold, the chip error rate is lower, and the comparison module adopts a third comparison mechanism or a fourth comparison mechanism to save calculation force. When the average error rate is higher than the error rate threshold, the chip error rate is higher, and the comparison module adopts a first comparison mechanism or a second comparison mechanism to maintain high-precision comparison. The average error rate of the chip is obtained, so that a comparison mechanism can be selected more flexibly, and the use is more convenient and accurate.
In a second aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of any one of the first aspects when executing the computer program.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. The flexible comparison method is characterized by comprising the steps of comparing based on a detection circuit board, wherein the detection circuit board comprises a data processing module, a comparison module and at least one chip interface to be tested, the data processing module is connected with a storage module, the storage module is used for storing detection data transmitted by the data processing module, the data processing module is connected with an external computer, and verification data is preset in the comparison module and is connected with the chip interface to be tested; the method comprises the following steps:
the comparison module is pre-provided with a calculation threshold value, and selects a comparison place and a comparison mechanism of output data of the chip to be tested according to the current calculation value; and/or the number of the groups of groups,
the comparison module is pre-provided with an accuracy threshold value, and selects a comparison place and a comparison mechanism of output data of the chip to be tested according to the input accuracy value;
the comparison place of the output data of the chip to be tested is the detection circuit board or an external computer;
the comparison mechanism comprises: the first comparison mechanism is used for comparing the verification data with the output data of the chip to be tested and recording all comparison results; the second comparison mechanism is used for comparing the verification data with the output data of the chip to be tested in a low-bit mode, and recording all comparison results when the low-bit or high-bit or formed bit is inconsistent; the third comparison mechanism is used for comparing the verification data with the output data of the chip to be tested, recording all inconsistent comparison results, and sending a comparison consistent signal to the data processing module if the comparison results are completely consistent; a fourth comparison mechanism, wherein the comparison module compares the verification data with the output data of the chip to be tested in a low bit position, and when the low bit position or the high bit position or the bit positions formed by the low bit position or the high bit position are inconsistent, all the comparison inconsistent results are recorded; and the fifth comparison mechanism is used for transmitting the output data of the chip to be tested to an external computer, wherein the external computer is preset with verification data, and the external computer is used for comparing the verification data with the output data of the chip to be tested and recording all comparison results.
2. The flexible comparison method suitable for chip detection according to claim 1, wherein the comparison module detects that the current calculation force value is lower than the calculation force threshold value, and the comparison location of the chip output data to be detected is converted into an external computer by the detection circuit board; and/or the number of the groups of groups,
and the comparison module detects that the currently input precision value is higher than the precision threshold value, and the comparison position of the output data of the chip to be tested is converted into an external computer by the detection circuit board.
3. The flexible comparison method suitable for chip detection according to claim 1, wherein the comparison module defaults to the third comparison mechanism, and the comparison module detects a current calculated force value after the comparison module runs out of the third comparison mechanism;
when the current calculated force value of the comparison module is lower than a calculated force threshold value, the fifth comparison mechanism is adopted by the comparison module;
and when the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison module adopts the first comparison mechanism or the second comparison mechanism for comparison again.
4. The flexible comparison method suitable for chip detection according to claim 1, wherein the comparison module defaults to the fourth comparison mechanism, and the comparison module detects a current calculated force value after the comparison module runs out of the fourth comparison mechanism;
when the current calculated force value of the comparison module is lower than the calculated force threshold value, the comparison module adopts the fifth comparison mechanism for comparison again;
and when the current calculated force value of the comparison module is higher than the calculated force threshold value, the comparison module adopts the first comparison mechanism or the second comparison mechanism for comparison again.
5. The flexible comparison method for chip detection according to claim 1, wherein the comparison module adopts the first comparison mechanism by default, and the comparison module adopts the third comparison mechanism or the fourth comparison mechanism again after the comparison module runs out of the first comparison mechanism if the accuracy value of the comparison module detection input is lower than the accuracy threshold.
6. The flexible comparison method for chip detection according to claim 1, wherein the second comparison mechanism is adopted by the comparison module by default, and the third comparison mechanism or the fourth comparison mechanism is adopted by the comparison module for comparison again if the accuracy value of the comparison module detection input is lower than the accuracy threshold value after the comparison module runs out of the second comparison mechanism.
7. The flexible comparison method for chip detection according to claim 1, wherein the comparison module is pre-provided with an error rate threshold, the comparison module detects that the current error rate is higher than the error rate threshold, and the comparison module continues to compare by adopting the first comparison mechanism or the second comparison mechanism.
8. The flexible comparison method for chip detection according to claim 7, wherein an external computer obtains an average error rate of chips to be tested in the past, and when the average error rate is lower than an error rate threshold, the comparison module adopts the third comparison mechanism or the fourth comparison mechanism; and when the average error rate is higher than an error rate threshold, the comparison module continues to compare by adopting the first comparison mechanism or the second comparison mechanism.
9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of any of claims 1-8 when executing the computer program.
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