CN115866436A

CN115866436A - Communication circuit and related device

Info

Publication number: CN115866436A
Application number: CN202310159153.XA
Authority: CN
Inventors: 宁林琼; 赵楠; 赵礼列
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-02-24
Filing date: 2023-02-24
Publication date: 2023-03-28
Anticipated expiration: 2043-02-24
Also published as: CN115866436B

Abstract

The embodiment of the application provides a communication circuit and a related device. The communication circuit includes: the system comprises a processing module, a WIFI module and an anti-interference circuit arranged on a bus passage between the processing module and the WIFI module; the processing module and the WIFI module transmit a first data signal and a second data signal; the anti-interference circuit is used for filtering interference suffered by the bus when the bus transmits the data signal; the anti-interference circuit comprises a first common-mode inductor and/or a second common-mode inductor; two ends of the first common-mode inductor are respectively connected with a first group of interfaces of the processing module and a second group of interfaces of the WIFI module; and two ends of the second common-mode inductor are respectively connected with the third group of interfaces of the processing module and the fourth group of interfaces of the WIFI module. Therefore, common mode interference in the data signal transmission process can be reduced, distortion, loss and the like of the data signal are reduced, and abnormal phenomena such as network blockage, interruption and the like caused by the interference are improved.

Description

Communication circuit and related device

Technical Field

The present application relates to the field of terminal technologies, and in particular, to a communication circuit and a related apparatus.

Background

With the development of internet technology, internet surfing is more and more popular in life of people, sometimes a plurality of terminal devices need to surf the internet by using one account at the same time, for example, in a home network, a plurality of terminal devices such as a mobile phone, a computer, a network television and the like exist. These terminal devices are connected to a router, which is connected to the internet via an account.

With the continuous upgrade of router products, the transmission rate of the network cable is higher and higher, and the network cable is developed from the previous 10M, 100M and 1000M to the current 2.5G or 10G.

However, when the terminal device is connected to the internet through the router, phenomena such as jamming and network disconnection may occur, and the user experience is poor.

Disclosure of Invention

The embodiment of the application provides a communication circuit and a related device, which are applied to the technical field of terminals. In the access of WIFI module and processing module, access anti-interference circuit, noise wave interference that produces in the filtering signal transmission process through anti-interference circuit, and then the unusual phenomena such as network card pause, interrupt that effectively improve because of the interference causes.

In a first aspect, an embodiment of the present application provides a communication circuit. The communication circuit includes: the device comprises a processing module, an anti-interference circuit and a wireless fidelity (WIFI) module; an anti-interference circuit is arranged on a bus channel between the processing module and the WIFI module; the processing module is used for transmitting a first data signal to the WIFI module and receiving a second data signal from the WIFI module; the anti-interference circuit is used for filtering interference when the bus transmits the first data signal and/or filtering interference when the bus transmits the second data signal; the WIFI module is used for receiving the first data signal from the processing module and transmitting a second data signal to the processing module; the anti-interference circuit comprises a first common-mode inductor and/or a second common-mode inductor; one end of the first common-mode inductor is connected with a first group of interfaces used for transmitting first data signals in the processing module, and the other end of the first common-mode inductor is connected with a second group of interfaces used for transmitting the first data signals in the WIFI module; one end of the second common mode inductor is connected with a third group of interfaces used for transmitting second data signals in the processing module, and the other end of the second common mode inductor is connected with a fourth group of interfaces used for transmitting second data signals in the WIFI module.

The reason for finding that the network of the terminal device is blocked and disconnected in the embodiment of the application is as follows: when a processing module and a WIFI module in a router connected with terminal equipment transmit data through a bus, clutter interference exists, so that data obtained by the WIFI module are distorted, lost and the like, and abnormal phenomena such as network blockage, network disconnection and the like are caused. According to the embodiment of the application, the anti-interference circuit is connected into a passage of the WIFI module and the processing module, clutter interference generated in the signal transmission process is filtered through the anti-interference circuit, and then abnormal phenomena such as network blocking and interruption caused by interference are effectively improved. In addition, the common-mode inductor is connected to reduce common-mode interference in the data signal transmission process, distortion, loss and the like of data signals are reduced, and abnormal phenomena such as network blocking, interruption and the like caused by interference are further improved.

Optionally, the anti-interference circuit further includes a first capacitor, and/or a second capacitor; one end of the first capacitor is connected with the first interface or the second interface, the other end of the first capacitor is grounded, the first interface is any one interface in the first group of interfaces, and the second interface is any one interface in the second group of interfaces; one end of the second capacitor is connected with the third interface or the fourth interface, the other end of the second capacitor is grounded, the third interface is any one of the third group of interfaces, and the fourth interface is any one of the fourth group of interfaces; the value of the first capacitor is any value from 0pF to 68pF, and the value of the second capacitor is any value from 0pF to 68 pF.

Therefore, high-frequency interference suffered in the data signal transmission process can be realized, the distortion, the loss and the like of the data signal are reduced, and the abnormal phenomena of network blockage, interruption and the like caused by the interference are further improved.

Optionally, the value of first electric capacity is 8.2pF, and the value of second electric capacity is 8.2pF.

Therefore, the abnormal conditions of distortion, loss and the like of the data signals can be effectively improved, and the work of the bus can be ensured.

Optionally, the first capacitor is connected with the second interface and is located at one side close to the WIFI module; the second capacitor is connected with the fourth interface and is positioned at one side close to the processing module.

Therefore, the capacitor is placed at the receiving side of the first data signal, interference introduced in transmission can be filtered, the filtering anti-interference effect is further improved, and the quality of the first data signal is improved. The capacitor is arranged on the receiving side of the second data signal, and can filter interference introduced in transmission, so that the filtering anti-interference effect is further improved, and the quality of the second data signal is improved.

Optionally, the immunity circuit further includes: a first transient diode, and/or a second transient diode; one end of the first transient diode is connected with the first interface or the second interface, and the other end of the first transient diode is grounded; one end of the second transient diode is connected with the third interface or the fourth interface, and the other end of the second transient diode is grounded.

Like this, promote anti surge, antistatic effect between processing module and the WIFI module, promote signal transmission's stability and reliability.

Optionally, the processing module is further configured to transmit a clock signal to the WIFI module, where the clock signal is used to trigger the WIFI module to read the first data signal; the immunity circuit further includes: a third capacitor; one end of the third capacitor is connected with a fifth group of interfaces used for transmitting clock signals in the processing module, and the other end of the third capacitor is connected with a sixth group of interfaces used for transmitting clock signals in the WIFI module; the value of the third capacitor is any value from 0pF to 265 pF.

Therefore, the direct-current component of the clock signal can be filtered, so that the voltage value corresponding to the symmetry axis of the clock signal is closer to 0V, the offset of sampling time is reduced, and the condition that the data signal read by the WIFI module is incorrect is reduced.

Optionally, the value of the third capacitor is 100pF.

Therefore, the abnormal conditions such as the distortion of the clock signal can be effectively improved, and the work of the bus can be ensured.

Optionally, the processing module is further configured to transmit a clock signal to the WIFI module, where the clock signal is used to trigger the WIFI module to read the first data signal; the immunity circuit further includes: a fourth capacitor; one end of a fourth capacitor is connected with a fifth interface or a sixth interface, the other end of the fourth capacitor is grounded, the fifth interface is any one of a fifth group of interfaces used for transmitting clock signals in the processing module, and the sixth interface is any one of a sixth group of interfaces used for transmitting clock signals in the WIFI module; the value of the fourth capacitance is any value from 0pF to 68 pF.

Therefore, high-frequency interference suffered in the clock signal transmission process can be realized, the distortion, the loss and the like of the clock signal are reduced, and the abnormal phenomena of network blockage, interruption and the like caused by the interference are further improved.

Optionally, a value of the fourth capacitor is 8.2pF.

Optionally, the fourth capacitor is connected to the sixth interface and is located on one side close to the WIFI module.

Therefore, the capacitor is placed at the receiving side of the clock signal, interference introduced in transmission can be filtered, the filtering anti-interference effect is further improved, and the quality of the clock signal is improved.

Optionally, the bus is a peripheral component interconnect standard PCIE bus path or a serial gigabit media independent SGMII bus.

Optionally, the WIFI module includes: the WIFI module works in the 2.4G frequency band and/or the WIFI module works in the 5G frequency band.

In a second aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a terminal device, and the terminal device may also be referred to as a terminal (terminal), a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), or the like. The terminal device may be a router, a mobile phone (mobile phone), a smart television, a wearable device, a tablet computer (Pad), a computer with wireless transceiving function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in self-driving (self-driving), a wireless terminal in remote surgery (remote medical supply), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a wireless terminal in city (smart city), a wireless terminal in smart home (smart home), and the like.

The electronic device includes: the method comprises the following steps: a power supply module, and the communication circuit of any one of the first aspect; the power module is used for supplying power for the communication circuit.

The second aspect of the present application corresponds to the technical solution of the first aspect of the present application, and the beneficial effects obtained by the feasible implementation manner corresponding to the second aspect are similar and will not be described again.

Drawings

Fig. 1 is a schematic diagram of a terminal device for surfing the internet according to an embodiment of the present application;

FIG. 2 is a test diagram of jump bits in data signals transmitted in a PCIE bus in a possible design;

fig. 3 is a schematic structural diagram of a communication circuit according to an embodiment of the present disclosure;

fig. 4 is a test diagram of jump shift in a data signal transmitted in a PCIE bus after adding a common mode inductor according to the embodiment of the present application;

fig. 5 is a schematic structural diagram of a communication circuit according to an embodiment of the present disclosure;

fig. 6 is a test chart of all bits in a data signal transmitted in a bus without adding the capacitor C5 and the capacitor C6 according to the embodiment of the present application;

fig. 7 is a test chart of all bits in the data signal transmitted in the bus after the capacitor C5 and the capacitor C6 are added according to the embodiment of the present application;

fig. 8 is a schematic structural diagram of a communication circuit according to an embodiment of the present disclosure;

fig. 9 is a test chart of jump bits in a data signal transmitted in a bus when the capacitor C9 and the capacitor C10 are not added according to an embodiment of the present disclosure;

fig. 10 is a test chart of jump bits in data signals transmitted in a bus after a capacitor C9 and a capacitor C10 are added according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a communication circuit according to an embodiment of the present application;

fig. 12 is a test chart of jump bits in data signals transmitted in a bus when the capacitor C11 and the capacitor C12 are not added according to the embodiment of the present application;

fig. 13 is a test chart of jump bits in data signals transmitted in a bus after adding a capacitor C11 and a capacitor C12 according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a communication circuit according to an embodiment of the present application;

fig. 15 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to facilitate clear description of the technical solutions of the embodiments of the present application, some terms and techniques referred to in the embodiments of the present application are briefly described below:

1. peripheral component interconnect (pci) bus: is a high-speed serial computer expansion bus standard.

It should be noted that the data path (lane) in the PCIE bus is composed of two sets of differential signals, and 4 signal lines in total. The transmitting part of the transmitting end and the receiving part of the receiving end are connected by using a group of differential signals, and the link is also called as a transmitting link of the transmitting end and a receiving link of the receiving end; the receiving part of the transmitting end and the transmitting part of the receiving end are connected by another set of differential signals, and the link is also called a receiving link of the transmitting end and a transmitting link of the receiving end.

2. Serial gigabit media independent interface (SGMII bus): is a high-speed serial computer expansion bus standard.

3. Eye pattern: the eye diagram is a graph displayed by accumulating a series of digital signals on an oscilloscope. The method contains rich information, can observe the influence of intersymbol interference and noise from an eye pattern, and embodies the integral characteristics of digital signals, thereby estimating the quality degree of a system.

The method for observing the eye pattern comprises the following steps: an oscilloscope is used to connect across the output end of the receiving filter, then the scanning period of the oscilloscope is adjusted to synchronize the horizontal scanning period of the oscilloscope with the period of the received code element, and the figure seen on the screen of the oscilloscope is like the eyes of a human, so the oscilloscope is called an eye pattern.

It should be noted that the size of the "eye" opening of the eye pattern reflects the strength of the intersymbol interference. The larger the "eye" is, and the more positive the eye pattern is, the smaller the intersymbol interference is; and conversely, the larger the intersymbol interference.

When noise is present, it will be superimposed on the signal and the traces of the observed eye pattern will be blurred. If there is intersymbol interference at the same time, the "eye" will open less. Compared with the eye pattern without intersymbol interference, the original clear and positive thin traces become fuzzy strip lines and are not very positive. The bigger the noise is, the wider and fuzzy the stitch is; the greater the intersymbol crosstalk, the less positive the eye pattern.

4. Phase-locked loops (PLL): the frequency and phase synchronization technology is realized by utilizing a feedback control principle, and has the function of keeping the clock output by a circuit synchronous with an external reference clock. When the frequency or phase of the reference clock changes, the phase-locked loop detects the change and adjusts the output frequency through its internal feedback system until the two resynchronize, which is also referred to as "phase-lock".

5. Other terms

In the embodiments of the present application, the terms "first", "second", and the like are used to distinguish the same or similar items having substantially the same function and effect. For example, the first chip and the second chip are only used for distinguishing different chips, and the sequence order thereof is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the embodiments of the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a alone, A and B together, and B alone, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c can be single or multiple.

In the embodiment of the present invention, "at 8230 \ 8230at time", may be an instant when a certain condition occurs, or may be a period of time after the certain condition occurs, and this is not particularly limited in the embodiment of the present invention. In addition, the interface of the terminal device provided in the embodiment of the present application is only an example, and the interface may further include more or less content.

6. Terminal device

The terminal device of the embodiment of the present application may also be any form of electronic device, for example, the electronic device may include a handheld device having a communication function, an in-vehicle device, and the like. For example, some electronic devices are: a mobile phone (mobile phone), a tablet computer, a palm computer, a notebook computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned driving (self driving), a wireless terminal in remote surgery (remote medical supply), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation security (smart), a wireless terminal in city (smart city), a wireless terminal in smart home (smart home), a cellular phone, a cordless phone, a session initiation protocol (session initiation protocol), SIP) phone, wireless Local Loop (WLL) station, personal Digital Assistant (PDA), handheld device with wireless communication function, computing device or other processing device connected to wireless modem, vehicle-mounted device, wearable device, terminal device in 5G network or terminal device in Public Land Mobile Network (PLMN) for future evolution, etc., which are not limited by the embodiments of the present application.

By way of example and not limitation, in the embodiments of the present application, the electronic device may also be a wearable device. Wearable equipment can also be called wearable intelligent equipment, is the general term of applying wearable technique to carry out intelligent design, develop the equipment that can dress to daily wearing, like glasses, gloves, wrist-watch, dress and shoes etc.. A wearable device is a portable device that is worn directly on the body or integrated into the clothing or accessories of the user. The wearable device is not only a hardware device, but also realizes powerful functions through software support, data interaction and cloud interaction. The generalized wearable smart device includes full functionality, large size, and can implement full or partial functionality without relying on a smart phone, such as: smart watches or smart glasses and the like, and only focus on a certain type of application functions, and need to be used in cooperation with other devices such as smart phones, such as various smart bracelets for physical sign monitoring, smart jewelry and the like.

In addition, in the embodiment of the present application, the electronic device may also be a terminal device in an internet of things (IoT) system, where IoT is an important component of future information technology development, and the main technical feature of the electronic device is to connect an article with a network through a communication technology, so as to implement an intelligent network with human-computer interconnection and object-object interconnection.

The electronic device in the embodiment of the present application may also be referred to as: a terminal device, a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user equipment, etc.

In an embodiment of the present application, the electronic device or each network device includes a hardware layer, an operating system layer running on top of the hardware layer, and an application layer running on top of the operating system layer. The hardware layer includes hardware such as a Central Processing Unit (CPU), a Memory Management Unit (MMU), and a memory (also referred to as a main memory). The operating system may be any one or more computer operating systems that implement business processing through processes (processes), such as a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or a windows operating system. The application layer comprises applications such as a browser, an address list, word processing software, instant messaging software and the like.

With the continuous development of information technology in modern society, wireless networks are increasingly used in modern society, and routers are generally used for transmitting wireless data to the living environment of people. A router, which may also be referred to as a gateway device, is used to connect a plurality of logically separate networks, a so-called logical network representing a single network or a sub-network. This may be accomplished by the routing function of the wireless router when data is transferred from one subnet to another.

Fig. 1 is a schematic diagram of a terminal device for surfing the internet according to an embodiment of the present disclosure. As shown in fig. 1, when the terminal device opens a webpage and plays a video, the terminal device can be connected to WIFI provided by the router, and then connected to the internet through the router.

In a possible scenario, the following may occur: the terminal device is connected to WIFI provided by the router, but not to the network. Or, when the terminal device plays the video through the WIFI provided by the router, the video may be played normally sometimes, and sometimes cannot be played, that is, the network is unstable.

In a general understanding, if the terminal device cannot normally surf the internet through the WIFI provided by the router, the account logged in by the router may be owed or due. Or the router fails to be connected with the Internet. Or the software system of the terminal equipment fails and the internet cannot be accessed. Therefore, when the terminal device cannot surf the internet normally through the WIFI provided by the router, the adopted means can be used for reconnecting the terminal device with the WIFI provided by the router, replacing the router or the terminal device, or restarting the router.

However, the above-mentioned methods of replacing hardware or reconnecting the terminal device and restarting the router are sometimes not effective. The hardware or software of the terminal device and the hardware or software of the router which cannot normally surf the internet are detected, and it can be found that the hardware of the terminal device, the software system of the terminal device, the hardware of the router and the software system of the terminal device are normal and have no fault.

Based on this, the reason that the terminal device without hardware or software failure can not surf the internet normally is further analyzed in the embodiment of the application, and it is found that the reason that the terminal device can not surf the internet normally is: when a System On Chip (SOC) of a router and a WIFI module of the router perform signal transmission through a bus, clutter interference exists, so that abnormal situations such as network disconnection and jamming occur when a terminal device surfs the internet through the WIFI provided by the router.

For example, when the terminal device surfs the internet through WIFI provided by the router, the data can be obtained from the SOC through the WIFI module of the router. However, data signals transmitted between the WIFI module of the router and the SOC are interfered, and then data signal distortion causes partial or all data loss, so that abnormal phenomena such as jamming and network disconnection occur in the terminal device.

Specifically, taking the case that the WIFI module and the SOC in the router are connected by a PCIE bus, the quality of the data signal in the PCIE bus is tested to be poor, and there is a clutter.

For example, fig. 2 shows a test pattern (eye diagram) of transition bits in data signals transmitted in a PCIE bus in a possible design. Take 100, 101, 011, 010 of the data signals superimposed together as an example.

The test chart shown in fig. 2 includes: curves formed by superimposing 100, 101, 011 and 010 together in the data signal, and a plurality of black areas. When the data signal passes through the black area, the data signal does not satisfy the communication specification.

As shown in fig. 2, the black region includes: top area 201, middle area 202, bottom area 203. The top region 201 defines the maximum amplitude requirement for the data signal, the middle region 202 defines the eye opening requirement for the data signal, and the bottom region 203 defines the minimum amplitude requirement for the data signal.

As can be seen in fig. 2, part of the data signal does not meet the communication specification in a possible design. Illustratively, the partial data signal of gray box 204 falls in the top region 201 and the partial data signal of gray box 205 falls in the bottom region 203.

It should be noted that, with the continuous upgrade of router products, the transmission rate of the network cable is higher and higher, and the network cable is developed from the former 10M, 100M, 1000M to the present 2.5G or 10G. When a System On Chip (SOC) of the router and a WIFI module of the router transmit signals through a bus, clutter interference is more serious. In addition, as application scenes of routing products are diversified and complicated, the anti-interference performance requirement of the router products is improved.

In view of this, in the embodiment of the present application, the anti-interference circuit is connected to the WIFI module and the SOC path in the router, and the anti-interference circuit filters noise interference generated in the signal transmission process, so as to effectively improve abnormal phenomena such as network congestion and interruption caused by interference.

A PCIE bus is taken as an example, and a communication circuit provided in the embodiment of the present application is described below with reference to the drawings.

Fig. 3 is a schematic structural diagram of a communication circuit according to an embodiment of the present disclosure. Taking an example where a processing module in the communication circuit is an SOC, as shown in fig. 3, the communication circuit includes: SOC 301, WIFI module 302, and first immunity circuit 303. The SOC 301 and the WIFI module 302 are connected by a bus. A first anti-interference circuit 303 is arranged on a bus path between the SOC 301 and the WIFI module.

SOC 301 is configured to transmit a first data signal to WIFI module 302. SOC 301 is also configured to receive a second data signal from WIFI module 302.

It is understood that, in the embodiment of the present application, the SOC is used as a processing module, the SOC may be replaced with other processing modules (for example, a Microprocessor (MCU), a processor, and the like) in the communication circuit, and the SOC may also be replaced with corresponding components including the processing module, for example, a controller, and the like. The embodiment of the present application does not limit this.

Correspondingly, the WIFI module 302 is configured to receive a first data signal from the SOC 301, and the WIFI module 302 is further configured to transmit a second data signal to the SOC 301.

In the embodiment of the present application, the WIFI module may be a WIFI module (2.4G WIFI module) working at a 2.4G frequency band, or may also be a WIFI module (5G WIFI module) working at a 5G frequency band, or a WIFI module working at another frequency band, which is not limited in the embodiment of the present application.

The first immunity circuit 303 is configured to filter out common mode interference that is suffered when a bus between the SOC 301 and the WIFI module 302 transmits a data signal. Specifically, the first immunity circuit 303 is configured to filter a common mode interference received when the bus transmits the first data signal, and/or filter a common mode interference received when the bus transmits the second data signal.

Therefore, clutter interference generated in the data signal transmission process is filtered through the first anti-interference circuit, and abnormal phenomena such as network blockage, interruption and the like caused by interference are preferably improved.

Specifically, the SOC 301 includes a data transfer module, a reference clock module, and a reset module. The data transmission module in the SOC 301 is configured to transmit a first data signal to the WIFI module 302 and to receive a second data signal from the WIFI module 302. Correspondingly, the WIFI module 302 includes a data transmission module, a reference clock module and a reset module. The data transmission module in the WIFI module 302 is configured to receive the first data signal from the SOC 301 and transmit the second data signal to the SOC 301.

It should be noted that, a differential signal is adopted in the PCIE bus to transmit the first data signal and the second data signal, the data transmission module of the SOC 301 in fig. 3 includes two groups of interfaces, and four corresponding ports are respectively: a first port 301a, a second port 301b, a third port 301c, and a fourth port 301d.

Wherein, one set of interfaces is used for transmitting a first data signal, that is, the first port 301a is used for transmitting a D + signal related to the first data signal, and the second port 301b is used for transmitting a D-signal related to the first data signal; the other set of interfaces is for receiving a second data signal, i.e., the third port 301c is for receiving a D + signal associated with the second data signal and the fourth port 301D is for receiving a D-signal associated with the second data signal.

Correspondingly, the data transmission module of the WIFI module 302 in fig. 3 includes two sets of interfaces, and there are four corresponding ports: a first port 302a, a second port 302b, a third port 302c, and a fourth port 302d.

Wherein, one set of interfaces is used for receiving a first data signal, i.e. the first port 302a is used for receiving a D + signal related to the first data signal, and the second port 302b is used for transmitting a D-signal related to the first data signal; the other set of interfaces is used to transmit the second data signal, i.e., the third port 302c is used to transmit the D + signal associated with the second data signal and the fourth port 302D is used to transmit the D-signal associated with the second data signal.

It should be noted that, in the PCIE physical layer link, the electrical specification requires that a capacitor is connected in series to the TX link of the PCIE data transmission link for AC coupling. Specifically, a capacitor C1 is arranged between the first port 301a of the SOC 301 and the first port 302a of the WIFI module 302; a capacitor C2 is arranged between the second port 301b of the SOC 301 and the second port 302b of the WIFI module 302; a capacitor C3 is arranged between the third port 301C of the SOC 301 and the third port 302C of the WIFI module 302; a capacitor C4 is arranged between the fourth port 301d of the SOC 301 and the fourth port 302d of the WIFI module 302.

The value of the capacitor C1, the value of the capacitor C2, the value of the capacitor C3 and the value of the capacitor C4 can be any values from 75nF to 265 nF. Illustratively, the value of the capacitor C1, the value of the capacitor C2, the value of the capacitor C3, and the value of the capacitor C4 may be 100nF.

The first immunity circuit 303 is configured to filter a common mode interference suffered by the bus when the bus transmits the first data signal, and/or filter a common mode interference suffered by the bus when the bus transmits the second data signal.

Therefore, common-mode interference of data signals can be reduced, distortion of the data signals, partial data loss and the like caused by transmission are reduced, and abnormal phenomena such as network blockage, interruption and the like caused by interference are effectively improved.

In a first possible implementation manner, the first immunity circuit 303 is configured to filter a common mode interference suffered by the bus when the bus transmits the first data signal.

Illustratively, as shown in fig. 3, the first immunity circuit 303 includes a first common mode inductor L1. One end of the first common mode inductor L1 is connected to an interface of the SOC 301 for transmitting the first data signal, and the other end of the first common mode inductor L1 is connected to an interface of the WIFI module 302 for receiving the first data signal.

Specifically, one end of the first common mode inductor L1 includes a first pin 303a and a second pin 303b. The first pin 303a is connected to a first port 301a of the SOC 301, and the second pin 303b is connected to a second port 301b of the SOC 301.

The other end of the first common mode inductor L1 includes a third pin 303c and a fourth pin 303d. The third pin 303c is connected to the first port 302a of the WIFI module 302, and the fourth pin 303d is connected to the second port 302b of the WIFI module 302.

Therefore, common-mode interference of the first data signal can be reduced, distortion, partial data loss and the like of the first data signal caused by transmission are reduced, and abnormal phenomena such as network blockage, interruption and the like caused by interference are improved.

It can be understood that, when the interference signal is a common mode signal, the magnetic fields generated by the interference signal transmitted on the signal line for transmitting the first data signal are the same in magnitude and opposite in direction, and the magnetic field existing in the coil in the common mode inductor is increased to generate a current. And the inductance can prevent the change of current and the change of magnetic flux in the coil, thereby further counteracting a magnetic field generated by an interference signal and inhibiting a common mode signal. Or it can be understood that the common mode inductor can form a high impedance to the common mode signal and has a small obstruction to the differential mode signal (e.g., a D + signal associated with the first data signal, a D-signal associated with the first data signal), thereby suppressing common mode noise and reducing common mode interference.

For example, fig. 4 is a test diagram of jump shift bits in data signals transmitted in a PCIE bus after adding a common mode inductor according to the embodiment of the present application. Take 100, 101, 011, 010 of the data signals superimposed together as an example.

The test chart shown in fig. 4 includes: a curve formed by superposing 100, 101, 011 and 010 of the data signals together, and a plurality of black regions. When the data signal passes through the black area, the data signal does not satisfy the communication specification.

As shown in fig. 4, the black region includes: top zone 401, middle zone 402, bottom zone 403. The top region 401 defines the maximum amplitude requirement for the data signal, the middle region 402 defines the eye opening requirement for the data signal, and the bottom region 403 defines the minimum amplitude requirement for the data signal.

Compared with the test chart shown in fig. 2, in the test chart shown in fig. 4, the curve formed by the jump bit does not pass through the top area and the bottom area, and abnormal situations such as distortion and loss of the data signal can be reduced.

Therefore, after the common-mode inductor is added, the conditions of distortion, loss and the like of data signals can be reduced, and the abnormal phenomena of network blockage, interruption and the like caused by common-mode interference are further improved.

In a second possible implementation manner, the first immunity circuit 303 is configured to filter out common mode interference suffered by the bus when the bus transmits the second data signal.

Illustratively, as shown in fig. 3, the first immunity circuit 303 includes a second common mode inductor L2. One end of the second common-mode inductor L2 is connected to an interface of the SOC 301, where the interface is used for receiving a second data signal, and the other end of the second common-mode inductor L2 is connected to an interface of the WIFI module 302, where the interface is used for sending the second data signal.

Specifically, one end of the second common mode inductor L2 includes a fifth pin 303e and a sixth pin 303f. The fifth pin 303e is connected to the third port 301c of the SOC 301, and the sixth pin 303f is connected to the fourth port 301d of the SOC 301.

The other end of the first common mode inductor L1 includes a seventh pin 303g and an eighth pin 303h. The seventh pin 303g is connected to the third port 302c of the WIFI module 302, and the eighth pin 303h is connected to the fourth port 302d of the WIFI module 302.

Therefore, common-mode interference of the second data signal can be reduced, distortion, partial data loss and the like of the second data signal caused by transmission are reduced, and abnormal phenomena such as network blockage, interruption and the like caused by the interference are preferably improved.

It can be understood that the first anti-interference circuit of the embodiment of the present application may be used in the router maintenance at a later stage, and the first anti-interference circuit is added to the motherboard of the router, or the first anti-interference circuit may also be used in the manufacturing process of the router, and when the router is manufactured, the first anti-interference circuit is integrated in the motherboard of the router, so as to improve the network instability of the router. The first anti-interference circuit may be any other type of anti-interference circuit, and the embodiments of the present application are not particularly limited.

Fig. 5 is a schematic structural diagram of a communication circuit according to an embodiment of the present disclosure.

As shown in fig. 5, the communication circuit includes: a System On Chip (SOC) 301, a WIFI module 302, and a second immunity circuit 304. The SOC 301 and the WIFI module 302 are connected by a bus. A second anti-interference circuit 304 is arranged on a bus path between the SOC 301 and the WIFI module.

The functions and structures of the SOC 301 and the WIFI module 302 may refer to the above related descriptions, and are not described herein again.

In this embodiment, the second interference rejection circuit 304 is configured to perform high-frequency filtering on the first data signal transmitted by the bus, and/or perform high-frequency filtering on the second data signal transmitted by the bus.

In a first possible implementation manner, the second interference rejection circuit 304 is configured to perform high-frequency filtering on the first data signal transmitted by the bus. Therefore, high-frequency interference on the first data signal in the transmission process can be realized, distortion, loss and the like of the first data signal are reduced, and abnormal phenomena such as network blockage, interruption and the like caused by the interference are further improved.

Illustratively, as shown in fig. 5, the second anti-interference circuit includes a capacitor C5 and a capacitor C6. One end of the capacitor C5 is connected to the first port 301a of the SOC 301 or connected to the first port 302a of the WIFI module 302. The other terminal of the capacitor C5 is grounded. One end of the capacitor C6 is connected to the second port 301b of the SOC 301 or connected to the second port 302b of the WIFI module 302. The other terminal of the capacitor C6 is grounded.

Wherein, the value of electric capacity C5 can be 0pF to 68 pF's arbitrary value, and the value of electric capacity C6 can be 0pF to 68 pF's arbitrary value.

Optionally, the capacitor C5 is located at a side close to the WIFI module 302, and the capacitor C6 is located at a side close to the WIFI module 302.

Therefore, the capacitor is placed at the receiving side of the first data signal, interference introduced in transmission can be filtered, the filtering anti-interference effect is further improved, and the quality of the first data signal is improved.

It can be understood that the larger the value of the capacitor is, the better the filtering effect for high frequencies is. However, the bus is affected by the overlarge capacitance, so that the value of the capacitance C5 is 8.2pF, and the value of the capacitance C6 is 8.2pF, which not only can effectively improve the abnormal conditions of distortion, loss and the like of the data signal, but also can ensure the work of the bus.

For example, signal transmission before and after adding the capacitors C5 and C6 will be described with reference to fig. 6 and 7. Fig. 6 shows a test pattern (eye pattern) of all bits (all bits) in the data signal transmitted in the bus when the capacitor C5 and the capacitor C6 are not added, and fig. 7 shows a test pattern (eye pattern) of all bits in the data signal transmitted in the bus after the capacitor C5 and the capacitor C6 are added.

The test chart shown in fig. 6 includes: a curve formed by superposing all waveforms in the data signal together, and a plurality of black regions. The black region includes: top zone 601, middle zone 602, bottom zone 603. The functions of the top area 601, the middle area 602, and the bottom area 603 can refer to the corresponding descriptions above, and are not described herein.

As can be seen from fig. 6, when the capacitor C5 and the capacitor C6 are not added, part of the data signal in the bus passes through the black area, and part of the data signal transmitted by the bus does not meet the communication specification. Illustratively, a portion of the data signal of gray box 604 falls within middle region 602.

The test chart shown in fig. 7 includes: a curve formed by superposing all waveforms in the data signal together, and a plurality of black regions. The black region includes: top region 701, middle region 702, bottom region 703. The functions of the top region 701, the middle region 702 and the bottom region 703 can refer to the corresponding descriptions above, and are not described herein again.

In comparison with the test chart shown in fig. 6, in the test chart shown in fig. 7, the curve formed by all bits does not pass through the middle area, and the data signal satisfies the communication specification. Therefore, after the capacitor C5 and the capacitor C6 are added, the conditions of distortion, loss and the like of data signals can be reduced, and the abnormal phenomena of network blockage, interruption and the like can be further improved.

In a second possible implementation manner, the second interference rejection circuit 304 is configured to perform high-frequency filtering on the second data signal transmitted by the bus. Therefore, high-frequency interference on the second data signal in the transmission process can be realized, distortion, loss and the like of the second data signal are reduced, and abnormal phenomena such as network blockage, interruption and the like caused by the interference are further improved.

Illustratively, as shown in fig. 5, the second anti-interference circuit includes a capacitor C7 and a capacitor C8. One end of the capacitor C7 is connected to the third port 301C of the SOC 301 or connected to the third port 302C of the WIFI module 302. The other terminal of the capacitor C7 is grounded. One end of the capacitor C8 is connected to the fourth port 301d of the SOC 301 or connected to the fourth port 302d of the WIFI module 302. The other terminal of the capacitor C8 is grounded.

Wherein, the value of electric capacity C7 can be 0pF to 68 pF's arbitrary value, and the value of electric capacity C8 can be 0pF to 68 pF's arbitrary value.

Alternatively, the capacitor C7 is located on the side close to the SOC 301, and the capacitor C8 is located on the side close to the SOC 301.

Therefore, the capacitor is placed at the receiving side of the second data signal, interference introduced in transmission can be filtered, the filtering anti-interference effect is further improved, and the quality of the second data signal is improved.

It can be understood that the larger the value of the capacitance, the better the filtering effect for high frequencies. However, the bus is affected by the overlarge capacitance, so that the value of the capacitance C7 is 8.2pF, and the value of the capacitance C8 is 8.2pF, which not only can effectively improve the abnormal conditions of distortion, loss and the like of the data signal, but also can ensure the work of the bus.

On the basis of the above embodiment, the second anti-interference circuit 304 is also used for performing surge protection and electrostatic protection.

In a first possible implementation manner, the second anti-interference circuit 304 is used for performing surge protection and electrostatic protection on a signal line of the first data signal transmitted by the bus.

Illustratively, as shown in fig. 5, the second interference rejection circuit 304 includes a Transient Voltage Supply (TVS) D1 and a TVS D2. One end of the TVS tube D1 is connected to the first port 301a of the SOC 301, or connected to the first port 302a of the WIFI module 302. The other end of the TVS tube D1 is grounded. One end of the TVS tube D2 is connected to the second port 301b of the SOC 301 or connected to the second port 302b of the WIFI module 302. The other end of the TVS tube D2 is grounded.

In a second possible implementation manner, the second anti-interference circuit 304 is used for performing surge protection and electrostatic protection on a signal line of the second data signal transmitted by the bus.

Illustratively, as shown in fig. 5, the second immunity circuit 304 includes a TVS tube D3 and a TVS tube D4. One end of the TVS tube D3 is connected to the third port 301c of the SOC 301 or connected to the third port 302c of the WIFI module 302. The other end of the TVS tube D3 is grounded. One end of the TVS tube D4 is connected to the fourth port 301D of the SOC 301 or connected to the fourth port 302D of the WIFI module 302. The other end of the TVS tube D4 is grounded.

Like this, promote anti surge, antistatic effect between SOC and the WIFI module, promote signal transmission's stability and reliability. It can be understood that the second anti-interference circuit in the embodiments of the present application may be added to a motherboard of a router in the later maintenance of the router, or the second anti-interference circuit may also be used in the production and manufacturing process of the router, and when the router is manufactured, the second anti-interference circuit is integrated in the motherboard of the router, so as to improve the network instability of the router. The second anti-interference circuit may be any other type of anti-interference circuit, and embodiments of the present application are not particularly limited.

As can be appreciated, the WIFI module reads the data signal transmitted on the bus based on the clock signal. If the clock signal is read incorrectly, the reading of the data signal may be affected, and abnormal phenomena such as network congestion and network disconnection may occur.

The clock signal received by the WIFI module may be provided by the SOC, or may be provided by another external circuit, which is not limited herein.

The above-mentioned transmission interference of the data signal is explained in fig. 3 to 7, and the transmission interference of the clock signal is explained in the following with reference to fig. 8 to 13.

It is understood that the reference clock module in SOC 301 is used to transmit a clock signal to WIFI module 302. Correspondingly, the WIFI module 302 includes a data transmission module, a reference clock module and a reset module. The reference clock module in the WIFI module 302 is configured to receive a clock signal from the SOC 301.

It can be understood that, after receiving the clock signal, the WIFI module 302 may integrate the clock signal at the PLL module, and use the clock signal as a reference clock for the serial-to-parallel conversion module, the codec module, the scrambling/descrambling module, and the like, so as to read the first data signal received by the WIFI module 302 based on the clock signal.

For example, fig. 8 is a schematic structural diagram of a communication circuit provided in an embodiment of the present application. As shown in fig. 8, the communication circuit includes: a System On Chip (SOC) 301, a WIFI module 302, and a third immunity circuit 305. The SOC 301 and the WIFI module 302 are connected by a bus. A third anti-interference circuit 305 is arranged on a bus path between the SOC 301 and the WIFI module.

As shown in fig. 8, a reference clock module of the SOC 301 has a group of interfaces, and the total two ports are: a fifth port 301e and a sixth port 301f. The fifth port 301e is for transmitting a clock signal related D + signal and the sixth port 301f is for transmitting a clock signal related D-signal.

Correspondingly, the reference clock module of the WIFI module 302 corresponds to a group of interfaces, and the total two ports are respectively: a fifth port 302e and a sixth port 302f. The fifth port 302e is for receiving a clock signal related D + signal and the sixth port 302f is for receiving a clock signal related D-signal.

The third immunity circuit 305 is configured to filter low-frequency interference suffered by a bus between the SOC 301 and the WIFI module 302 when the bus transmits a clock signal. Low-frequency interference can also be understood as interference of a direct current component.

It should be noted that, when the clock signal is transmitted, crosstalk of a direct current component may occur, so that a voltage value corresponding to a symmetry axis of the clock signal is far from 0V, and sampling time is shifted, so that time for the WIFI module to read the data signal based on the clock signal is shifted, and the read data signal is erroneous.

In the embodiment of the present application, the third immunity circuit 305 includes a capacitor C9 and a capacitor C10. One end of the capacitor C9 is connected to the fifth port 301e of the SOC 301, and the other end of the capacitor C9 is connected to the fifth port 302e of the WIFI module 302. One end of the capacitor C10 is connected to the sixth port 301f of the SOC 301, and the other end of the capacitor C10 is connected to the sixth port 302f of the WIFI module 302.

The value of the capacitor C9 may be any value from 0nF to 265nF, and the value of the capacitor C10 may be any value from 0nF to 265 nF.

Therefore, the direct-current component of the clock signal can be filtered by the capacitor C9 and the capacitor C10, so that the voltage value corresponding to the symmetry axis of the clock signal is closer to 0V, the offset of sampling time is reduced, and the condition that the data signal read by the WIFI module is incorrect is reduced.

It can be understood that the larger the value of the capacitor is, the better the filtering effect on low frequency is, so that the voltage value corresponding to the symmetry axis of the clock signal is closer to 0V. However, the attenuation of high frequency components in the clock signal is increased due to the excessively large capacitance, which leads to a decrease in the height of the clock signal in the eye diagram, and a gradual rise and an increase in jitter of the analyzed clock signal. Therefore, the value of the capacitor C9 is 100nF, and the value of the capacitor C10 is 100nF, which not only can effectively improve the abnormal conditions such as the distortion of the clock signal, but also can ensure the operation of the bus.

Next, signal transmission before and after addition of the capacitor C9 and the capacitor C10 will be described with reference to fig. 9 and 10. Fig. 9 shows a test pattern (eye pattern) of a shift bit in a clock signal transmitted in a bus when the capacitor C9 and the capacitor C10 are not added, and fig. 10 shows a test pattern (eye pattern) of a shift bit in a clock signal transmitted in a bus after the capacitor C9 and the capacitor C10 are added.

Illustratively, 100, 101, 011, 010 are added together in the clock signal. The test chart shown in fig. 9 includes: a curve formed by superposing 100, 101, 011 and 010 of the clock signals together, and a plurality of black regions. The black region includes: top region 901, middle region 902, bottom region 903. The functions of the top region 901, the middle region 902 and the bottom region 903 can refer to the corresponding descriptions above, and are not described herein again.

As can be seen from fig. 9, the voltage values corresponding to the symmetry axes of the curves formed by adding 100, 101, 011 and 010 together in the clock signal are not 0V.

In addition, when the capacitor C9 and the capacitor C10 are not added, a part of the clock signal in the bus may pass through the black area due to the offset of the clock signal, and a part of the clock signal transmitted by the bus does not meet the communication specification. Illustratively, a portion of the clock signal of the gray box 904 falls in the middle region 902.

The test chart shown in fig. 10 includes: curves formed by superimposing the clock signals 101, 010 together, and a plurality of black areas. The black region includes: top region 1001, middle region 1002, bottom region 1003. The top region 1001, the middle region 1002, and the bottom region 1003, and the functions of the respective regions can refer to the corresponding descriptions above, which are not described herein again.

As can be seen from fig. 10, after the capacitor C9 and the capacitor C10 are added, the voltage value corresponding to the symmetry axis of the curve formed by the clock signals 101 and 010 being superimposed together is close to or equal to 0V. In addition, the clock signal in the bus does not pass through the black area, and the clock signal meets the communication specification.

Thus, the skew, distortion and loss of the clock signal can be reduced.

It can be understood that the third anti-interference circuit of the embodiment of the present application may be used in the router maintenance at a later stage, and the third anti-interference circuit is added to the motherboard of the router, or the third anti-interference circuit may also be used in the manufacturing process of the router, and when the router is manufactured, the third anti-interference circuit is integrated in the motherboard of the router, so as to improve the network instability of the router. The third anti-interference circuit may be any other type of anti-interference circuit, and the embodiments of the present application are not particularly limited.

For example, fig. 11 is a schematic structural diagram of a communication circuit provided in an embodiment of the present application. As shown in fig. 11, the communication circuit includes: a System On Chip (SOC) 301, a WIFI module 302, and a fourth immunity circuit 306. The SOC 301 and the WIFI module 302 are connected by a bus. A fourth anti-interference circuit 306 is arranged on a bus path between the SOC 301 and the WIFI module.

The fourth immunity circuit 306 is used for high-frequency filtering of the clock signal transmitted by the bus.

Illustratively, as shown in fig. 11, the third immunity circuit 305 includes a capacitor C11 and a capacitor C12. One end of the capacitor C11 is connected to the fifth port 301e of the SOC 301 or connected to the fifth port 302e of the WIFI module 302. The other terminal of the capacitor C11 is grounded. One end of the capacitor C12 is connected to the sixth port 301f of the SOC 301 or connected to the sixth port 302f of the WIFI module 302. The other terminal of the capacitor C12 is grounded.

The value of the capacitor C11 may be any value from 0nF to 68pF, and the value of the capacitor C12 may be any value from 0nF to 68 pF.

Therefore, the high-frequency interference on the clock signal in the transmission process can be reduced, the distortion, the loss and the like of the clock signal are reduced, and the abnormal phenomena of network blockage, interruption and the like caused by the interference are further improved.

Alternatively, the capacitor C11 is located on the side close to the SOC 301, and the capacitor C12 is located on the side close to the SOC 301.

It can be understood that the larger the value of the capacitor is, the better the filtering effect for high frequencies is. However, the bus is affected by the overlarge capacitance, so that the value of the capacitance C11 is 8.2pF, and the value of the capacitance C12 is 8.2pF, which not only can effectively improve the abnormal conditions of clock signal distortion, loss and the like, but also can ensure the work of the bus.

For example, signal transmission before and after adding the capacitor C11 and the capacitor C12 will be described with reference to fig. 12 and 13. Fig. 12 shows a test pattern (eye pattern) of all bits (all bits) in the clock signal transmitted in the bus when the capacitor C11 and the capacitor C12 are not added, and fig. 13 shows a test pattern (eye pattern) of all bits in the clock signal transmitted in the bus after the capacitor C11 and the capacitor C12 are added.

Take the example of superimposing the clock signals 101, 010 together. The test chart shown in fig. 12 includes: curves formed by superimposing the clock signals 101, 010 together, and a plurality of black areas. The black region includes: top region 1201, middle region 1202, bottom region 1203. The functions of the top region 1201, the middle region 1202 and the bottom region 1203 can refer to the above corresponding descriptions, and are not described herein again.

As can be seen from fig. 12, when the capacitor C11 and the capacitor C12 are not added, part of the clock signal in the bus may pass through the black area, and part of the clock signal transmitted by the bus does not meet the communication specification. Illustratively, a portion of the clock signal of gray box 1204 falls in middle region 1202.

The test chart shown in fig. 13 includes: curves formed by superimposing the clock signals 101, 010 together, and a plurality of black areas. The black region includes: top region 1301, middle region 1302, bottom region 1303. The functions of the top region 1301, the middle region 1302, and the bottom region 1303 may refer to the corresponding descriptions, which are not described herein again.

As can be seen from fig. 13, after the capacitor C11 and the capacitor C12 are added, the clock signal in the bus does not pass through the black area, and both the clock signals meet the communication specification.

Thus, distortion and loss of clock signals can be reduced.

It can be understood that the fourth immunity circuit of the embodiment of the present application may be used in the router maintenance at a later stage, and the fourth immunity circuit is added to the motherboard of the router, or the fourth immunity circuit may also be used in the manufacturing process of the router, and when the router is manufactured, the fourth immunity circuit is integrated in the motherboard of the router, so as to improve the network instability of the router. The fourth anti-interference circuit may be any other type of anti-interference circuit, and the embodiments of the present application are not particularly limited.

It is to be understood that the communication circuit provided in the embodiment of the present application may include any one or more of the first immunity circuit shown in fig. 3, the second immunity circuit shown in fig. 5, the third immunity circuit shown in fig. 8, and the fourth immunity circuit shown in fig. 11. Illustratively, the communication circuit may include both the first immunity circuit shown in fig. 3 and the second immunity circuit shown in fig. 5; the communication circuit may further include: the first immunity circuit shown in fig. 3, the second immunity circuit shown in fig. 5, the third immunity circuit shown in fig. 8, and the fourth immunity circuit shown in fig. 11 are not limited in particular.

In some embodiments, SOC 301 also includes a reset module. Illustratively, as shown in fig. 3, 5, 8, and 11, the reset module of the SOC 301 has one port, i.e., the seventh port 301g. The seventh port 301g is used to send a reset signal.

Adaptively, WIFI module 302 also includes a reset module. Illustratively, as shown in fig. 3, 5, 8, and 11, the reset module of the WIFI module 302 has one port, i.e., a seventh port 302g. The seventh port 302g is for receiving a reset signal. When the reset signal is effective, the WIFI module resets.

It is understood that the SOC 301 includes a set of PCIE interfaces, where the PCIE interfaces include: the SOC 301 includes a first port 301a, a second port 301b, a third port 301c, a fourth port 301d, a fifth port 301e, a sixth port 301f, and a seventh port 301g.

The above embodiment describes the anti-interference circuit by taking an example that the SOC includes a set of PCIE interfaces. The SOC may include multiple sets of PCIE interfaces, and each set of PCIE interfaces may have an anti-interference circuit corresponding thereto. Illustratively, the first set of PCIE interfaces is correspondingly connected to one or more of the first anti-interference circuit, the second anti-interference circuit, the third anti-interference circuit, and the fourth anti-interference circuit. The second group of PCIE interfaces are correspondingly connected with one or more of a first anti-interference circuit, a second anti-interference circuit, a third anti-interference circuit and a fourth anti-interference circuit. And are not limited herein.

Fig. 14 is a schematic structural diagram of a communication circuit according to an embodiment of the present disclosure. Taking as an example that each group of PCIE interfaces is correspondingly connected with a first anti-interference circuit, a second anti-interference circuit, a third anti-interference circuit, and a fourth anti-interference circuit, as shown in fig. 14, the communication circuit includes an SOC 1401, a 2.4G WIFI module 1402, a 5G WIFI module 1403, a 2.4G anti-interference circuit 1404, and a 5G anti-interference circuit 1405.SOC 1401 is connected with 2.4G WIFI module 1402 through 2.4G immunity circuit 1404, and SOC 1401 is connected with 5G WIFI module 1403 through 5G immunity circuit 1405.

In fig. 14, a first set of PCIE interfaces of SOC 1401 corresponds to a set of PCIE interfaces of 2.4G WIFI module 1402; the second set of PCIE interfaces of SOC 1401 corresponds to a set of PCIE interfaces of 5G WIFI module 1403.

Specifically, the SOC 1401 includes two sets of PCIE interfaces, and the first set of PCIE interfaces includes: TX1+ port, TX 1-port, RX1+ port, RX 1-port, CLK1+ port, CLK 1-port, and RST1 port. The second set of PCIE interfaces includes: TX2+ port, TX 2-port, RX2+ port, RX 2-port, CLK2+ port, CLK 2-port, and RST2 port.

Correspondingly, the 2.4G WIFI module 1402 includes a set of PCIE interfaces, and the PCIE interfaces include: RX1+ port, RX 1-port, TX1+ port, TX 1-port, CLK1+ port, CLK 1-port, and RST1 port.

5G WIFI module 1403 includes a set of PCIE interfaces, and these PCIE interfaces include: RX2+ port, RX 2-port, TX2+ port, TX 2-port, CLK2+ port, CLK 2-port, and RST2 port.

The 2.4G immunity circuit 1404 is configured to perform immunity processing on signals transmitted between the SOC 1401 and the 2.4G WIFI module 1402. The detailed structure and function of the 2.4G anti-interference circuit 1404 can refer to the corresponding descriptions above, and are not described herein. A 5G immunity circuit 1405 may be used to immunity signals transmitted between SOC 1401 and 5G WIFI module 1403. The specific structure and function of the 5G anti-interference circuit 1405 can refer to the corresponding description above, and are not described herein again.

The above embodiments are described by taking an example in which the PCIE bus transmission signal is used in the communication circuit. The anti-interference circuit shown in the embodiment of the present application may also be applied to other buses that transmit differential signals, for example, an SGMII bus, and the like, which is not limited herein.

The communication circuit provided by the embodiment of the application can be applied to an electronic device with a routing function, an electronic device with a hot spot service, or an electronic device using a full network convergence acceleration technology (link turbo). And is not particularly limited herein. The communication circuit provided by the embodiment of the application can be applied to electronic equipment with a WIFI function. The electronic device includes a router, a mobile phone (mobile phone), a tablet computer (Pad), a computer with a wireless transceiving function, and the like, and specific device forms of the terminal device and the like may refer to the above description, and are not described herein again.

Fig. 15 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present disclosure. As shown in fig. 15, the electronic apparatus includes: power module 1501, processing module 1502, and WIFI module 1503. The specific connection and respective functions of the processing module 1502 and the WIFI module 1503 may refer to corresponding descriptions in the communication circuit, which are not described herein again.

Power module 1501 may include power supplies, power management components, and the like. The power management component is used for managing charging of the power supply and power supply of the power supply to other modules (such as the processing module and the WIFI module).

If the electronic device is a router, the electronic device may further include: memory, switches, physical interfaces, etc. Physical interfaces include, but are not limited to: a local area network interface, a wide area network interface, and a router configuration interface. The router configuration interface includes a console port and an auxiliary port.

The memory can be non-volatile memory, random access memory, flash memory, and read only memory. The router comprises a random access memory, a read-only memory and a random storage memory, wherein the random access memory discards information when the router is started or power supply is interrupted, the read-only memory stores starting software of the router, the starting software is first software operated by the router and is responsible for the router to enter a normal working state, and the router stores a complete operating system in the random access memory as a backup so as to be used as a backup when the operating system cannot be used. The router owns a dynamic host configuration protocol (DHCP server).

The random access memory can be used as a storage device of the IP pool, and the DHCP server of the router selects an IP address from the IP pool and distributes the IP address to an electronic device connected with the router. In addition, the random access memory may store various parameters such as a MAC address of the electronic device connected to the router, an IP address assigned to the electronic device by the router, and a binding relationship between the MAC address and the IP address of the electronic device connected to the router.

In addition, the random access memory may also store picture resource data (location of the LAN interface on the router, interface parameters, appearance, etc.) of a virtual interface (virtual LAN interface of the LAN interface) corresponding to a physical interface (such as the LAN interface) of the router, a mapping relationship between the physical interface and the virtual interface, and the like.

The rom is typically provided on one or more chips soldered to the motherboard of the router.

The main purpose of the flash memory is to store the operating system of the router and maintain the normal operation of the router, and if the router is installed with the flash memory, the flash memory is mainly used to boot the default location of the operating system of the router, so long as the capacity of the flash memory is sufficient, a plurality of operating system images can be stored to provide multiple boot options, wherein the operating system of the router may adopt a Linux operating system or other operating systems, which is not limited herein.

The main purpose of the non-volatile memory is to store configuration data (boot configuration) that is read in when the operating system boots. The random access memory is mainly used as an operating system table and a buffer storage area, and the operating system can meet all conventional storage requirements through the random access memory so that the router can quickly access the information, wherein the storage speed of the random access memory is superior to the three types mentioned above.

It is to be understood that parameters such as an IP pool of the router, parameters of an electronic device connected to the router, picture resource data, and a binding relationship between a MAC address and an IP address of an electronic device connected to the router may also be stored in the non-volatile memory or other types of memories, and the embodiments of the present application are not limited herein.

If the electronic device is a terminal device such as a mobile phone or a tablet, the electronic device may further include one or more of the following modules: an external memory interface, an internal memory, a Universal Serial Bus (USB) interface, a mobile communication module, an audio module, a speaker, a receiver, a microphone, an earphone interface, a sensor module, a button, a motor, an indicator, a camera, a display screen, and a Subscriber Identity Module (SIM) card interface, etc. Wherein, the sensor module may include a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

It is to be understood that the illustrated structure of the embodiment of the present invention does not limit the electronic device. In other embodiments of the present application, an electronic device may include more or fewer components than shown, or some components may be combined, some components may be split, or a different arrangement of components may be used. The illustrated components may be implemented in hardware, software, or a combination of software and hardware. The embodiment of the application provides a chip. The chip comprises the communication circuit. The principle and technical effects are similar to those of the related embodiments, and are not described herein again.

It should be noted that, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) referred to in the present application are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards, and are provided with corresponding operation entries for the user to choose authorization or denial.

The above embodiments are only for illustrating the embodiments of the present invention and are not to be construed as limiting the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the embodiments of the present invention shall be included in the scope of the present invention.

Claims

1. A communication circuit, comprising: the device comprises a processing module, an anti-interference circuit and a wireless fidelity (WIFI) module;

the anti-interference circuit is arranged on a bus path between the processing module and the WIFI module;

the processing module is used for transmitting a first data signal to the WIFI module and receiving a second data signal from the WIFI module;

the anti-interference circuit is used for filtering interference suffered by the bus when the bus transmits the first data signal and/or filtering interference suffered by the bus when the bus transmits the second data signal;

the WIFI module is used for receiving the first data signal from the processing module and transmitting the second data signal to the processing module;

wherein the immunity circuit comprises a first common mode inductor and/or a second common mode inductor;

one end of the first common-mode inductor is connected with a first group of interfaces used for transmitting the first data signals in the processing module, and the other end of the first common-mode inductor is connected with a second group of interfaces used for transmitting the first data signals in the WIFI module;

one end of the second common-mode inductor is connected with a third group of interfaces used for transmitting the second data signals in the processing module, and the other end of the second common-mode inductor is connected with a fourth group of interfaces used for transmitting the second data signals in the WIFI module.

2. The communication circuit of claim 1, wherein the immunity circuit further comprises a first capacitance, and/or a second capacitance;

one end of the first capacitor is connected with a first interface or a second interface, the other end of the first capacitor is grounded, the first interface is any one of the first group of interfaces, and the second interface is any one of the second group of interfaces;

one end of the second capacitor is connected with a third interface or a fourth interface, the other end of the second capacitor is grounded, the third interface is any one of the third group of interfaces, and the fourth interface is any one of the fourth group of interfaces;

the value of the first capacitor is any value from 0pF to 68pF, and the value of the second capacitor is any value from 0pF to 68 pF.

3. The communication circuit of claim 2,

the value of the first capacitor is 8.2pF, and the first capacitor is connected with the second interface and is positioned at one side close to the WIFI module;

the value of second electric capacity is 8.2pF, the second electric capacity with fourth interface connection, and be located and be close to processing module's one side.

4. The communication circuit of any of claims 1-3, wherein the immunity circuit further comprises: a first transient diode, and/or a second transient diode;

one end of the first transient diode is connected with the first interface or the second interface, and the other end of the first transient diode is grounded;

one end of the second transient diode is connected with the third interface or the fourth interface, and the other end of the second transient diode is grounded.

5. The communication circuit according to any of claims 1-3, wherein the processing module is further configured to transmit a clock signal to the WIFI module, the clock signal being configured to trigger the WIFI module to read the first data signal;

the immunity circuit further includes: a third capacitor;

one end of the third capacitor is connected with a fifth group of interfaces used for transmitting the clock signals in the processing module, and the other end of the third capacitor is connected with a sixth group of interfaces used for transmitting the clock signals in the WIFI module;

the value of the third capacitor is any value from 0pF to 265 pF.

6. The communication circuit of claim 5,

the value of the third capacitor is 100pF.

7. The communication circuit of any of claims 1-3, wherein the processing module is further configured to transmit a clock signal to the WIFI module, the clock signal being configured to trigger the WIFI module to read the first data signal;

the immunity circuit further includes: a fourth capacitor;

one end of the fourth capacitor is connected with a fifth interface or a sixth interface, the other end of the fourth capacitor is grounded, the fifth interface is any one of a fifth group of interfaces used for transmitting the clock signal in the processing module, and the sixth interface is any one of a sixth group of interfaces used for transmitting the clock signal in the WIFI module;

the value of the fourth capacitor is any value from 0pF to 68 pF.

8. The communication circuit of claim 7,

the value of fourth electric capacity is 8.2pF, the fourth electric capacity with sixth interface connection, and be located and be close to one side of WIFI module.

9. The communication circuit of any of claims 1-3, wherein the bus is a PCIE bus or a serial gigabit media independent SGMII bus.

10. The communication circuit of any of claims 1-3, wherein the WIFI module comprises: the WIFI module works in the 2.4G frequency band and/or the WIFI module works in the 5G frequency band.

11. An electronic device, comprising: a power supply module, and the communication circuit of any one of claims 1-10; the power module is used for supplying power to the communication circuit.