CN115866341B - Method and device for HDMIPHY loop-back test based on FPGA - Google Patents
Method and device for HDMIPHY loop-back test based on FPGA Download PDFInfo
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Abstract
The invention is suitable for the field of chip test, and provides a method and a device for HDMIPHY loop back test based on FPGA, the method for HDMIPHY loop back test bypasses HDMI protocol layer, directly applies excitation to HDMIPHY, receives and realizes loop back after signal speed reduction, and then compares the signals, the method does not need to develop a chip, reduces the risk, does not need HDMIPHY internal data source capable of generating rules, has no excessive limitation to HDMIPHY, and has better universality; in addition, the FPGA platform is adopted for realizing flexible operation, abundant debugging means, and bypasses the HDMI protocol layer, thereby avoiding the resource expense of encoding and decoding.
Description
Technical Field
The invention belongs to the technical field of chip testing, and particularly relates to a HDMIPHY loop-back testing method and device based on an FPGA.
Background
In recent years, with the increasing demand for multimedia applications, various types of digital display interfaces are beginning to appear on electronic devices in daily use. These display interfaces include a high definition multimedia interface (HighDefinition MultimediaInterface, HDMI), a digital display interface (DP), a mobile industry processor interface (MobileIndustryProcessorInterface, MIPI), and the like. Among them, the HDMI interface is most widely used, and it is generally integrated on a computer, a server, a television, or a liquid crystal display.
HDMI can be divided into an HDMI output Terminal (TX) and an HDMI receiving terminal (Resiever, RX) in the transmission direction. The protocol layer (Conterller, ctrl) and the transport layer (PHY) are classified according to hierarchical division. In the modern pursuit of high-definition audio and video, the transmission speed requirement on the HDMI interface is higher and higher, and then the transmission speed of HDMIPHY is higher and higher. This presents a certain difficulty for testing HDMITX outputs, as mass production testing of chips is typically done with an automated tester (AutomaticTestEquipment, ATE). However, during testing the high-speed display interface, the ATE machine station cannot directly sample the high-speed signal transmitted by HDMIPHY due to the limitation of the interface speed, and thus the correctness of the interface transmission cannot be detected.
There are generally two solutions to this problem: firstly, a special test chip is developed, and the test chip is used for receiving HDMIPHY high-speed signals sent by the test chip so as to detect the correctness of the signals. The precondition is that HDMIPHY is built in a regular data generator, the original data can be deduced on the same rule outside the chip, and the original data is compared with the received data. Such tests are very specific, but require significant costs and risk of failure of the tape-out. And secondly, the signal transmitted by HDMITXPHY is subjected to protocol decoding by means of the HDMIMRX receiving chip, and the signal is restored to an original signal so as to judge the correctness. This approach is not flexible enough and the receiving end may not be fully compatible once the HDMI interface standard of the transmitting end upgrades or alters some functions. The two methods have the problems of long development period and limited debugging means.
Disclosure of Invention
In view of the above problems, the present invention aims to provide a method and a device for HDMIPHY loop-back test based on FPGA, which aims to solve the technical problems of difficult high-speed signal sampling, long development period of test scheme, high cost, limited debugging means, and incapability of changing back to test when the existing automatic tester tests the high-speed display interface.
On one hand, the HDMIPHY loop-back test device based on the FPGA comprises an automatic tester, a chip to be tested, a data storage area and the FPGA, wherein the chip to be tested comprises a first debugging interface, a pixel acquisition module, a storage controller, a first clock engine, a first pixel engine, an HDMI controller, a current divider and HDMIPHY, and the FPGA comprises a second debugging interface, high-speed Serdes, a second pixel engine, a data acquisition module, a second clock engine and a data buffer area;
The automatic testing machine is connected to the first debugging interface, the second debugging interface and the shunt;
In the chip to be tested, a storage controller is connected to a data storage area, the first debugging interface is respectively connected to a data acquisition module, the storage controller, a first clock engine and HDMIPHY, the data acquisition module is connected to the storage controller, the storage controller is connected to a first pixel engine, one path of the first pixel engine is directly connected to a first port of a shunt, the other path of the first pixel engine is connected to a second port of the shunt through an HDMI (high-definition multimedia interface) controller, an output port of the shunt is connected to HDMIPHY, and HDMIPHY is connected to high-speed Serdes;
In the FPGA, the second debugging interface is respectively connected to the high-speed Serdes, the second pixel engine and the data buffer area, the high-speed Serdes is connected to the data buffer area through the data acquisition module, the data acquisition module is connected to the second pixel engine through the second clock engine, the data buffer area is also connected to the second pixel engine, and the output end of the second pixel engine is connected to the pixel acquisition module of the chip to be tested.
Further, the automatic testing machine is used for generating test data and instructions, and inputting, reading back and comparing and checking the data and the instructions;
the data storage area is used for storing test data;
The first debugging interface is used for receiving test data and instructions sent by the automatic tester and controlling components related to the test in the chip to be tested, and comprises a pixel acquisition module, a storage controller and a first clock engine; the storage controller is used for controlling the access of pixel data in the data storage area; the first pixel engine is used for receiving the data output by the storage controller, converting the data into high-speed pixel signals and control signals related to the time sequence of the high-speed pixel signals, transmitting the control signals to the HDMI controller in a functional mode, and transmitting the control signals to the current divider in a test mode; the HDMI controller is used for receiving the signals output by the pixel engine module and carrying out HDMI format protocol coding, packaging and forwarding; the HDMIPHY is used for transmitting the high-speed signal subjected to protocol coding to an FPGA outside the chip in a functional mode, receiving pixel data from the shunt in a test mode and transmitting the pixel data to the FPGA outside the chip; the first clock engine is used for generating a clock signal matched with HDMIPHY transmission high-speed signals; the current divider is used for selecting one of signals, and the mode switching end of the current divider is controlled by the automatic testing machine and is used for selecting a functional mode or a testing mode; the pixel acquisition module is used for receiving low-speed pixel signals and accompanying control signals, transmitting the low-speed pixel signals and the accompanying control signals to the storage controller and finally storing the low-speed pixel signals and the accompanying control signals in the data storage area;
In the FPGA, the second debugging interface is used for receiving and issuing a control instruction of the automatic testing machine; the high-speed Serdes is used for receiving a high-speed signal from a chip to be tested; the data acquisition module is used for acquiring high-speed signals received by the high-speed Serdes and storing the high-speed signals in the data buffer area; the second pixel engine is used for taking out data from the data buffer area, converting the data into a low-speed video signal and an accompanying control signal, and transmitting the low-speed video signal and the accompanying control signal to a pixel acquisition module of the chip to be tested; the second clock module is used for generating a clock signal matched with the low-speed video signal transmitted by the second pixel engine.
Further, in the functional mode, HDMIPHY receives data from the HDMI controller, and performs transmission of the HDMI timing signal; in test mode HDMIPHY receives data from the pixel engine number one and clock signals from the clock engine number one directly and transmits them off-chip.
In another aspect, the method for performing HDMIPHY loop-back test based on the FPGA comprises the following steps:
the automatic testing machine sets the working mode of the chip to be tested as a testing mode by controlling the mode switching end of the current divider;
The automatic testing machine operates the storage controller through a first debugging interface of the chip to be tested, and writes test data of a single test into a first area of the data storage area;
the automatic tester configures HDMIPHY, a first pixel engine and a first clock engine of the chip to be tested through a first debugging interface of the chip to be tested;
The automatic testing machine is configured with a high-speed Serdes, a data acquisition module, a second pixel engine and a second clock engine through a second debugging interface of the FPGA;
Starting the FPGA to receive data enabling and enabling the chip to be tested to transmit data;
the storage controller reads the test data of the first area, outputs the test data to the high-speed Serdes of the FPGA through a first pixel engine, a current divider and HDMIPHY, and then acquires the data through the data acquisition module and temporarily stores the data in the data buffer area;
Configuring a pixel acquisition module of a chip to be tested and a second pixel engine of the FPGA;
starting a chip to be tested to receive data enabling and sending data enabling by the FPGA;
the second pixel engine acquires data from the data buffer area and sends the data to a pixel acquisition module of the chip to be tested in a low-speed mode, and then the low-speed data can be written into a second area of the data storage area through the storage controller;
the automatic testing machine reads the data in the first area and the second area in the data storage area and performs data comparison;
If the test result is the same, the loopback test is passed, otherwise, the loopback test is not passed, and the test result is output.
The beneficial effects of the invention are as follows: HDMI is a unidirectional interface, loop-back test can not be carried out, the method for HDMIPHY loop-back test bypasses HDMI protocol layer, directly applies excitation to HDMIPHY, receives and realizes loop-back after signal speed reduction, and then compares, the method does not need to develop a chip, reduces risk, does not need a regular data source generated in HDMIPHY, has no excessive limitation to HDMIPHY, and has better universality; in addition, the FPGA platform is adopted for realizing flexible operation, abundant debugging means, and bypasses the HDMI protocol layer, thereby avoiding the resource expense of encoding and decoding.
In a word, the invention bypasses the encoding and decoding process of the HDMI controller, so that the whole scheme is simpler and easier to realize; on the basis, a HDMIPHY loop-back test is constructed, and the loop-back test is introduced into a test scheme of the unidirectional interface, so that the practical problem is solved.
Drawings
FIG. 1 is a block diagram of an FPGA-based HDMIPHY loop-back test apparatus provided by an embodiment of the present invention;
FIG. 2 is a flow chart of a method for performing a HDMIPHY loop-back test based on an FPGA provided by an embodiment of the present invention;
Fig. 3 is a schematic diagram of a signal loop according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Loopback testing (Loopback, LP) is a common method of functional testing of bi-directional interfaces (interfaces containing both TX and RX) by means of self-collection to detect both TX and RX ports. This approach is generally not applicable to HDMI-like unidirectional interfaces. The invention bypasses the encoding and decoding process of the HDMI controller, so that the whole scheme is simpler and easier to realize; on the basis, a HDMIPHY loop-back test is constructed, and the loop-back test is introduced into a test scheme of the unidirectional interface, so that the practical problem is solved. In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Fig. 1 shows the structure of the device for performing the HDMIPHY loop-back test based on the FPGA according to the embodiment of the present invention, and only the portion relevant to the embodiment of the present invention is shown for convenience of explanation.
The HDMIPHY loop-back test device based on the FPGA provided by the embodiment comprises an automatic tester, a chip to be tested, a data storage area and the FPGA, wherein the chip to be tested, the data storage area and the FPGA are positioned on a test board.
The upper computer, namely the automatic testing machine, has rich IO resources and certain operation capability, is directly connected with the chip to be tested and the FPGA, and has the capabilities of controlling the testing flow, generating test data and instructions, inputting data instructions, reading back data, comparing and checking data and the like, and the function of the automatic testing machine is responsible for controlling the testing flow, inputting the test data and collecting, comparing and judging the test result. The test board card is integrated with a chip to be tested, a data storage area and an FPGA. The test object HDMIPHY is integrated inside the chip to be tested. The data storage area is used for storing data required for testing, and in order to ensure the reading speed, a Dynamic Random Access Memory (DRAM) is selected as the storage grain. The chip to be tested is a video transmission chip integrated with HDMITX interfaces, and the function of the chip to be tested is to be responsible for receiving the operation instructions and data of the automatic tester, sending high-speed data stream to the outside of the chip and receiving low-speed data stream from the outside of the chip. The FPGA is responsible for receiving high-speed data streams from a chip under test, converting the high-speed data streams into low-speed data streams, and outputting the low-speed data streams.
From a specific structure, as shown in fig. 1, the chip to be tested includes a first debug interface, a pixel acquisition module, a storage controller, a first clock engine, a first pixel engine, an HDMI controller, a splitter and HDMIPHY, and the FPGA includes a second debug interface, a high-speed Serdes, a second pixel engine, a data acquisition module, a second clock engine and a data buffer.
For specific connection relation, the automatic testing machine is connected to a first debugging interface, a second debugging interface and a shunt.
In the chip to be tested, the storage controller is connected to the data storage area, the first debugging interface is respectively connected to the data acquisition module, the storage controller, the first clock engine and HDMIPHY, the data acquisition module is connected to the storage controller, the storage controller is connected to the first pixel engine, one path of the first pixel engine is directly connected to a first port of the splitter, the other path of the first pixel engine is connected to a second port of the splitter through the HDMI controller, an output port of the splitter is connected to HDMIPHY, and HDMIPHY is connected to high-speed Serdes.
In the FPGA, the second debugging interface is respectively connected to the high-speed Serdes, the second pixel engine and the data buffer area, the high-speed Serdes is connected to the data buffer area through the data acquisition module, the data acquisition module is connected to the second pixel engine through the second clock engine, the data buffer area is also connected to the second pixel engine, and the output end of the second pixel engine is connected to the pixel acquisition module of the chip to be tested.
In the structure, the chip to be tested is provided with the first debugging interface, the automatic tester is communicated with the chip to be tested through the first debugging interface, and the first debugging interface can control all components in the chip to be tested so as to ensure that control instructions of the automatic tester take effect on all components in the chip to be tested. In the chip to be tested, a first pixel engine generates a high-speed signal, and at least one HDMIPHY of the first pixel engine is used for transmitting the high-speed signal; and the pixel acquisition module is used for receiving low-speed signals from the FPGA. The data storage area is used to hold input data from an automatic test machine. The data acquisition module of the FPGA acquires high-speed signals and stores the high-speed signals in the data buffer area, and the second pixel engine is responsible for converting the high-speed signal flow into low-speed signal flow and outputting the low-speed video flow. Specifically, the specific functions of the above components are as follows:
The first debugging interface is used for receiving test data and instructions sent by the automatic tester and controlling components related to the test in the chip to be tested, and comprises a pixel acquisition module, a storage controller and a first clock engine; the storage controller is used for controlling the access of pixel data in the data storage area; the first pixel engine is used for receiving the data output by the storage controller, converting the data into high-speed pixel signals and control signals related to the time sequence of the high-speed pixel signals, transmitting the control signals to the HDMI controller in a functional mode, and transmitting the control signals to the current divider in a test mode; the HDMI controller is used for receiving the signals output by the pixel engine module and carrying out HDMI format protocol coding, packaging and forwarding; the HDMIPHY is used for transmitting the high-speed signal subjected to protocol coding to an FPGA outside the chip in a functional mode, receiving pixel data from the shunt in a test mode and transmitting the pixel data to the FPGA outside the chip; the first clock engine is used for generating a clock signal matched with HDMIPHY transmission high-speed signals; the current divider is used for selecting one of signals, and the mode switching end of the current divider is controlled by the automatic testing machine and is used for selecting a functional mode or a testing mode; the pixel acquisition module is used for receiving low-speed pixel signals and accompanying control signals, transmitting the low-speed pixel signals and the accompanying control signals to the storage controller, and finally storing the low-speed pixel signals and the accompanying control signals in the data storage area.
In this configuration, the current mode is selected by the current splitter according to the input from the mode switching terminal of the automatic test machine, and the current mode is the functional mode or the test mode. In the functional mode (mode switching terminal input is "1"), HDMIPHY receives data from the HDMI controller, and performs transmission of the HDMI timing signal. In the test mode (mode switch input "0"), HDMIPHY directly receives data from the pixel engine No. one and clock signals from the clock engine No. one and transmits them to the off-chip. The existence of the current divider bypasses the encoding process of the HDMI controller at the chip end to be tested in the test mode, and simultaneously bypasses the decoding process of the HDMI at the FPGA receiving end, so that the test time and the resource expenditure of the FPGA can be effectively saved, and meanwhile, the complexity of the whole test system is reduced. In functional mode, there is no mode switch command from the automatic tester, so the input at the mode switch should always be "1".
In the FPGA, the FPGA device needs to be designed and programmed in advance and has the required functions. The FPGA can be programmed and debugged repeatedly, has great flexibility, and the structural design of the components in the FPGA jointly realizes a speed reduction function, receives high-speed signals from HDMIPHY, converts the high-speed signals into low-speed video signals and then forwards the low-speed video signals to a chip end to be tested. In particular, the PGA has the following components inside: a debug interface No. two, high speed Serdes (SerializerDeserializer, serdes, serializer/deserializer), a pixel engine No. two, a data acquisition module, a clock engine No. two, and a data buffer. The second debugging interface is used for receiving and issuing a control instruction of the automatic testing machine; the high-speed Serdes is used for receiving a high-speed signal from a chip to be tested, is a high-speed IO integrated in the FPGA and has the initial capability of the high-speed signal; the data acquisition module is used for acquiring high-speed signals received by the high-speed Serdes and storing the high-speed signals in the data buffer area; the second pixel engine is used for taking out data from the data buffer area, converting the data into a low-speed video signal and an accompanying control signal, and transmitting the low-speed video signal and the accompanying control signal to a pixel acquisition module of the chip to be tested; the second clock module is used for generating a clock signal matched with the low-speed video signal transmitted by the second pixel engine.
Based on the above structure, the present embodiment further provides another method for performing HDMIPHY loop-back test based on FPGA, as shown in fig. 2, including the following procedures:
S1, an automatic testing machine sets a working mode of a chip to be tested as a testing mode by controlling a mode switching end of a shunt;
s2, the automatic testing machine operates the storage controller through a first debugging interface of the chip to be tested, and test data of a single test are written into a first area of the data storage area;
S3, the automatic testing machine configures HDMIPHY, a first pixel engine and a first clock engine of the chip to be tested through a first debugging interface of the chip to be tested;
S4, the automatic testing machine configures a high-speed Serdes, a data acquisition module, a second pixel engine and a second clock engine through a second debugging interface of the FPGA;
s5, starting the FPGA to receive data enabling and enabling the chip to be tested to transmit data;
S6, the storage controller reads test data of the first area, outputs the test data to the high-speed Serdes of the FPGA through a first pixel engine, a current divider and HDMIPHY, and then acquires the data through the data acquisition module and temporarily stores the data in the data buffer area;
s7, configuring a pixel acquisition module of a chip to be tested and a second pixel engine of the FPGA;
S8, starting the chip to be tested to receive data enabling and the FPGA to send the data enabling;
s9, the second pixel engine acquires data from the data buffer area and sends the data to a pixel acquisition module of the chip to be tested in a low-speed mode, and then the low-speed data can be written into a second area of the data storage area through the storage controller;
S10, the automatic testing machine reads data in a first area and a second area in the data storage area and performs data comparison;
s11, if the loop-back test is the same, the loop-back test passes, otherwise, the loop-back test does not pass, and a test result is output.
In the process, firstly, the chip to be tested is switched into a test mode, so that data is ensured to bypass the HDMI controller and is directly fed into HDMIPHY, then the memory controller is operated through a debugging interface of the chip to be tested, and a certain amount of data is written into a first area of the data storage area to be used as original data to be transmitted in the test process; and components such as HDMIPHY, a first pixel engine, a first clock engine and the like in the chip to be tested are configured through a debugging interface of the chip to be tested, so that the chip to be tested is ready for sending data. And then configuring components such as a high-speed Serdes, a data acquisition module, a second pixel engine, a second clock engine and the like through a debugging interface of the FPGA, so that the FPGA is ready for receiving data.
And starting the FPGA to receive data enabling and starting the chip end to be tested to transmit the data enabling. At this time, the data flow on the test board is shown as TX data flow in fig. 3, and the FPGA end receives data at high speed Serdes and temporarily stores the data in the data buffer. It should be noted that the data buffer space is limited, and thus there is a certain requirement for the amount of data to be transmitted at a time. That is, the automatic tester needs to control the data amount of a single test according to the size of the data buffer area of the FPGA so as to avoid the situation of data loss. After the data buffer area is full, the chip end to be tested should just send the data volume of single test at this moment.
And configuring a pixel acquisition module of the chip to be tested, and preparing to receive data. And configuring a pixel engine module of the FPGA to prepare to send the data in the data buffer area to a chip end to be tested in a low-speed mode.
And starting the chip to be tested to receive the data enabling, and starting the FPGA end to send the data enabling. The flow of data on the test board is now shown as the RX data flow in FIG. 3. And the pixel acquisition module of the chip to be tested sends the received data to the storage controller and then writes the received data into a second area of the storage control area. At this point HDMIPHY the single loop test has completed and the data flow is as shown by the signal loop in fig. 3.
And the automatic testing machine reads the data in the first area and the second area of the data storage area, compares the data in the two read-back areas, and if the data in the two read-back areas are the same, the loop test is passed. Otherwise, the test result is output finally.
The single test is completed. If the test is to be continued, the above steps are repeated.
The invention configures the chip to be tested through the automatic testing machine, so that the data stream is directly transmitted to the outside of the chip from the first area flow HDMIPHY in the data storage area without being coded and converted by the protocol layer; the FPGA receives a high-speed signal from the chip to be tested and converts the high-speed signal into a low-speed signal, and the low-speed signal is transmitted back to the chip to be tested. The chip to be tested receives the low-speed signal and transfers the data stream to a second area in the storage area; and the automatic testing machine reads the first area and the second area in the storage area, compares the read data, and if the read data are the same, judges that the test is passed, and otherwise, does not pass. The method introduces a field programmable gate array device (FieldProgrammableGate Array, FPGA), can greatly shorten the development period, enrich the debugging means in the test process, and improve some defects in the common HDMI means test method. The method of the invention realizes the technical scheme of providing loop-back test for the unidirectional interfaces such as HDMI.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (2)
1. The device for HDMIPHY loop back test based on the FPGA is characterized by comprising an automatic tester, a chip to be tested, a data storage area and the FPGA, wherein the chip to be tested comprises a first debugging interface, a pixel acquisition module, a storage controller, a first clock engine, a first pixel engine, an HDMI controller, a shunt and HDMIPHY, and the FPGA comprises a second debugging interface, high-speed Serdes, a second pixel engine, a data acquisition module, a second clock engine and a data buffer area;
The automatic testing machine is connected to the first debugging interface, the second debugging interface and the shunt;
In the chip to be tested, a storage controller is connected to a data storage area, the first debugging interface is respectively connected to a data acquisition module, the storage controller, a first clock engine and HDMIPHY, the data acquisition module is connected to the storage controller, the storage controller is connected to a first pixel engine, one path of the first pixel engine is directly connected to a first port of a shunt, the other path of the first pixel engine is connected to a second port of the shunt through an HDMI (high-definition multimedia interface) controller, an output port of the shunt is connected to HDMIPHY, and HDMIPHY is connected to high-speed Serdes;
In the FPGA, a second debugging interface is respectively connected to a high-speed Serdes, a second pixel engine and a data buffer area, the high-speed Serdes is connected to the data buffer area through a data acquisition module, the data acquisition module is connected to the second pixel engine through a second clock engine, the data buffer area is also connected to the second pixel engine, and the output end of the second pixel engine is connected to a pixel acquisition module of a chip to be tested;
The automatic testing machine is used for generating test data and instructions, and inputting, reading back and comparing and checking the data and the instructions;
the data storage area is used for storing test data;
The first debugging interface is used for receiving test data and instructions sent by the automatic tester and controlling components related to the test in the chip to be tested, and comprises a pixel acquisition module, a storage controller and a first clock engine; the storage controller is used for controlling the access of pixel data in the data storage area; the first pixel engine is used for receiving the data output by the storage controller, converting the data into high-speed pixel signals and control signals related to the time sequence of the high-speed pixel signals, transmitting the control signals to the HDMI controller in a functional mode, and transmitting the control signals to the current divider in a test mode; the HDMI controller is used for receiving the signals output by the pixel engine module and carrying out HDMI format protocol coding, packaging and forwarding; the HDMIPHY is used for transmitting the high-speed signal subjected to protocol coding to an FPGA outside the chip in a functional mode, receiving pixel data from the shunt in a test mode and transmitting the pixel data to the FPGA outside the chip; the first clock engine is used for generating a clock signal matched with HDMIPHY transmission high-speed signals; the current divider is used for selecting one of signals, and the mode switching end of the current divider is controlled by the automatic testing machine and is used for selecting a functional mode or a testing mode; the pixel acquisition module is used for receiving low-speed pixel signals and accompanying control signals, transmitting the low-speed pixel signals and the accompanying control signals to the storage controller and finally storing the low-speed pixel signals and the accompanying control signals in the data storage area;
In the FPGA, the second debugging interface is used for receiving and issuing a control instruction of the automatic testing machine; the high-speed Serdes is used for receiving a high-speed signal from a chip to be tested; the data acquisition module is used for acquiring high-speed signals received by the high-speed Serdes and storing the high-speed signals in the data buffer area; the second pixel engine is used for taking out data from the data buffer area, converting the data into a low-speed video signal and an accompanying control signal, and transmitting the low-speed video signal and the accompanying control signal to a pixel acquisition module of the chip to be tested; the second clock engine is used for generating a clock signal matched with the low-speed video signal transmitted by the second pixel engine;
In the functional mode, HDMIPHY receives data from the HDMI controller, and performs transmission of HDMI timing signals; in test mode HDMIPHY receives data from the pixel engine number one and clock signals from the clock engine number one directly and transmits them off-chip.
2. A method for HDMIPHY loop-back testing based on an FPGA, the method comprising the steps of:
the automatic testing machine sets the working mode of the chip to be tested as a testing mode by controlling the mode switching end of the current divider;
The automatic testing machine operates the storage controller through a first debugging interface of the chip to be tested, and writes test data of a single test into a first area of the data storage area;
the automatic tester configures HDMIPHY, a first pixel engine and a first clock engine of the chip to be tested through a first debugging interface of the chip to be tested;
The automatic testing machine is configured with a high-speed Serdes, a data acquisition module, a second pixel engine and a second clock engine through a second debugging interface of the FPGA;
Starting the FPGA to receive data enabling and enabling the chip to be tested to transmit data;
The storage controller reads the test data of the first area, outputs the test data to the high-speed Serdes of the FPGA through a first pixel engine, a current divider and HDMIPHY, and then acquires the data through the data acquisition module and temporarily stores the data in the data buffer area;
Configuring a pixel acquisition module of a chip to be tested and a second pixel engine of the FPGA;
starting a chip to be tested to receive data enabling and sending data enabling by the FPGA;
the second pixel engine acquires data from the data buffer area and sends the data to a pixel acquisition module of the chip to be tested in a low-speed mode, and then the low-speed data can be written into a second area of the data storage area through the storage controller;
the automatic testing machine reads the data in the first area and the second area in the data storage area and performs data comparison;
If the test result is the same, the loopback test is passed, otherwise, the loopback test is not passed, and the test result is output.
Priority Applications (1)
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