CN115866262A - Code conversion system, coding method, storage medium and electronic equipment - Google Patents
Code conversion system, coding method, storage medium and electronic equipment Download PDFInfo
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Abstract
The embodiment of the invention discloses a code conversion system, a coding method, a storage medium and electronic equipment. The transcoding system comprises: the calculation module is used for multiplying the determined transformation coefficient and the data to be processed to obtain a first operation result; the transformation coefficient carries out code bit estimation determination on data to be processed through each transformation core; the calculation module comprises a plurality of multiplication units, and each multiplication unit comprises a plurality of general multipliers; and the accumulator is used for carrying out summation operation on the first operation result so as to obtain an encoding result. The scheme makes different transformation types and transformation sizes share one computing module formed by a general multiplier, thereby greatly improving the utilization rate of resources.
Description
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to a transcoding system, a transcoding method, a storage medium, and an electronic device.
Background
In 7 months 2020, the JVET (Joint Video expansion Team) Committee, consisting of the union of ITU-TVCEG and ISO/IEC MPEG, has completed its formulation. Compared with the previous generation Video Coding standard, namely High Efficiency Video Coding (HEVC), the Coding Efficiency of the VVC is increased by about one time, and meanwhile, the computational complexity of the VVC is also greatly increased. Transformation is an important process of VVC, which transforms residual data from a pixel domain to a frequency domain so as to remove redundant information on a transformation domain, and has high use frequency and high computational complexity in an encoding process. In the existing scheme, in the research result of HEVC, a transform structure implemented by using Multiple Constant Multiplication (MCM) has smaller hardware implementation area and power consumption than a transform structure implemented by using a general multiplier. However, as the conversion types and conversion sizes increase in the VVC, the conversion implemented based on the MCM structure will increase a large number of Shift and Add Units (SAUs), thereby greatly increasing the hardware implementation area. Moreover, when the SAUs designed based on the MCM method are used for calculating small blocks, only the corresponding small blocks are used, and the SAUs used for calculating large blocks are in an idle state, so that resources cannot be efficiently used for calculation. In addition, most of the existing schemes are implemented based on butterfly operation characteristics of DCT-II transform types, although the number of operations can be reduced, 64 parallelism degrees are required inside one-dimensional transform in the pipeline design, and such design can cause resource vacancy to a great extent while reducing a certain area in the structure implemented based on the MCM method.
Disclosure of Invention
To solve the above technical problems, embodiments of the present invention provide a transcoding system, a coding method, a storage medium, and an electronic device to solve at least the problems in the prior art.
In a first aspect, an embodiment of the present invention provides a transcoding system, including:
the calculation module is used for multiplying the determined transformation coefficient and the data to be processed to obtain a first operation result; the transformation coefficient carries out code bit estimation and determination on data to be processed through each transformation core; the calculation module comprises a plurality of multiplication units, and each multiplication unit comprises a plurality of general multipliers;
and the accumulator is used for carrying out summation operation on the first operation result so as to obtain an encoding result.
Further, an embodiment of the present invention provides an encoding method, including:
acquiring data to be processed, and performing code bit estimation on the data to be processed to determine a corresponding transformation matrix;
obtaining a corresponding transformation coefficient according to the transformation type and the transformation size corresponding to the transformation matrix;
multiplying the transformation coefficient and the data to be processed by a computing module to obtain a first result; the calculation module comprises a plurality of multiplication units, and each multiplication unit comprises a plurality of general multipliers;
the first result is summed by an accumulator to obtain an encoded result.
Further, an embodiment of the present invention provides a storage medium, on which a computer program is stored, which when executed by a processor implements the encoding method as described in the above embodiment.
Further, an embodiment of the present invention provides a storage medium, an electronic device, including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the encoding method as described in the above embodiments via execution of the executable instructions.
The embodiment of the invention provides a coding transformation system and a coding method, which are used for realizing VVC two-dimensional transformation based on a unified general multiplier, and can realize the support of DCT-II, DCT-VII and DCT-VIII transformation types and transformation sizes of all sizes in VVC by designing a plurality of multiplication units in a calculation module and arranging the same number of multipliers in each multiplication unit; and different transformation types and transformation sizes can be realized by sharing one computing module consisting of a general multiplier, so that the utilization rate of resources is greatly improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention and do not constitute a limitation of the invention. In the drawings:
fig. 1 is a schematic diagram illustrating a transcoding system according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a transcoding system according to an embodiment of the present invention;
FIG. 3 is a DCT-II provided in an embodiment of the present invention 4 And DCT-II 8 A schematic diagram of a transformation matrix;
FIG. 4 is a DCT-VII provided in accordance with an embodiment of the present invention 4 And DCT-VIII 4 A schematic diagram of a transformation relationship of the transformation matrix;
FIG. 5 is a diagram illustrating a general multiplication unit structure according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating an accumulator structure according to an embodiment of the present invention;
fig. 7 is a schematic diagram of an encoding method according to an embodiment of the present invention;
FIG. 8 is a diagram of a program product according to an embodiment of the invention;
fig. 9 is a schematic view of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a code conversion system. Referring to fig. 1, the transcoding system may include: a calculation module 101 and an accumulator 102. The calculation module 101 may perform a multiplication operation on the determined transform coefficient and the data to be processed to obtain a first operation result; the transformation coefficient carries out code bit estimation determination on data to be processed through each transformation core; the calculation module comprises a plurality of multiplication units, and each multiplication unit comprises a plurality of universal multipliers. The accumulator 102 may be configured to perform a summation operation on the first operation result to obtain an encoding result.
In the embodiment of the present application, the calculation module may include 32 multiplication units; each of the multiplication units includes 16 general-purpose multipliers.
In an embodiment of the present application, the system further includes: an internal register 105 for storing different types of transformation matrices.
In the embodiment of the application, the transformation matrix of each size in DCT-II has even-numbered rows and even-numbered rows which are even-symmetric and odd-numbered rows which are odd-symmetric; the transform matrices of each size in DCT-VII and DCT-VIII have the even rows in reverse order, and the odd rows in reverse order and reverse sign.
For example, in the proposed transformation structure, different types of transformation matrices are stored in internal registers. The corresponding transform coefficient can be selected according to the input transform type and transform size. For the transform kernel, two transform matrices of sizes 4 and 8 in the DCT-II transform kernel are shown in fig. 3, where even rows are even symmetric and odd rows are odd symmetric; the first row is row 0; and, the 4 × 4 transform matrix is composed of the first half elements of the even rows of the 8 × 8 matrix. These two features are also present in other sizes of transformation matrices. The DCT-VII transform kernel and the DCT-VIII transform kernel do not have the same butterfly properties as the DCT-II transform kernel.
The transformation matrixes of the DCT-VII transformation core and the DCT-VIII transformation core have very obvious similarity, and the transformation matrixes of the DCT-VII transformation core and the DCT-VIII transformation core have the characteristics of even-numbered row reverse order, odd-numbered row reverse order and reverse sign in numerical value; the first row is row 0. Fig. 4 shows the relationship between two transform matrices of size 4, such a property being present in transform matrices of other sizes as well.
Therefore, all the coefficient matrixes of the DCT-II transformation core can be deduced from the 64 x 64 coefficient matrix, the coefficient matrix of the DCT-VIII transformation core can be deduced from the coefficient matrix of the same-size DCT-VII transformation core, and all types of transformation in the VVC can be satisfied by only storing the 64 x 64 block coefficients in the DCT-II transformation core and the full-size block coefficients in the DCT-VII transformation core.
In the embodiment of the present application, in the calculation module, the matrix coefficients of the selected transform core are multiplied by 16 input transform core data through 32 sets of multiplication units, and each set of multiplication units has 16 general multipliers.
The number of the multiplication units depends on the number of the multiplication units needed when the largest transformation core enters, and the transformation block with the size of 64 of VVC in DCT-II has the characteristic of high-frequency zero setting, so that the result of multiplying the 32 subsequent transformation coefficients by the input data does not need to be calculated, half of the number of multiplication structures can be reduced, and only 32 general multiplication units and a small amount of control logic are needed to realize one-dimensional transformation.
As shown in fig. 5, a single general multiplication unit multiplies 16 input data by 16 transform coefficients, and selects an output according to different transform sizes. When the transformation size is 64, 32 and 16, the output of a single transformation unit is the sum of 16 product terms, when the transformation size is 8, the output of the single transformation unit is the sum of two groups of 8 product terms, and when the transformation size is 4, the output of the single transformation unit is the sum of four groups of 4 product terms.
In the embodiment of the present application, refer to the accumulator shown in fig. 6; the blocks with transform sizes of 16, 8 and 4 can output complete product-sum results after one clock, and the blocks with transform sizes of 64 and 32 can output complete product-sum results after four and two clocks of accumulation respectively.
In the embodiment of the present application, referring to fig. 2, the system further includes: and a parallel-to-serial module 103, configured to delay and output the coding result after the size is transformed.
In the embodiment of the present application, referring to fig. 2, the system further includes: a coefficient scaling module 104, configured to keep the transform coefficient at a preset standard.
Specifically, in order to keep the parallelism of the system at 16, a parallel-serial module is added behind an accumulator, the results of all the transformation sizes are output in a pipelined manner after being delayed by 4 clocks, and then transformation coefficients are kept within 16 bits through a coefficient scaling module.
In the embodiment of the application, an encoding method is also provided. As shown in fig. 7, an encoding method provided in the embodiment of the present application includes:
s11, acquiring data to be processed, and performing code bit estimation on the data to be processed to determine a corresponding transformation matrix;
step S12; obtaining corresponding transformation coefficient according to the transformation type and the transformation size corresponding to the transformation matrix
S13, multiplying the transformation coefficient and the data to be processed by a calculation module to obtain a first result; the computing module comprises a plurality of multiplication units, and each multiplication unit comprises a plurality of general multipliers;
and S14, performing summation operation on the first result by using an accumulator to obtain a coding result.
In an embodiment of the present application, the method further includes: and extracting the transformation coefficient corresponding to the transformation matrix from an internal register based on the transformation type and the transformation size.
Specifically, the above-described encoding method can be applied to the above-described transcoding system. The data to be processed may be continuous frame images in the video. For each image, firstly, code bit estimation is carried out by using each transformation core, and the image is searched by using the transformation matrix of each size corresponding to each type of transformation core, so that the transformation core of the optimal type corresponding to the current frame image and the size of the corresponding transformation matrix are determined according to the calculation result. The code bit estimation can be realized by adopting the prior art, and the process is not repeated in the invention.
After determining the transform type and the transform size, the corresponding transform matrix and the corresponding transform coefficient may be extracted from a preset internal register. For example, the transform coefficients of each type and each size of transform matrix may be pre-calculated and stored in an internal register, so that the encoder can quickly obtain the transform coefficients.
After the transformation coefficients are obtained, the transformation coefficients and the data to be processed can be used for operation in the calculation module. And obtaining a first operation result and inputting the first operation result into the accumulator. Specifically, for a single general multiplication, 16 input data are multiplied by 16 transform coefficients, respectively, and the output is selected according to different transform sizes. When the transformation size is 64, 32 and 16, the output of a single transformation unit is the sum of 16 product terms, when the transformation size is 8, the output of the single transformation unit is the sum of two groups of 8 product terms, and when the transformation size is 4, the output of the single transformation unit is the sum of four groups of 4 product terms.
The accumulator sums the first result input by the calculation module to obtain the coding result. Specifically, the blocks with transform sizes of 16, 8, and 4 can output the complete product-sum result after one clock, while the blocks with transform sizes of 64 and 32 can output the complete product-sum result after four or two clocks of accumulation.
And then, the coding result can be input into a parallel-serial module, in order to keep the parallelism of the system to be 16, the results of all the transformation sizes are output in a pipeline mode after being delayed by 4 clocks, and the transformation coefficients are kept within 16 bits through a coefficient scaling module.
Compared with the traditional scheme that a serial-parallel conversion module is added at the front stage of a one-dimensional conversion module so as to piece together 16 parallelism degrees to 64 parallelism degrees to realize a butterfly-shaped rapid algorithm, the system parallelism degree can be realized to be 16, the input data does not need to be pieced together, an internal calculation module adopts 16 multiplied by 32 general multipliers, conversion matrixes sent into the general multipliers are selected to be multiplied by the input data according to different conversion types and sizes, and results are sent into an accumulator to be summed. The structure of the invention was implemented with Verilog HDL and synthesized using Design Compiler with ASIC 28nm technology. From experimental results, the VVC two-dimensional transformation structure realized based on the unified general multiplier, which is provided by the invention, can be about 30.9% smaller than the traditional scheme in area. Moreover, the structure provided by the invention is superior to the traditional scheme in the aspects of universality and implementation difficulty, and the structure has more advantages in the aspect of realizing various video coding standards.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Further, an embodiment of the present invention provides a computer-readable storage medium, and fig. 8 is a schematic diagram of a computer-readable storage medium provided in an embodiment of the present invention. In particular, a program product is stored thereon which is capable of implementing the above-described method of the present specification. In some possible embodiments, aspects of the invention may also be implemented in the form of a program product comprising program code means for causing a terminal device to carry out the steps according to various exemplary embodiments of the invention described in the above section "exemplary methods" of the present description, when said program product is run on the terminal device.
According to the program product for realizing the method, the portable compact disc read only memory (CD-ROM) can be adopted, the program code is included, and the program product can be operated on terminal equipment, such as a personal computer. However, the program product of the present invention is not limited in this respect, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
A computer readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).
Further, the embodiment of the invention provides an electronic device. Fig. 9 is a schematic view of an electronic device according to an embodiment of the present invention. The electronic device may be used to implement the TDM system reliability evaluation described above. As shown in fig. 9, the electronic device 800 is in the form of a general purpose computing device. The components of the electronic device 800 may include, but are not limited to: the at least one processing unit 810, the at least one memory unit 820, a bus 830 connecting different system components (including the memory unit 820 and the processing unit 810), and a display unit 840.
Wherein the storage unit stores program code that is executable by the processing unit 810 to cause the processing unit 810 to perform steps according to various exemplary embodiments of the present invention as described in the above section "exemplary methods" of the present specification. For example, the processing unit 810 may perform the steps as shown in fig. 7.
The memory unit 820 may include volatile memory units such as a random access memory unit (RAM) 8201 and/or a cache memory unit 8202, and may further include a read only memory unit (ROM) 8203.
The storage unit 820 may also include a program/utility 8204 having a set (at least one) of program modules 8205, such program modules 8205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.
The electronic device 800 may also communicate with one or more external devices 900 (e.g., keyboard, pointing device, bluetooth device, etc.), which may be through an input/output (I/O) interface 850. The electronic device 800 further comprises a display unit 840 connected to the input/output (I/O) interface 850 for displaying. Also, the electronic device 800 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 860. As shown, the network adapter 860 communicates with the other modules of the electronic device 800 via the bus 830. It should be appreciated that although not shown, other hardware and/or software modules may be used in conjunction with the electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A transcoding system, comprising:
the calculation module is used for multiplying the determined transformation coefficient and the data to be processed to obtain a first operation result; the transformation coefficient carries out code bit estimation determination on data to be processed through each transformation core; the calculation module comprises a plurality of multiplication units, and each multiplication unit comprises a plurality of general multipliers;
and the accumulator is used for carrying out summation operation on the first operation result so as to obtain an encoding result.
2. The transcoding system of claim 1, wherein the system further comprises:
and the parallel-serial module is used for delaying and outputting the coding result generated by the accumulator.
3. The transcoding system of claim 1, wherein the system further comprises:
a coefficient scaling module for keeping the transform coefficient at a preset standard.
4. The transcoding system of claim 1 wherein the calculation module comprises 32 multiplication units; each of the multiplication units includes 16 general-purpose multipliers.
5. The transcoding system of claim 1, wherein the system further comprises:
and the internal register is used for storing different types of transformation matrixes.
6. The transcoding system of claim 1 or 5 wherein the DCT-II transform kernel has even-numbered rows and odd-numbered rows of the transform matrix of each size that are even-symmetric and odd-numbered rows;
the even rows of the transformation matrixes of all sizes corresponding to the DCT-VII transformation core and the DCT-VIII transformation core are in reverse order, and the odd rows are in reverse order and in reverse sign.
7. A method of encoding, comprising:
acquiring data to be processed, and performing code bit estimation on the data to be processed to determine a corresponding transformation matrix;
obtaining a corresponding transformation coefficient according to the transformation type and the transformation size corresponding to the transformation matrix;
multiplying the transformation coefficient and the data to be processed by a calculation module to obtain a first result; the computing module comprises a plurality of multiplication units, and each multiplication unit comprises a plurality of general multipliers;
the first result is summed by an accumulator to obtain an encoded result.
8. The encoding method of claim 7, wherein the method further comprises:
and extracting the transformation coefficient corresponding to the transformation matrix from an internal register based on the transformation type and the transformation size.
9. A storage medium, characterized in that a computer program is stored thereon, which program, when being executed by a processor, realizes the encoding method according to any one of claims 7 to 8.
10. An electronic device, comprising:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the encoding method of any of claims 7 to 8 via execution of the executable instructions.
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