CN115865866B

CN115865866B - Address allocation method and device

Info

Publication number: CN115865866B
Application number: CN202211595481.6A
Authority: CN
Inventors: 陈志海
Original assignee: Xiamen Hithium Energy Storage Technology Co Ltd
Current assignee: Xiamen Hithium Energy Storage Technology Co Ltd
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2023-12-22
Anticipated expiration: 2042-12-13
Also published as: CN115865866A

Abstract

The embodiment of the application provides an address allocation method and device, wherein the method comprises the following steps: the main control unit sends a first address allocation instruction on the CAN bus to enable the output end of the main control unit to be in a high level, sends a first communication address to enable an ith-1 slave control unit connected with the output end of the main control unit to receive the first communication address, and then sends the ith address allocation instruction to enable the output end of the ith-1 slave control unit to be in a high level and enable the output end of the control unit connected with the input end of the ith-1 slave control unit to be in a high level, and then sends the ith communication address, and repeats the steps until the output end of the ith-1 slave control unit is directly connected with the main control unit. By adopting the method, the address allocation of the slave control unit can be automatically realized by controlling the input and output voltages of the master control slave control unit.

Description

Address allocation method and device

Technical Field

The present invention relates to the field of communications technologies, and in particular, to an address allocation method and apparatus.

Background

The battery management system (Battery Management System, BMS) mainly comprises a control unit (Battery Control Module, BCM) and a plurality of slave control units (Battery Management Module, BMM), wherein parameter information of single batteries is monitored by each slave control unit and fed back to the master control unit, so that the master control unit monitors the states of the batteries in real time according to the feedback information, and different addresses are required to be allocated to the plurality of slave control units before the slave control units are respectively controlled. The conventional address allocation cannot be compatible with a distributed communication architecture, and manual address allocation needs to be performed on each cluster, so that great workload is required for address allocation.

Disclosure of Invention

The embodiment of the application provides an address allocation method and device, wherein a main control unit sends an address allocation instruction on a CAN bus to control the output ends of a plurality of control units to be in high level or low level, and sends communication addresses on the CAN bus so as to enable the control units meeting the requirements to perform address writing, thereby realizing automatic address allocation on slave control units.

In a first aspect, an embodiment of the present application provides an address allocation method, which is applied to a battery management system, where the battery management system includes a plurality of control units, each of the plurality of control units includes an input end and an output end, the input end and the output end of each control unit are in a low level in an initial state, the input ends and the output ends of the plurality of control units are connected in series through a control hard line, the plurality of control units include a master control unit and M slave control units, and network communication is performed between the master control unit and the M slave control units through a CAN bus, and the method includes:

the method comprises the steps that a main control unit sends a first address allocation instruction on a CAN bus so that the output end of the main control unit is in a high level, wherein the high level refers to the fact that the voltage is in a first preset voltage range, and the low level refers to the fact that the voltage is in a second preset voltage range, and the minimum value in the first preset voltage range is larger than the maximum value in the second preset voltage range;

The method comprises the steps that a main control unit sends a first communication address on a CAN bus, so that an i-1 slave control unit connected with the output end of the main control unit receives the first communication address;

s1, a main control unit sends an ith allocation address instruction on a CAN bus so that the output end of a control unit connected with the input end of an ith slave control unit is low level, and the output end of the ith slave control unit is high level, wherein i is more than or equal to 2 and less than or equal to M+1;

s2, determining whether the output end of the i-1 slave control unit is connected with a master control unit or not;

s3, if the slave unit is not the master unit and is directly connected with the output end of the i-1 slave unit, the master unit sends the i-th communication address on the CAN bus so that the i-th slave unit directly connected with the i-1 slave unit receives the i-th communication address;

and repeating the steps S1 to S3 until the output end of the ith slave control unit is determined to be directly connected with the master control unit.

It CAN be seen that, in this embodiment of the present application, the master control unit sends the first address allocation instruction on the CAN bus, so that the output end of the master control unit is at a high level, and sends the first communication address, so that the ith-1 slave control unit connected to the output end of the master control unit receives the first communication address, and the master control unit resends the ith address allocation instruction, so that the output end of the ith-1 slave control unit is at a high level and the output end of the control unit connected to the input end of the ith-1 slave control unit is at a high level, and the master control unit resends the ith communication address, and repeats this until the output end of the ith-1 slave control unit is directly connected to the master control unit. By adopting the method, the address allocation of the slave control unit can be automatically realized by controlling the input and output voltages of the master control slave control unit.

In a possible embodiment, the master control unit and the plurality of slave control units each include a CAN transceiver interface chip, the CAN transceiver interface chip includes a first port and a second port, the first port and the second port are respectively connected with the physical bus, and at least one resistor is connected between the physical bus connected with the first port and the physical bus connected with the second port.

In the embodiment of the application, at least one resistor is connected between the physical buses respectively connected with the first port and the second port in the CAN transceiver interface chip in the master control unit and the slave control unit, so that the voltage difference between the physical buses respectively connected with the first port and the second port CAN be improved, and the function of stabilizing signals is achieved.

In one possible embodiment, before the master control unit sends the first address allocation instruction on the CAN bus, the method further comprises: the method comprises the steps that a main control unit sends a first instruction on a CAN bus, and receives a first response sent by a slave control unit, wherein the first response is used for indicating that the slave control unit has received the first instruction; the number of received first responses is determined to be M.

In the embodiment of the application, before address allocation is performed, the master control unit sends a first instruction on the CAN bus, receives a first response sent by the slave control unit, and determines that the received first response is M, so that normal network communication between the master control unit and M slave control units CAN be ensured, and subsequent address allocation is facilitated.

In one possible embodiment, after the master control unit sends the first communication address on the CAN bus, the method further comprises: if the master control unit does not receive the second response from the ith slave control unit within the first preset time, the address allocation is finished, and the second response is used for indicating that the ith slave control unit finishes address writing.

In the embodiment of the application, after the master control unit sends the first communication address, if the second response from the i-1 slave control unit is not received within the first preset time, the address allocation is finished, so that the master control unit can be prevented from continuously sending the next address allocation instruction and the communication address when the i-1 slave control unit cannot write the address, and the power consumption of the system is reduced.

In one possible embodiment, after the master control unit sends the first communication address on the CAN bus, the method further comprises: if the master control unit does not receive the second response from the ith slave control unit in the first preset time, determining the position of a fault in a control hard line between M slave control units according to the number of slave control units with address allocation completed in the M slave control units, wherein the second response is used for indicating the ith slave control unit to complete address writing.

In this embodiment of the present application, after the master control unit has sent the first communication address, if the second response from the i-1 th slave control unit is not received within the first preset time, the location where the fault exists in the control hard line between the M slave control units is determined according to the number of slave control units that have completed address allocation. Therefore, the fault position can be directly determined, the maintenance is convenient, and the engineering quantity of system maintenance is reduced.

In a possible embodiment, after determining that the output terminal of the i-1 th slave unit is directly connected to the master unit, the method further includes: determining the number of communication addresses sent by a main control unit on a CAN bus, and calculating a first difference value between the number of communication addresses and the number M; if the first difference is not zero, a first distribution address error report is generated, wherein the first distribution address error report comprises indication information for indicating that the number of the fault slave units is the first difference.

In the embodiment of the application, after determining that the output end of the ith-1 slave control unit is directly connected with the master control unit, determining whether a first difference value between the number of communication addresses sent by the master control unit on the CAN bus and the number M is zero, and if not, generating an allocation address report carrying a first difference value for indicating the number of the fault slave control units. This ensures that after the address assignment has ended, each slave has successfully completed the address assignment.

In a possible embodiment, after the master control unit sends the ith address allocation instruction on the CAN bus, the method further includes:

the main control unit receives a third response aiming at the ith address allocation instruction on the CAN bus, wherein the third response is used for indicating that the ith-1 slave control unit finishes the output end adjustment to be at a high level; if the main control unit does not receive the third response from the ith-1 slave control unit within the second preset time, ending address allocation and generating a second allocation address error report, wherein the second allocation address error report comprises indication information for indicating that the fault slave control unit is the ith-1 slave control unit;

or when i=m+1, if it is determined that the slave unit is not the master unit and is connected to the output end of the i-1 th slave unit, the master unit sends a second instruction on the CAN bus according to the initial address of the slave unit, receives a fourth response of the slave units without the assigned address, determines the positions of the faulty slave units in the M slave units according to the number of the fourth responses, and generates a third assigned address error report, where the third assigned address error report includes indication information for indicating the positions of the faulty slave units;

or when i=m+1, if it is determined that the slave unit connected to the output end of the i-1 th slave unit is not the master unit, the master unit sends a third instruction on the CAN bus according to the allocated address, receives a fifth response of the slave unit corresponding to the allocated address, determines the positions of the faulty slave units in the M slave units according to the number of the fifth responses, and generates a fourth allocation address error report, where the fourth allocation address error report includes indication information for indicating the positions of the faulty slave units.

In this embodiment of the present application, if the output end of the i-1 th slave unit cannot be adjusted to a high level after the master unit sends the i-th address allocation instruction, a third response may be sent to the master unit each time after the output end of the i-1 th slave unit is adjusted to a high level, if the i-1 th slave unit is not received for a long time, the i-1 th slave unit may be considered to have a fault, or in the case of i=m+1, the master unit sends a second instruction according to the initial address, determines the location of the faulty slave unit according to the number of received slave unit responses, or the master unit sends a third instruction according to the sent communication address, and determines the location of the faulty slave unit according to the number of received slave unit responses. By adopting the method, whether the output ends of the slave control units cannot be adjusted to high level in the M slave control units can be determined, so that the system cannot finish address allocation all the time, and the power consumption of the system is reduced.

In a second aspect, an embodiment of the present application provides an address allocation device, applied to a battery management system, where the battery management system includes a plurality of control units, each of the plurality of control units includes an input terminal and an output terminal, the input terminal and the output terminal of each control unit are at a low level in an initial state, the input terminals and the output terminals of the plurality of control units are connected in series through a control hard wire, the plurality of control units include a master control unit and M slave control units, and network communication is performed between the master control unit and the M slave control units through a CAN bus, where the device includes:

The sending unit is used for sending a first address allocation instruction on the CAN bus by the main control unit so as to enable the output end of the main control unit to be in a high level, wherein the high level refers to the voltage size in a first preset voltage range, the low level refers to the voltage size in a second preset voltage range, and the minimum value in the first preset voltage range is larger than the maximum value in the second preset voltage range;

the transmission unit is used for transmitting the first communication address on the CAN bus by the main control unit so that the ith-1 slave control unit connected with the output end of the main control unit receives the first communication address;

the system comprises a transmission unit, a control unit and a slave unit, wherein the transmission unit is also used for transmitting an ith allocation address instruction on a CAN bus by the master unit so that the output end of the control unit connected with the input end of the i-1 slave unit is low level, the output end of the i-1 slave unit is high level, and i is more than or equal to 2 and less than or equal to M+1;

s2, a determining unit, which is used for determining whether the output end of the i-1 slave control unit is connected with the master control unit or not;

s3, a sending unit, which is also used for sending the ith communication address on the CAN bus if the output end of the ith slave control unit is not the master control unit and is directly connected with the output end of the ith slave control unit, so that the ith slave control unit directly connected with the ith slave control unit receives the ith communication address;

And repeating the steps S1 to S3 until the determining unit determines that the output end of the ith-1 slave control unit is directly connected with the master control unit.

In a third aspect, embodiments of the present application provide an electronic device, where the device includes a processor, a memory, and a communication interface, where the processor, the memory, and the communication interface are connected to each other and perform communication therebetween, the memory stores executable program code, the communication interface is configured to perform wireless communication, and the processor is configured to retrieve the executable program code stored in the memory and perform, for example, some or all of the steps described in any of the methods of the first aspect.

In a fourth aspect, an embodiment of the present application provides a battery management system, where the system includes a plurality of control units, each control unit in the plurality of control units includes a low-level input end and an output end, the input ends and the output ends of the plurality of control units are connected in series through a control hard wire, the plurality of control units include a master control unit and M slave control units, network communication is performed between the master control unit and the M slave control units through a CAN bus, and the system implements address allocation for the plurality of slave control units by using the method described in the first aspect of the embodiment of the present application.

In a fifth aspect, embodiments of the present application provide a computer readable storage medium having stored therein program data which, when executed by a processor, is adapted to carry out the program data to carry out some or all of the steps described in the first aspect of the embodiments of the present application.

In a sixth aspect, embodiments of the present application provide a computer program product, wherein the computer program product comprises a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps described in the first aspect of the embodiments of the present application. The computer program product may be a software installation package.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an address allocation system according to an embodiment of the present application;

fig. 2 is a flow chart of an address allocation method according to an embodiment of the present application;

fig. 3 is a flowchart of another address allocation method according to an embodiment of the present application;

FIG. 4a is a functional block diagram of an address assignment device according to an embodiment of the present application;

FIG. 4b is a block diagram illustrating functional units of another address assignment device according to an embodiment of the present application;

fig. 5 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps is not limited to the elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a battery management system according to an embodiment of the present application, as shown in fig. 1, the battery management system includes a master control unit and M slave control units, where the master control unit and the M slave control units include an output end and an input end, and the input ends and the output ends of the master control unit and the M slave control units are connected in series through a control hard wire 102, and network communication is performed between the master control unit and the M slave control units through a controller area network (Controller Area Network, CAN) bus 101.

A CAN transceiver interface chip is arranged in the master control unit and the M slave control units, each CAN transceiver interface chip is provided with two ports, namely CANH and CANL, the state of the CANH end CAN only be high level or suspension state, and the CANL end CAN only be low level or suspension state, so that the phenomenon that when a system error exists, when multiple nodes CAN not send data to a bus at the same time, the bus is short-circuited to damage some nodes is ensured, each CAN node has an automatic port closing function under the condition that the error is serious, the operation of other nodes on the bus is not influenced, the situation that the operation of the other nodes on the bus is not influenced is ensured, the problem occurs like in a network due to the fact that the individual nodes, the bus is in a 'dead lock' state, and at least one resistor is connected in series between the physical buses connected with the CANH and the CANL ports is ensured.

Based on this, the embodiment of the application provides an address allocation method, and the embodiment of the application is described in detail below with reference to the accompanying drawings.

Referring to fig. 2, fig. 2 is a flow chart of an address allocation method provided in an embodiment of the present application, where the address allocation method is applied to the battery management system shown in fig. 1, the battery management system includes a plurality of control units, each of the plurality of control units includes an input end and an output end, the input end and the output end of each control unit are at a low level in an initial state, the input ends and the output ends of the plurality of control units are connected in series through a control hard line, the plurality of control units include a master control unit and M slave control units, and network communication is performed between the master control unit and the M slave control units through a CAN bus, as shown in fig. 2, the method includes the following steps:

step 201, the main control unit sends a first address allocation instruction on the CAN bus, so that the output end of the main control unit is at a high level.

The low level and the high level refer to digital logic, which can be represented by 0 and 1, but are determined according to the voltage in terms of processing, i.e. the high level refers to the voltage magnitude being in a first preset voltage range, and the low level refers to the voltage magnitude being in a second preset voltage range, and the minimum value in the first preset voltage range is larger than the maximum value in the second preset voltage range. Illustratively, the voltage at the port is between 0 and 3V, showing a low level, and the voltage at the port is between 4 and 7V, showing a high level.

In the battery management system, after the initial installation of the battery management system is successful, there are a master control unit and M slave control units, and at this time, all of the M slave control units are in network communication with the master control unit by one communication address, so that the master control unit cannot respectively communicate with the M slave control units, and at this time, it is required to allocate respectively different addresses to the M slave control units so that the master control units respectively communicate with the M slave control units. Therefore, in the initial state, the master control unit sends a first address allocation instruction on the CAN bus according to the initial addresses of the M slave control units, and after the M slave control units receive the first address allocation instruction on the CAN bus, the master control unit is ready to perform address allocation, and at the moment, the output end of the master control unit is adjusted to be in a high level.

The CAN transceiver interface chip is arranged in each control unit so that each control unit CAN carry out network communication through a CAN bus, and the first port and the second port respectively correspond to a high level and a low level.

Before address allocation is performed, a first instruction CAN be sent by the master control unit on the CAN bus according to initial addresses of the M slave control units, so that the M slave control units reply first responses on the CAN bus, the master control unit receives the first responses from the M slave control units through the CAN bus, and if the number of the first responses is M, it CAN be determined that network communication between the master control unit and the M slave control units is normal.

Step 202, the master control unit sends a first communication address on the CAN bus, so that the i-1 slave control unit connected to the output terminal of the master control unit receives the first communication address.

After the output end of the master control unit is adjusted to be at a high level, the input end of the i-1 slave control unit connected with the output end of the master control unit is also affected by the high level of the output end of the master control unit, so that the input end of the i-1 slave control unit is also changed to be at a high level, after the master control unit sends a first communication address on the CAN bus, M slave control units all recognize the first communication address, but only the slave control unit with the high level input end CAN complete writing of the first communication address, namely, the i-1 slave control unit connected with the output end of the master control unit CAN complete writing of the first communication address.

After the master control unit finishes sending the first communication address, the i-1 slave control unit sends a second response on the CAN bus after finishing address writing, when the master control unit receives the second response, the i-1 slave control unit finishes address allocation, but if the master control unit does not receive the second response within the first preset time, the i-1 slave control unit does not write an address, which means that the system has a fault, the address allocation is ended. It will be appreciated that the present implementation is applicable to the entire address assignment flow, i.e. as soon as any one of the M slave units has completed address writing, a second response is sent on the CAN bus.

Wherein, as in the above embodiment, after the master control unit sends the first communication address on the CAN bus, if the second response from the i-1 th slave control unit is not received within the first preset time, the location where the fault exists in the control hard line between the M slave control units may be determined according to the number of slave control units for which the address allocation has been completed in the M slave control units, in addition to ending the address allocation. For example, if the address allocation of the two slave units has been completed at this time, the location where the fault exists is a control hard line between the second slave unit and the third slave unit, which may be that the line is disconnected, so that the output terminal of the second slave unit cannot be connected to the input terminal of the third slave unit, and in the case that the output terminal of the second slave unit is at a high level, the input terminal of the third slave unit cannot be displayed at a high level, and thus the address writing cannot be completed.

In step 203, the master control unit sends an i-th address allocation instruction on the CAN bus, so that the output end of the control unit connected to the input end of the i-1-th slave control unit is at a low level and the output end of the i-1-th slave control unit is at a high level.

Wherein i is more than or equal to 2 and less than or equal to M+1. Starting from the second address allocation instruction, in addition to the output of the i-1 th slave unit being adjusted to a high level, the output of the control unit connected to the input of the i-1 th slave unit is also adjusted to a low level, i.e. if i=2, the control unit connected to the input of the first slave unit is the master unit, i=3, and the control unit connected to the output of the second slave unit is the first slave unit. This is to ensure that only one slave unit has its input terminal shown high during one address allocation, so that only one slave unit can write the address, thereby achieving the purpose of allocating a different address to each slave unit.

Step 204, determining whether the output end of the i-1 slave control unit is connected with the master control unit.

One condition for ending the address allocation in this embodiment is whether the output terminal of the i-1 slave unit is connected to the master unit, and if the output terminal of the i-1 slave unit is connected to the master unit, the input terminal of the master unit is displayed as high level because the output terminal of the i-1 slave unit is at high level, so that the master unit ends the address allocation if judging that the input terminal of the master unit is at high level.

In step 205, if the slave unit is not the master unit and is directly connected to the output terminal of the i-1 slave unit, the master unit sends the i-th communication address on the CAN bus, so that the i-th slave unit directly connected to the i-1 slave unit receives the i-th communication address.

If the output end of the i-1 slave control unit is not directly connected with the master control unit, that is, the input end of the master control unit is not displayed as high level, the master control unit will continue to allocate addresses.

And repeating the steps 203 to 205 until the output end of the ith-1 slave control unit is determined to be directly connected with the master control unit, and ending address allocation.

The sequence of address allocation for the slave units is determined according to the sequence when the slave units are connected in series with the output end of the master unit, as shown in fig. 1, the first slave unit is connected with the output end of the master unit recently, and under the condition that the first slave unit equipment is normal, the first slave unit is the slave unit performing the first address allocation, the second slave unit performs the address allocation after the first slave unit completes the address allocation, until the mth slave unit completes the address allocation, at this time, the output end of the mth slave unit is adjusted to be at a high level, and then the input end of the master unit is also displayed to be at a high level.

After determining that the output end of the i-1 slave control unit is directly connected with the master control unit, the master control unit finishes address allocation, and if the slave control units in the M slave control units have faults to cause short circuit, the number of the addresses allocated by the master control unit is different from the number M of the slave control units. In an exemplary embodiment, the second slave unit has a short-circuit fault, and the output end of the first slave unit is connected to the input end of the second slave unit, but because the second slave unit has a short-circuit fault, the input end of the third slave unit connected to the output end of the second slave unit is directly connected to the output end of the first slave unit, and when an address is allocated, the second slave unit cannot participate in address allocation due to the fault, but does not affect the display of the input end of the final master unit to be high.

Therefore, after the address allocation is finished, the number of the slave units with faults in the M slave units is determined according to the difference value between the number of the communication addresses sent by the master and the number M of the slave units in the address allocation process.

After the master control unit sends the ith address allocation instruction, the output end of the ith slave control unit needs to be adjusted to be at a high level, but if the output end of the ith slave control unit cannot be adjusted to be at the high level at this time, the input end of the ith slave control unit cannot be displayed to be at the high level, and after the master control unit sends the ith communication address, the ith slave control unit does not write the ith communication address. For this case, there are three ways to identify this in the present embodiment.

The first mode is that after the main control unit sends the ith address allocation instruction, when the output end of the ith slave control unit is adjusted to be at a high level, the ith slave control unit sends a third response for indicating that the ith slave control unit has completed the adjustment of the output end to be at the high level, and if the main control unit does not receive the third response within a second preset time, the ith slave control unit can be judged to have faults.

In the second mode, when i=m+1, that is, the m+1-th allocation address instruction sent by the master control unit, if the whole allocation address flow is normal, the m+1-th allocation address instruction corresponds to the M-th slave control unit, but there are only M slave control units, that is, the M-th slave control unit is connected to the output end of the master control unit, and if the input end of the master control unit is not displayed at the high level, it is indicated that the i-1-th slave control unit is not connected to the output end of the master control unit, and then it can be determined that one slave control unit has the fault. The master control unit sends a second instruction on the CAN bus according to the initial address so as to enable the slave control units with unassigned addresses to respond, and determines the position of the failed slave control unit according to the difference between the total number M of the slave control units and the number of the slave control units with unassigned addresses. For example, if the number of responses of slave units to which no address is assigned is 3 and M is 5, the location of the failed slave unit is the second slave unit connected at the output of the master unit.

The third mode is also that after determining that the slave unit has a fault according to i=m+1 in the second mode, the master unit transmits a third instruction on the CAN bus according to the communication address which has been transmitted on the CAN bus, so that the slave unit with the assigned address responds, and determines the position of the faulty slave unit according to the number of responses of the slave units with the assigned address. For example, if the number of responses of the slave units to which addresses have been assigned is 3, the location of the failed slave unit is the third slave unit connected at the output of the master unit.

In addition, there may be a case where after the master unit transmits the i-th address assignment command, the output end of the control unit connected to the input end of the i-1 th slave unit cannot be adjusted to a low level, which may cause the input end of the i-1 th slave unit to be continuously at a high level, and if the output end of the i-1 th slave unit shown in the above embodiment cannot be adjusted to a high level, it may be determined whether there is such a fault based on the third mode described above, that is, after the master unit transmits the third command on the CAN bus according to the communication address that has been transmitted on the CAN bus, according to the communication address corresponding to the received response of the slave unit if it is required to determine such a fault at the time of address assignment. For example, if the transmitted addresses include 1, 2 and 3, after the master unit transmits the third instruction on the CAN bus according to the three communication addresses, if the communication address corresponding to the received response includes 1 and 3, it may be determined that there are two faults that the output terminal of the control unit connected to the input terminal of the i-1 th slave unit cannot be adjusted to the low level and the output terminal of the i-1 th slave unit cannot be adjusted to the high level.

Referring to fig. 3, fig. 3 is a flowchart illustrating another address allocation method according to an embodiment of the present application. As shown in fig. 3, after the address allocation is started, the master control unit sends a first address allocation command to enable all the slave control unit output ends to be low level and all the master control unit output ends to be high level, when the address allocation is performed, the master control unit sends a communication address X, judges whether the slave control unit X input end is high level, if the slave control unit X input end is high level, the address X is written, then the master control unit responds to the configuration result, namely, whether the address X is written, if the slave control unit X does not complete address writing, the address allocation is finished, if the slave control unit X completes address writing, the master control unit sends an i-th address allocation command, judges whether i is 2, if i is 2, the master control unit output end is adjusted to be low level, and if i is not 2, the slave control unit X-1 output end is adjusted to be low level, if i is not 2, and judges whether the master control unit input end is high level, if the master control unit input end is high level, the address allocation is finished, if the master control unit X input end is not high level, and if the master control unit X is not high level, the communication step is repeated until the master control unit input is high level.

In accordance with the above-described embodiment, referring to fig. 4a, fig. 4a is a functional block diagram of an address allocation device according to an embodiment of the present application, where the device is applied to the battery management system shown in fig. 1, and as shown in fig. 4a, the address allocation device 40 includes:

a sending unit 401, configured to send a first address allocation instruction by using a master control unit on a CAN bus, so that an output end of the master control unit is at a high level, where the high level indicates that the voltage is in a first preset voltage range, and the low level indicates that the voltage is in a second preset voltage range, and a minimum value in the first preset voltage range is greater than a maximum value in the second preset voltage range;

The sending unit 401 is further configured to send, by the master control unit, the first communication address on the CAN bus, so that the i-1 th slave control unit connected to the output end of the master control unit receives the first communication address;

the S1 is a transmitting unit 401, and is further used for transmitting an ith allocation address instruction on the CAN bus by the main control unit, so that the output end of the control unit connected with the input end of the ith-1 slave control unit is low level, the output end of the ith-1 slave control unit is high level, and i is more than or equal to 2 and less than or equal to M+1;

s2, a determining unit 402, configured to determine whether the output end of the i-1 th slave control unit is connected to a master control unit;

s3, a sending unit 401, which is further used for sending the ith communication address on the CAN bus if the output end of the ith slave control unit is not the master control unit and is directly connected with the output end of the ith slave control unit, so that the ith slave control unit directly connected with the ith slave control unit receives the ith communication address;

s1 to S3 are repeated until the determining unit 402 determines that the output end of the i-1 th slave unit is directly connected to the master unit.

In a possible embodiment, before the sending unit 401 is configured to send the first address allocation instruction on the CAN bus by the master unit, the method further includes: the main control unit sends a first instruction on the CAN bus, and receives a first response sent by the slave control unit through the receiving unit 403, wherein the first response is used for indicating that the slave control unit has received the first instruction; the number of received first responses is determined to be M by the determination unit 402.

In a possible embodiment, after the sending unit 401 is configured to send the first communication address on the CAN bus by the master unit, the method further includes: if the master control unit does not receive the second response from the i-1 th slave control unit within the first preset time through the receiving unit 403, the address allocation is finished, and the second response is used for indicating that the i-1 th slave control unit has completed address writing.

In a possible embodiment, after the sending unit 401 is configured to send the first communication address on the CAN bus by the master unit, the method further includes: if the master unit does not receive the second response from the i-1 th slave unit within the first preset time through the receiving unit 403, the determining unit 402 determines a location where a fault exists in the control hard line between the M slave units according to the number of slave units for which address allocation has been completed in the M slave units, where the second response is used to indicate that the i-1 th slave unit has completed address writing.

In a possible embodiment, after the determining unit 402 determines that the output terminal of the i-1 th slave unit is directly connected to the master unit, the determining unit is further configured to: determining the number of communication addresses sent by a main control unit on a CAN bus, and calculating a first difference value between the number of communication addresses and the number M; if the first difference is not zero, a first allocation address error report is generated by the generating unit 404, where the first allocation address error report includes indication information for indicating that the number of faulty slave units is the first difference.

In a possible embodiment, after the sending unit 401 is configured to send the ith address allocation instruction on the CAN bus by the master unit, the method further includes:

the main control unit receives a third response to the ith allocation address instruction on the CAN bus through the receiving unit 403, wherein the third response is used for indicating that the ith-1 slave control unit finishes the output end adjustment to be at a high level; if the master control unit does not receive the third response from the ith-1 slave control unit within the second preset time, ending address allocation, and generating a second allocation address error report by the generating unit 404, wherein the second allocation address error report comprises indication information for indicating that the fault slave control unit is the ith-1 slave control unit;

Or when i=m+1, if the determining unit 402 determines that the slave unit connected to the output end of the i-1 th slave unit is not the master unit, the sending unit 401 is configured to send a second instruction on the CAN bus by using the master unit according to the initial address of the slave unit, receive a fourth response of the slave unit with no address allocated by using the receiving unit 403, determine the positions of the failed slave units in the M slave units according to the number of the fourth responses, and generate a third allocation address error report by using the generating unit 404, where the third allocation address error report includes indication information for indicating the positions of the failed slave units;

or when i=m+1, if the determining unit 402 determines that the slave unit connected to the output terminal of the i-1 th slave unit is not the master unit, the sending unit 401 is configured to send a third instruction on the CAN bus by using the master unit according to the allocated address, receive, by using the receiving unit 403, a fifth response of the slave unit corresponding to the allocated address, the determining unit 402 determines, by using the number of the fifth responses, a location of a faulty slave unit in the M slave units, and generate, by using the generating unit 404, a fourth allocation address error report, where the fourth allocation address error report includes indication information for indicating the location of the faulty slave unit.

It can be understood that, since the method embodiment and the apparatus embodiment are in different presentation forms of the same technical concept, the content of the method embodiment portion in the present application should be adapted to the apparatus embodiment portion synchronously, which is not described herein.

In the case of using integrated units, as shown in fig. 4b, fig. 4b is a functional unit block diagram of another address allocation device according to an embodiment of the present application. In fig. 4b, the address allocation means 41 comprises: a processing module 412 and a communication module 411. The processing module 412 is used for controlling and managing the actions of the address allocation device, e.g. the steps of the sending unit 401, the determining unit 402, the receiving unit 403 and the generating unit 404, and/or for performing other processes of the techniques described herein. The communication module 411 is used to support interaction between the address allocation apparatus and other devices. As shown in fig. 4b, the address allocation device 41 may further comprise a memory module 413, the memory module 413 being adapted to store program code and data of the address allocation device.

The processing module 412 may be a processor or controller, such as a central processing unit (Central Processing Unit, CPU), a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an ASIC, an FPGA or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. A processor may also be a combination that performs computing functions, e.g., including one or more microprocessors, a combination of a DSP and a microprocessor, and so forth. The communication module 411 may be a transceiver, an RF circuit, or a communication interface, etc. The memory module 413 may be a memory.

All relevant contents of each scenario related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein. The address allocation device 41 may perform the address allocation method shown in fig. 2.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions in accordance with the embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired or wireless means from one website site, computer, server, or data center. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk.

Fig. 5 is a block diagram of an electronic device according to an embodiment of the present application. As shown in fig. 5, the electronic device 500 may include one or more of the following components: a processor 501, a memory 502 coupled to the processor 501, wherein the memory 502 may store one or more computer programs that may be configured to implement the methods as described in the embodiments above when executed by the one or more processors 501. The electronic device 500 may be the master control unit or the slave control unit.

The processor 501 may include one or more processing cores. The processor 501 utilizes various interfaces and lines to connect various portions of the overall electronic device 500, perform various functions of the electronic device 500, and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 502, and invoking data stored in the memory 502. Alternatively, the processor 501 may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field-Programmable gate array (FPGA), programmable Logic Array (PLA). The processor 501 may integrate one or a combination of several of a central processing unit (CentralProcessing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a passenger interface, an application program and the like; the GPU is used for being responsible for rendering and drawing of display content; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 501 and may be implemented solely by a single communication chip.

The Memory 502 may include a random access Memory (Random Access Memory, RAM) or a Read-Only Memory (ROM). Memory 502 may be used to store instructions, programs, code sets, or instruction sets. The memory 502 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like. The storage data area may also store data created by the electronic device 500 in use, and the like.

It is to be appreciated that electronic device 500 may include more or fewer structural elements than those described in the above-described block diagrams, including, for example, a power module, physical key, wiFi (Wireless Fidelity ) module, speaker, bluetooth module, sensor, etc., without limitation.

An embodiment of the present application provides a computer readable storage medium, where the computer readable storage medium stores program data that, when executed by a processor, is configured to perform part or all of the steps of any one of the address allocation methods described in the above method embodiments.

The present application also provides a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform part or all of the steps of any one of the address allocation methods described in the method embodiments above. The computer program product may be a software installation package, said computer comprising a receiving side and/or a transmitting side.

It should be noted that, for simplicity of description, the method embodiments of any one of the address allocation methods described above are all described as a series of combinations of actions, but those skilled in the art should appreciate that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously according to the present application. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments and that the acts referred to are not necessarily required in the present application.

Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various method embodiments of any of the address assignment methods described above may be performed by a program that instructs associated hardware, and that the program may be stored in a computer readable memory, which may include: flash disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.

The foregoing has described embodiments of the present application in detail, and specific examples have been used herein to illustrate the principles and embodiments of a method and apparatus for address allocation, where the foregoing embodiments are merely for aiding in understanding of the method and core idea of the present application; meanwhile, as for those skilled in the art, according to the idea of an address allocation method and apparatus of the present application, there are various changes in the specific embodiments and application scope, and in summary, the present disclosure should not be construed as limiting the present application.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, hardware products, and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be appreciated that any product of the processing method of the flowcharts described in connection with the method embodiments of the address assignment method of the present application, such as the terminals of the flowcharts described above and the computer program products, falls within the scope of the relevant product(s) described in the present application.

It will be apparent to those skilled in the art that various modifications and variations can be made in the address assignment method and apparatus provided herein without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. An address allocation method, applied to a battery management system, wherein the battery management system includes a plurality of control units, each control unit of the plurality of control units includes an input terminal and an output terminal, the input terminal and the output terminal of each control unit are at a low level in an initial state, the input terminal and the output terminal of the plurality of control units are connected in series through a control hard wire, and the plurality of control units include a master control unit and M slave control units, and network communication is performed between the master control unit and the M slave control units through a CAN bus, the method includes:

the main control unit sends a first address allocation instruction on the CAN bus so that the output end of the main control unit is in a high level, wherein the high level refers to the voltage magnitude in a first preset voltage range, the low level refers to the voltage magnitude in a second preset voltage range, and the minimum value in the first preset voltage range is larger than the maximum value in the second preset voltage range;

The main control unit sends a first communication address on the CAN bus so that an ith-1 slave control unit connected with the output end of the main control unit receives the first communication address;

s1, the main control unit sends an ith allocation address instruction on the CAN bus so that the output end of a control unit connected with the input end of the ith-1 slave control unit is low level, and the output end of the ith-1 slave control unit is high level, wherein i is more than or equal to 2 and less than or equal to M+1;

s2, determining whether the output end of the ith-1 slave control unit is connected with the master control unit or not;

s3, if the output end of the ith slave control unit is not the master control unit, the master control unit sends an ith communication address on the CAN bus so that the ith slave control unit directly connected with the ith-1 slave control unit receives the ith communication address;

repeating S1-S3 until the fact that the output end of the ith-1 slave control unit is directly connected with the master control unit is determined;

after the main control unit sends the ith address allocation instruction on the CAN bus, the method further comprises:

when the i=m+1, if it is determined that the slave unit connected to the output end of the i-1 slave unit is not the master unit, the master unit sends a third instruction on the CAN bus according to the allocated address, and receives a fifth response of the slave unit corresponding to the allocated address;

When the communication address corresponding to the fifth response has continuity corresponding to the address allocation sequence, determining the positions of the faulty slave units in the M slave units according to the number of the fifth responses;

when the communication address corresponding to the fifth response does not have continuity corresponding to the address allocation sequence, comparing the communication address corresponding to the fifth response with a target continuous address, determining that the communication address corresponding to the fifth response has a missing target communication address in the target continuous address, determining the positions of the faulty slave units in the M slave units according to the missing target communication address, wherein the target continuous address is a communication address with continuity determined by taking a first communication address starting point and a communication address with the last allocation sequence in the communication address corresponding to the fifth response as an end point, and at this time, determining that the output end of a control unit connected with the input end of the faulty slave unit cannot be adjusted to be low level and the output end of the faulty slave unit cannot be adjusted to be high level;

a fourth assigned address error report is generated, the fourth assigned address error report including indication information for indicating the location of the faulty slave unit.

2. The method of claim 1, wherein each of the master unit and the plurality of slave units includes a CAN transceiver interface chip, the CAN transceiver interface chip including a first port and a second port, the first port and the second port being respectively connected to physical buses, wherein at least one resistor is connected between the physical buses to which the first port is connected and the physical buses to which the second port is connected.

3. The method according to claim 1 or 2, characterized in that before the master unit sends a first allocation address instruction on the CAN bus, the method further comprises:

the main control unit sends a first instruction on the CAN bus and receives a first response sent by the slave control unit, wherein the first response is used for indicating the slave control unit to have received the first instruction;

the number of received first responses is determined to be M.

4. The method of claim 3, wherein after the master unit transmits the first communication address on the CAN bus, the method further comprises:

and if the master control unit does not receive a second response from the ith slave control unit within a first preset time, ending address allocation, wherein the second response is used for indicating that the ith slave control unit finishes address writing.

5. The method of claim 3 or 4, wherein after the master unit transmits a first communication address on the CAN bus, the method further comprises:

if the master control unit does not receive a second response from the ith slave control unit within a first preset time, determining a position where a fault exists in a control hard wire between the M slave control units according to the number of slave control units with address allocation completed in the M slave control units, wherein the second response is used for indicating that the ith slave control unit has completed address writing.

6. The method of claim 1, wherein after determining that the output of the i-1 th slave unit is directly connected to the master unit, the method further comprises:

determining the number of communication addresses sent by the main control unit on the CAN bus, and calculating a first difference value between the number of the communication addresses and the number M;

and if the first difference value is not zero, generating a first distribution address error report, wherein the first distribution address error report comprises indication information for indicating that the number of the fault slave units is the first difference value.

7. The method of claim 1, wherein after the master unit sends an i-th address allocation instruction on the CAN bus, the method further comprises:

The main control unit receives a third response to the ith allocation address instruction on the CAN bus, wherein the third response is used for indicating that the ith-1 slave control unit finishes output end adjustment to be high level;

if the master control unit does not receive the third response from the ith slave control unit within the second preset time, ending address allocation and generating a second allocation address error report, wherein the second allocation address error report comprises indication information for indicating that the fault slave control unit is the ith-1 slave control unit; or (b)

When i=m+1, if it is determined that the slave unit is not the master unit and is connected to the output end of the i-1 th slave unit, the master unit sends a second instruction on the CAN bus according to the initial address of the slave unit, receives a fourth response of the slave units without address allocation, determines the positions of the faulty slave units in the M slave units according to the number of the fourth responses, and generates a third allocation address error report, where the third allocation address error report includes indication information for indicating the positions of the faulty slave units.

8. An address allocation apparatus, characterized in that it is applied to a battery management system, the battery management system includes a plurality of control units, each control unit of the plurality of control units includes an input terminal and an output terminal, the input terminal and the output terminal of each control unit are at a low level in an initial state, the input terminal and the output terminal of the plurality of control units are connected in series through a control hard wire, and the plurality of control units include a master control unit and M slave control units, and network communication is performed between the master control unit and the M slave control units through a CAN bus, the apparatus includes:

The sending unit is used for sending a first address allocation instruction on the CAN bus by the main control unit so as to enable the output end of the main control unit to be in a high level, wherein the high level refers to that the voltage is in a first preset voltage range, the low level refers to that the voltage is in a second preset voltage range, and the minimum value in the first preset voltage range is larger than the maximum value in the second preset voltage range;

the sending unit is further configured to send a first communication address to the main control unit on the CAN bus, so that an i-1 th slave control unit connected to an output end of the main control unit receives the first communication address;

the system comprises a transmission unit, a control unit and a control unit, wherein the transmission unit is also used for transmitting an ith allocation address instruction on the CAN bus by the main control unit so that the output end of the control unit connected with the input end of the ith-1 slave control unit is in a low level, and the output end of the ith-1 slave control unit is in a high level, wherein i is more than or equal to 2 and less than or equal to M+1;

s3, the sending unit is further used for sending an ith communication address on the CAN bus if the output end of the ith slave control unit is not the master control unit and is directly connected with the output end of the ith slave control unit, so that the ith slave control unit directly connected with the ith slave control unit receives the ith communication address;

Repeating S1-S3 until the determining unit determines that the output end of the i-1 slave control unit is directly connected with the master control unit;

after the main control unit sends the ith address allocation instruction on the CAN bus according to the sending unit, the device further comprises:

9. An electronic device, the device comprising:

the device comprises a processor, a memory and a communication interface, wherein the processor, the memory and the communication interface are mutually connected and complete communication work among each other;

the memory stores executable program codes, and the communication interface is used for wireless communication;

the processor is configured to invoke the executable program code stored on the memory to perform the method of any of claims 1-7.

10. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any one of claims 1-7.