CN115865783B - Method and device for determining target node and computer readable storage medium - Google Patents
Method and device for determining target node and computer readable storage medium Download PDFInfo
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Abstract
The application provides a method and a device for determining a target node and a computer readable storage medium, relates to the field of communication, and can reduce the calculated amount when determining a target source node and a target destination node and improve the efficiency. The method comprises the following steps: acquiring a first node topological graph; the first node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes and a plurality of destination nodes, and a second node topological graph is determined according to the first node topological graph; the second node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes, a plurality of destination nodes, source machine room nodes and destination machine room nodes, wherein the source machine room nodes are respectively connected with each source node, the destination machine room nodes are respectively connected with each destination node, and a destination path between the source machine room nodes and the destination machine room nodes is determined according to the second node topological graph and a destination path algorithm; and taking the second node on the target path as a target source node and the penultimate node on the target path as a target destination node.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method and apparatus for determining a target node, and a computer readable storage medium.
Background
In a single machine room there may be multiple nodes of the same communication network. Fig. 1 is a schematic diagram of a single-machine room multi-node provided in the present application, as shown in fig. 1, 3 nodes exist in a machine room a, which are respectively node 1, node 2 and node 3. In general, a communication network corresponding to a source computer room and a communication network corresponding to a destination computer room need to communicate through an optimal path, and the premise of determining the shortest path is to determine a target source node and a target destination node first, and then determine the optimal path between the target source node and the target destination node.
In order to determine target source nodes in a source machine room and target destination nodes in a destination machine room, the existing scheme is to respectively determine a plurality of paths between each source node of the source machine room and each destination node of the destination machine room through a shortest path algorithm, then select an optimal path from a plurality of communication paths, and take nodes at two ends of the optimal path as the target source nodes and the target destination nodes.
Because a plurality of paths need to be determined, the calculation amount is large and the efficiency is low when the target source node and the target destination node are determined by the scheme.
Disclosure of Invention
The application provides a method and a device for determining a target node and a computer readable storage medium, which can reduce the calculated amount when determining a target source node and a target destination node and improve the efficiency.
In order to achieve the above purpose, the present application adopts the following technical scheme:
in a first aspect, a method for determining a target node is provided, where the method includes: acquiring a first node topological graph; the first node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes and a plurality of sink nodes, wherein the source nodes are positioned in a source machine room, and the sink nodes are positioned in a sink machine room; determining a second node topology according to the first node topology; the second node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes, a plurality of destination nodes, source machine room nodes and destination machine room nodes, wherein the source machine room nodes are respectively connected with each source node, the destination machine room nodes are respectively connected with each destination node, the connection weight of the source machine room nodes and each source node is a preset weight, and the connection weight of the destination machine room nodes and each destination node is a preset weight; determining a target path between the source machine room node and the sink machine room node according to the second node topological graph and the target path algorithm; and taking the second node on the target path as a target source node and the penultimate node on the target path as a target destination node.
Based on the scheme, the second node topological graph is determined according to the first node topological graph, the target path between the source machine room node and the sink machine room node is determined according to the second node topological graph, the second node and the penultimate node of the target path are determined as target nodes, and as the connection weight of the source machine room node and each source node is the same, the connection weight of the sink machine room node and each sink node is the same, and therefore after the target path between the source machine room node and the sink machine room node is obtained, the corresponding target source node and the target sink node can be determined. Compared with the existing scheme requiring determination of multiple paths, the scheme can determine the target source node and the target destination node only by determining the target path between the source computer room node and the destination computer room node, and the multiple paths are not required to be determined, so that the calculation amount for determining the target source node and the target destination node can be reduced, and the efficiency is improved.
With reference to the first aspect, in certain implementation manners of the first aspect, determining the second node topology according to the first node topology specifically includes: determining source machine room nodes according to the source machine room and determining sink machine room nodes according to the sink machine room; and connecting the source machine room node with each source node in the first node topological graph respectively, and connecting the sink machine room node with each sink node in the first node topological graph respectively to obtain a second node topological graph.
Based on this scheme, a scheme of determining the second node topology from the first node topology can be implemented.
With reference to the first aspect, in some implementations of the first aspect, the target path algorithm is a delay minimum path algorithm, and determining, according to the second node topology graph and the target path algorithm, a target path between a source computer room node and a destination computer room node specifically includes: obtaining time delay between connected nodes in the second node topological graph; and inputting the time delay between the connected nodes in the second node topological graph and the second node topological graph into a time delay minimum path algorithm to obtain a time delay minimum path between the source machine room node and the sink machine room node.
Based on the scheme, the scheme of determining the target path between the source machine room node and the sink machine room node according to the second node topological graph and the target path algorithm can be realized.
With reference to the first aspect, in some implementations of the first aspect, the target path algorithm is a hop-count minimum path algorithm, and determining, according to the second node topology graph and the target path algorithm, a target path between a source computer room node and a destination computer room node specifically includes: and inputting the second node topological graph into a path algorithm with the minimum hop count to obtain a path with the minimum hop count between the source machine room node and the sink machine room node.
Based on the scheme, the scheme of determining the target path between the source machine room node and the sink machine room node according to the second node topological graph and the target path algorithm can be realized.
In a second aspect, a determining device of a target node is provided for implementing the determining method of the target node in the first aspect. The determining device of the target node comprises a corresponding module, unit or means (means) for implementing the method, wherein the module, unit or means can be implemented by hardware, software or implemented by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the functions described above.
With reference to the second aspect, in certain embodiments of the second aspect, the determining device of the target node includes: the device comprises an acquisition module and a processing module; the acquisition module is used for acquiring a first node topological graph; the first node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes and a plurality of sink nodes, wherein the source nodes are positioned in a source machine room, and the sink nodes are positioned in a sink machine room; the processing module is used for determining a second node topological graph according to the first node topological graph; the second node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes, a plurality of destination nodes, source machine room nodes and destination machine room nodes, wherein the source machine room nodes are respectively connected with each source node, the destination machine room nodes are respectively connected with each destination node, the connection weight of the source machine room nodes and each source node is a preset weight, and the connection weight of the destination machine room nodes and each destination node is a preset weight; the processing module is also used for determining a target path between the source machine room node and the sink machine room node according to the second node topological graph and the target path algorithm; and the processing module is also used for taking the second node on the target path as a target source node and the penultimate node on the target path as a target destination node.
With reference to the second aspect, in some implementations of the second aspect, the processing module is further configured to determine a second node topology map according to the first node topology map, and specifically includes: determining source machine room nodes according to the source machine room and determining sink machine room nodes according to the sink machine room; and connecting the source machine room node with each source node in the first node topological graph respectively, and connecting the sink machine room node with each sink node in the first node topological graph respectively to obtain a second node topological graph.
With reference to the second aspect, in some implementations of the second aspect, the target path algorithm is a delay minimum path algorithm, and the processing module is further configured to determine, according to the second node topology map and the target path algorithm, a target path between the source computer room node and the sink computer room node, including: obtaining time delay between connected nodes in the second node topological graph; and inputting the time delay between the connected nodes in the second node topological graph and the second node topological graph into a time delay minimum path algorithm to obtain a time delay minimum path between the source machine room node and the sink machine room node.
With reference to the second aspect, in some implementations of the second aspect, the target path algorithm is a hop-count minimum path algorithm, and the processing module is further configured to determine, according to the second node topology map and the target path algorithm, a target path between a source machine room node and a sink machine room node, including: and inputting the second node topological graph into a path algorithm with the minimum hop count to obtain a path with the minimum hop count between the source machine room node and the sink machine room node.
In a third aspect, a determining apparatus of a target node is provided, including: at least one processor, a memory for storing instructions executable by the processor; wherein the processor is configured to execute instructions to implement a method as provided by the first aspect and any one of its possible implementations.
In a fourth aspect, a computer readable storage medium is provided, which instructions, when executed by a processor of a determining apparatus of a target node, enable the determining apparatus of the target node to perform the method as provided in the first aspect and any one of its possible implementations.
In a fifth aspect, there is provided a computer program product comprising instructions which, when run on a computer, enable the computer to perform the method provided by the first aspect and any one of its possible embodiments.
In a sixth aspect, there is provided a chip system comprising: a processor and interface circuit; interface circuit for receiving computer program or instruction and transmitting to processor; the processor is configured to execute a computer program or instructions to cause the chip system to perform a method as provided in the first aspect and any one of its possible embodiments described above.
The technical effects of any one of the embodiments of the second aspect to the sixth aspect may be referred to the technical effects of the different embodiments of the first aspect, and are not described herein.
Drawings
FIG. 1 is a schematic diagram of a single-room multi-node provided herein;
fig. 2 is a schematic architecture diagram of a target node determining system provided in the present application;
fig. 3 is a flow chart of a method for determining a target node provided in the present application;
FIG. 4a is a first node topology provided herein;
FIG. 4b is a second node topology provided herein;
FIG. 5 is a flowchart of another method for determining a target node provided in the present application;
FIG. 6 is a flowchart of another method for determining a target node provided in the present application;
FIG. 7 is a schematic diagram of a determining device provided in the present application;
fig. 8 is a schematic structural view of still another determining apparatus provided in the present application.
Detailed Description
In the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", and the like are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
Meanwhile, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion that may be readily understood.
It is appreciated that reference throughout this specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, various embodiments are not necessarily referring to the same embodiments throughout the specification. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence number of each process does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
It is to be understood that in this application, the terms "when …," "if," and "if" are used to indicate that the corresponding process is to be performed under some objective condition, and are not intended to limit the time, nor do they require that the acts be performed with a judgment, nor are they intended to imply that other limitations are present.
It can be appreciated that some optional features of the embodiments of the present application may be implemented independently in some scenarios, independent of other features, such as the scheme on which they are currently based, to solve corresponding technical problems, achieve corresponding effects, or may be combined with other features according to requirements in some scenarios. Accordingly, the apparatus provided in the embodiments of the present application may also implement these features or functions accordingly, which is not described herein.
Throughout this application, unless specifically stated otherwise, identical or similar parts between the various embodiments may be referred to each other. In the present application, unless specifically stated or logic conflict, terms and/or descriptions between different embodiments and between implementation methods in the embodiments are consistent and may be mutually cited, technical features in the different embodiments and implementation methods in the embodiments may be combined to form a new embodiment, implementation, method, or implementation method according to their inherent logic relationship. The following embodiments of the present application are not to be construed as limiting the scope of the present application.
Fig. 2 is a schematic architecture diagram of a target node determining system provided in the present application, and the technical solution of the embodiment of the present application may be applied to the target node determining system shown in fig. 2, where, as shown in fig. 2, the target node determining system 20 includes a target node determining device 21 and an electronic device 22.
The determining device 21 of the target node is directly connected or indirectly connected to the electronic device 22, and in this connection relationship, the connection may be wired or wireless, which is not limited in this embodiment of the present application.
The determining means 21 of the target node may be adapted to receive data from the electronic device 22.
The electronic device 22 may be used for transmitting data to the determining means 21 of the target node.
It should be noted that, the determining device 21 of the target node and the electronic device 22 may be independent devices, or may be integrated in the same device, which is not specifically limited in this application.
When the determining means 21 of the target node and the electronic device 22 are integrated in the same device, the communication between the determining means 21 of the target node and the electronic device 22 is a communication between the internal modules of the device. In this case, the communication flow therebetween is the same as "in the case where the determination means 21 of the target node and the electronic device 22 are independent of each other".
In the following embodiments provided in the present application, the present application will be described taking the case where the determination device 21 of the target node and the electronic device 22 are provided independently of each other.
In practical applications, the method for determining a target node provided in the embodiments of the present application may be applied to the determining device 21 of the target node, or may be applied to a device included in the determining device 21 of the target node.
The determination method of the target node provided in the embodiment of the present application will be described below by taking the determination device 21 of the target node to which the determination method of the target node is applied as an example with reference to the accompanying drawings.
For convenience of description, the determining device of the target node will be simply referred to as a determining device in the following detailed description of the present application, and will not be described in detail herein.
Fig. 3 is a flow chart of a method for determining a target node provided in the present application, as shown in fig. 3, the method includes the following steps:
s301, a determining device acquires a first node topological graph.
The first node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes and a plurality of sink nodes, wherein the source nodes are located in a source machine room, and the sink nodes are located in a sink machine room.
Fig. 4a is a first node topology diagram provided in the present application, where, as shown in fig. 4a, the first node topology diagram includes 5 intermediate nodes, which are respectively an intermediate node 11, an intermediate node 12, an intermediate node 13, an intermediate node 14 and an intermediate node 15, and includes 3 source nodes, which are respectively a source node 4, a source node 5 and a source node 6, including 4 sink nodes, which are respectively a sink node 7, a sink node 8, a sink node 9 and a sink node 10, where the source node 4, the source node 5 and the source node 6 are located in a source room, and the sink node 7, the sink node 8, the sink node 9 and the sink node 10 are located in a sink room.
The intermediate node 11 in the first node topology is connected to the source node 4, the intermediate node 12, and the intermediate node 13, the intermediate node 13 is connected to the source node 5, the intermediate node 11, the intermediate node 12, the intermediate node 14, the intermediate node 15, and the sink node 9, and the intermediate node 14 is connected to the source node 6, the intermediate node 13, and the intermediate node 15, respectively.
As a possible implementation, in connection with fig. 2, the determining means receives a message from the electronic device, where the message includes the first node topology map, and the determining means obtains the first node topology map from the message.
As still another possible implementation manner, the determining device obtains connection relationships among the plurality of intermediate nodes, the plurality of source nodes and the plurality of sink nodes, and obtains corresponding relationships between the plurality of source nodes and the source machine room and corresponding relationships between the plurality of sink nodes and the sink machine room, so as to obtain the first node topology map.
S302, the determining device determines a second node topological graph according to the first node topological graph.
The second node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes, a plurality of destination nodes, source machine room nodes and destination machine room nodes, wherein the source machine room nodes are respectively connected with each source node, the destination machine room nodes are respectively connected with each destination node, the connection weight of the source machine room nodes and each source node is a preset weight, and the connection weight of the destination machine room nodes and each destination node is a preset weight.
It should be noted that the preset weight may be 1, or the preset weight may be 0.5, or the preset weight may be 10, which is not limited in this application.
As one possible implementation manner, the determining device determines a source machine room node according to the source machine room and determines a sink machine room node according to the sink machine room, connects the source machine room node with each source node in the first node topological graph respectively, sets a connection weight to be a preset weight, connects the sink machine room node with each sink node in the first node topological graph respectively, and sets the connection weight to be a preset weight, so as to obtain the second node topological graph.
It should be noted that, for a specific description of this possible implementation manner, reference may be made to the following part of this application in specific embodiments, which are not described herein in detail.
Fig. 4b is a second node topology diagram provided in the present application, where, as shown in fig. 4b, the second node topology diagram includes 5 intermediate nodes, which are respectively an intermediate node 11, an intermediate node 12, an intermediate node 13, an intermediate node 14 and an intermediate node 15, and includes 3 source nodes, which are respectively a source node 4, a source node 5 and a source node 6, and includes 4 sink nodes, which are respectively a sink node 7, a sink node 8, a sink node 9 and a sink node 10, and includes a source machine room node and a sink machine room node, where the source machine room node is respectively connected with the source node 4, the source node 5 and the source node 6, and the sink machine room node is respectively connected with the sink node 7, the sink node 8, the sink node 9 and the sink node 10.
And S303, determining a target path between the source machine room node and the sink machine room node by the determining device according to the second node topological graph and the target path algorithm.
It should be noted that the target path algorithm may be a minimum hop path algorithm, for example, the target path algorithm may be Dijkstra algorithm, or the target path algorithm may be a minimum delay path algorithm, which is not limited in this application.
As a possible implementation manner, the determining device inputs the second node topological graph into a target path algorithm to obtain a target path between the source computer room node and the destination computer room node.
It should be noted that, for a specific description of this possible implementation manner, reference may be made to the following part of this application in specific embodiments, which are not described herein in detail.
S304, the determining device takes the second node on the target path as a target source node and takes the penultimate node on the target path as a target destination node.
As a possible implementation manner, in connection with fig. 4b, if the target path is a source machine room node-source node 5-intermediate node 13-sink machine room node 9-sink machine room node, the determining device takes the second node source node 5 on the target path as the target source node and takes the last-to-last node sink node 9 on the target path as the target sink node.
After the determining means determines the target source node and the target sink node, a path between the target source node and the target sink node may be further determined.
Based on the scheme, the second node topological graph is determined according to the first node topological graph, the target path between the source machine room node and the sink machine room node is determined according to the second node topological graph, the second node and the penultimate node of the target path are determined as target nodes, and as the connection weight of the source machine room node and each source node is the same, the connection weight of the sink machine room node and each sink node is the same, and therefore after the target path between the source machine room node and the sink machine room node is obtained, the corresponding target source node and the target sink node can be determined. Compared with the existing scheme requiring determination of multiple paths, the scheme can determine the target source node and the target destination node only by determining the target path between the source computer room node and the destination computer room node, and the multiple paths are not required to be determined, so that the calculation amount for determining the target source node and the target destination node can be reduced, and the efficiency is improved.
The foregoing is a general description of the aspects of the present application, which are further described below with reference to the accompanying drawings.
In one design, fig. 5 is a flow chart of another method for determining a target node provided in the present application, as shown in fig. 5, where S302 provided in the specific embodiment of the present application specifically includes the following steps:
s501, determining means determines source machine room nodes according to the source machine room and determines sink machine room nodes according to the sink machine room.
As a possible implementation, the determining means abstracts the source machine room to a source machine room node and the determining means abstracts the sink machine room to a sink machine room node.
S502, the determining device connects the source machine room node with each source node in the first node topological graph respectively, and connects the sink machine room node with each sink node in the first node topological graph respectively, so as to obtain a second node topological graph.
As a possible implementation, taking the preset weight as 1 as an example, referring to fig. 4b, the determining device connects the source room node with the source node 4, and sets the connection weight to 1, the determining device connects the source room node with the source node 5, and sets the connection weight to 1, the determining device connects the source room node with the source node 6, and sets the connection weight to 1, the determining device connects the sink room node with the sink node 7, and sets the connection weight to 1, the determining device connects the sink room node with the sink node 8, and sets the connection weight to 1, the determining device connects the sink room node with the sink node 9, and sets the connection weight to 1, the determining device connects the sink room node with the sink node 10, and sets the connection weight to 1, and finally the second node topology map is obtained.
Based on this scheme, a scheme of determining the second node topology from the first node topology can be implemented.
In one design, fig. 6 is a flow chart of another method for determining a target node provided in the present application, and as shown in fig. 6, the target path algorithm is a delay minimum path algorithm, and S303 provided in the specific embodiment of the present application may specifically include:
s601, the determining device obtains time delay between the connected nodes in the second node topological graph.
Illustratively, in connection with fig. 4b, the delay between the intermediate node 11 and the intermediate node 12 in the second node topology is 0.2 milliseconds (ms), the delay between the intermediate node 13 and the source node 5 is 0.1ms, the delay between the intermediate node 14 and the intermediate node 13 is 0.3ms, etc.
As a possible implementation, in connection with fig. 2, the determining means receives a message from the electronic device, where the message includes a time delay between connected nodes in the second node topology, and the determining means obtains the time delay between connected nodes in the second node topology from the message.
S602, the determining device inputs the time delay between the connected nodes in the second node topological graph and the second node topological graph into a time delay minimum path algorithm to obtain a time delay minimum path between the source machine room node and the sink machine room node.
It should be noted that, the specific implementation process of the determining device to obtain the minimum delay path by inputting the delay between the connected nodes in the second node topology diagram and the second node topology diagram into the minimum delay path algorithm may refer to the description in the existing scheme, which is not described herein.
Based on the scheme, the scheme of determining the target path between the source machine room node and the sink machine room node according to the second node topological graph and the target path algorithm can be realized.
In one design, the target path algorithm is a hop-count minimum path algorithm, and S303 provided in this embodiment of the present application may specifically include:
the determining device inputs the second node topological graph into a path algorithm with the minimum hop count to obtain a path with the minimum hop count between the source machine room node and the sink machine room node.
It should be noted that, the specific implementation process of the determining device to input the second node topological graph into the path algorithm with the minimum hop count to obtain the path with the minimum hop count may refer to the description in the existing scheme, which is not described herein.
Based on the scheme, the scheme of determining the target path between the source machine room node and the sink machine room node according to the second node topological graph and the target path algorithm can be realized.
The above description has been made mainly from the point of view of the determining means executing the determining method of the target node. In order to implement the above-mentioned functions, the determining means comprise corresponding hardware structures and/or software modules for performing the respective functions. Those of skill in the art will readily appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The embodiment of the present application may divide the functional modules of the determining apparatus according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules may be implemented in hardware or in software functional modules. Optionally, the division of the modules in the embodiments of the present application is schematic, which is merely a logic function division, and other division manners may be actually implemented. Further, "module" herein may refer to an application-specific integrated circuit (ASIC), an electrical circuit, a processor and memory that execute one or more software or firmware programs, an integrated logic circuit, and/or other devices that can provide the above-described functionality.
Fig. 7 shows a schematic diagram of a configuration of a determination device in the case of a functional module division. As shown in fig. 7, the determining apparatus 70 includes an acquisition module 701 and a processing module 702.
In some embodiments, the determining means 70 may further comprise a storage module (not shown in fig. 7) for storing program instructions and data.
The acquiring module 701 is configured to acquire a first node topology map; the first node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes and a plurality of sink nodes, wherein the source nodes are positioned in a source machine room, and the sink nodes are positioned in a sink machine room; a processing module 702, configured to determine a second node topology map according to the first node topology map; the second node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes, a plurality of destination nodes, source machine room nodes and destination machine room nodes, wherein the source machine room nodes are respectively connected with each source node, the destination machine room nodes are respectively connected with each destination node, the connection weight of the source machine room nodes and each source node is a preset weight, and the connection weight of the destination machine room nodes and each destination node is a preset weight; the processing module 702 is further configured to determine a target path between the source computer room node and the sink computer room node according to the second node topology map and the target path algorithm; the processing module 702 is further configured to use the second node on the target path as the target source node and the penultimate node on the target path as the target destination node.
With reference to the second aspect, in some implementations of the second aspect, the processing module 702 is further configured to determine a second node topology map according to the first node topology map, specifically includes: determining source machine room nodes according to the source machine room and determining sink machine room nodes according to the sink machine room; and connecting the source machine room node with each source node in the first node topological graph respectively, and connecting the sink machine room node with each sink node in the first node topological graph respectively to obtain a second node topological graph.
With reference to the second aspect, in some implementations of the second aspect, the target path algorithm is a latency minimum path algorithm, and the processing module 702 is further configured to determine, according to the second node topology map and the target path algorithm, a target path between a source computer room node and a destination computer room node, specifically including: obtaining time delay between connected nodes in the second node topological graph; and inputting the time delay between the connected nodes in the second node topological graph and the second node topological graph into a time delay minimum path algorithm to obtain a time delay minimum path between the source machine room node and the sink machine room node.
With reference to the second aspect, in some implementations of the second aspect, the target path algorithm is a hop-count minimum path algorithm, and the processing module 702 is further configured to determine, according to the second node topology map and the target path algorithm, a target path between a source computer room node and a destination computer room node, specifically including: and inputting the second node topological graph into a path algorithm with the minimum hop count to obtain a path with the minimum hop count between the source machine room node and the sink machine room node.
All relevant contents of each step related to the above method embodiment may be cited to the functional descriptions of the corresponding functional modules, which are not described herein.
In the case of realizing the functions of the above-described functional modules in the form of hardware, fig. 8 shows a schematic configuration of a determination device. As shown in fig. 8, the determining device 80 includes a processor 801, a memory 802, and a bus 803. The processor 801 and the memory 802 may be connected by a bus 803.
The processor 801 is a control center of the determining apparatus 80, and may be one processor or a collective term of a plurality of processing elements. For example, the processor 801 may be a general-purpose central processing unit (central processing unit, CPU), or may be another general-purpose processor. Wherein the general purpose processor may be a microprocessor or any conventional processor or the like.
As one example, processor 801 may include one or more CPUs, such as CPU 0 and CPU 1 shown in fig. 8.
Memory 802 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), magnetic disk storage or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
As a possible implementation, the memory 802 may exist separately from the processor 801, and the memory 802 may be connected to the processor 801 through the bus 803 for storing instructions or program code. The processor 801, when calling and executing instructions or program code stored in the memory 802, is capable of implementing the method for determining a target node provided in the embodiments of the present application.
In another possible implementation, the memory 802 may also be integrated with the processor 801.
Bus 803 may be an industry standard architecture (Industry Standard Architecture, ISA) bus, a peripheral component interconnect (Peripheral Component Interconnect, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 8, but not only one bus or one type of bus.
It should be noted that the structure shown in fig. 8 does not constitute a limitation of the determination device 80. The determining means 80 may comprise more or less components than shown in fig. 8, or may be combined with certain components, or may be arranged in different components.
As an example, in connection with fig. 7, the acquisition module 701 and the processing module 702 in the determination device 70 realize the same functions as those of the processor 801 in fig. 8.
Optionally, as shown in fig. 8, the determining apparatus 80 provided in the embodiment of the present application may further include a communication interface 804.
A communication interface 804 for connecting with other devices via a communication network. The communication network may be an ethernet, a radio access network, a wireless local area network (wireless local area networks, WLAN), etc. The communication interface 804 may include a receiving unit for receiving data and a transmitting unit for transmitting data.
In a possible implementation manner, in the determining apparatus 80 provided in the embodiments of the present application, the communication interface 804 may also be integrated in the processor 801, which is not limited in particular in the embodiments of the present application.
As a possible product form, the determining device of the embodiment of the present application may be further implemented using the following: one or more field programmable gate arrays (field programmable gate array, FPGA), programmable logic devices (programmable logic device, PLD), controllers, state machines, gate logic, discrete hardware components, any other suitable circuit or combination of circuits capable of performing the various functions described throughout this application.
From the above description of embodiments, it will be apparent to those skilled in the art that the foregoing functional unit divisions are merely illustrative for convenience and brevity of description. In practical applications, the above-mentioned function allocation may be performed by different functional units, i.e. the internal structure of the device is divided into different functional units, as needed, to perform all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.
The present application also provides a computer-readable storage medium, on which a computer program or instructions are stored, which when executed cause a computer to perform the steps of the method flow shown in the above-described method embodiments.
Embodiments of the present application provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the steps of the method flows shown in the method embodiments described above.
An embodiment of the present application provides a chip system, including: a processor and interface circuit; interface circuit for receiving computer program or instruction and transmitting to processor; the processor is configured to execute the computer program or instructions to cause the chip system to perform the steps of the method flow shown in the method embodiments described above.
The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: electrical connections having one or more wires, portable computer diskette, hard disk. Random access Memory (Random Access Memory, RAM), read-Only Memory (ROM), erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), registers, hard disk, optical fiber, portable compact disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any other form of computer-readable storage medium suitable for use by a person or persons of skill in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in a special purpose ASIC. In the context of the present application, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
Since the determining apparatus, the computer readable storage medium, and the computer program product provided in this embodiment may be applied to the method for determining a target node provided in this embodiment, the technical effects that may be obtained by the determining apparatus, the computer readable storage medium, and the computer readable storage medium may refer to the method embodiment described above, and the embodiments of this application are not repeated herein.
Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the present application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. A method of determining a target node, the method comprising:
acquiring a first node topological graph; the first node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes and a plurality of sink nodes, wherein the source nodes are positioned in a source machine room, and the sink nodes are positioned in a sink machine room;
determining a second node topology graph according to the first node topology graph; the second node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes, a plurality of destination nodes, source machine room nodes and destination machine room nodes, wherein the source machine room nodes are respectively connected with each source node, the destination machine room nodes are respectively connected with each destination node, the connection weight of the source machine room nodes and each source node is a preset weight, the connection weight of the destination machine room nodes and each destination node is the preset weight, the source machine room nodes are nodes abstracted from the source machine room, and the destination machine room nodes are nodes abstracted from the destination machine room;
determining a target path between the source machine room node and the sink machine room node according to the second node topological graph and a target path algorithm;
and taking the second node on the target path as a target source node and the penultimate node on the target path as a target destination node.
2. The method according to claim 1, wherein said determining a second node topology from said first node topology comprises:
determining the source machine room node according to the source machine room and determining the sink machine room node according to the sink machine room;
and connecting the source machine room node with each source node in the first node topological graph respectively, and connecting the sink machine room node with each sink node in the first node topological graph respectively to obtain the second node topological graph.
3. The method according to claim 1 or 2, wherein the target path algorithm is a delay minimum path algorithm, and the determining, according to the second node topology map and the target path algorithm, a target path between the source computer room node and the sink computer room node specifically includes:
obtaining the time delay between the connected nodes in the second node topological graph;
and inputting the time delay between the connected nodes in the second node topological graph and the second node topological graph into the time delay minimum path algorithm to obtain the time delay minimum path between the source machine room node and the sink machine room node.
4. The method according to claim 1 or 2, wherein the target path algorithm is a hop-count minimum path algorithm, and the determining, according to the second node topology and the target path algorithm, a target path between the source computer room node and the sink computer room node specifically includes:
And inputting the second node topological graph into the path algorithm with the minimum hop count to obtain a path with the minimum hop count between the source machine room node and the sink machine room node.
5. A target node determining apparatus, wherein the target node determining apparatus includes: the device comprises an acquisition module and a processing module;
the acquisition module is used for acquiring a first node topological graph; the first node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes and a plurality of sink nodes, wherein the source nodes are positioned in a source machine room, and the sink nodes are positioned in a sink machine room;
the processing module is used for determining a second node topological graph according to the first node topological graph; the second node topological graph comprises a plurality of intermediate nodes, a plurality of source nodes, a plurality of destination nodes, source machine room nodes and destination machine room nodes, wherein the source machine room nodes are respectively connected with each source node, the destination machine room nodes are respectively connected with each destination node, the connection weight of the source machine room nodes and each source node is a preset weight, the connection weight of the destination machine room nodes and each destination node is the preset weight, the source machine room nodes are nodes abstracted from the source machine room, and the destination machine room nodes are nodes abstracted from the destination machine room;
The processing module is further configured to determine a target path between the source machine room node and the sink machine room node according to the second node topological graph and a target path algorithm;
the processing module is further configured to use a second node on the target path as a target source node and a penultimate node on the target path as a target destination node.
6. The apparatus for determining a target node according to claim 5, wherein the processing module is further configured to determine a second node topology according to the first node topology, and specifically comprises:
determining the source machine room node according to the source machine room and determining the sink machine room node according to the sink machine room;
and connecting the source machine room node with each source node in the first node topological graph respectively, and connecting the sink machine room node with each sink node in the first node topological graph respectively to obtain the second node topological graph.
7. The apparatus according to claim 5 or 6, wherein the target path algorithm is a delay minimum path algorithm, and the processing module is further configured to determine a target path between the source computer room node and the sink computer room node according to the second node topology map and the target path algorithm, and specifically includes:
Obtaining the time delay between the connected nodes in the second node topological graph;
and inputting the time delay between the connected nodes in the second node topological graph and the second node topological graph into the time delay minimum path algorithm to obtain the time delay minimum path between the source machine room node and the sink machine room node.
8. The apparatus for determining a destination node according to claim 5 or 6, wherein the destination path algorithm is a hop count minimum path algorithm, and the processing module is further configured to determine a destination path between the source computer room node and the sink computer room node according to the second node topology map and the destination path algorithm, and specifically includes:
and inputting the second node topological graph into the path algorithm with the minimum hop count to obtain a path with the minimum hop count between the source machine room node and the sink machine room node.
9. A target node determining apparatus, wherein the target node determining apparatus includes: a processor coupled to a memory for storing a program or instructions which, when executed by the processor, cause the determining means of the target node to perform the method of any of claims 1 to 4.
10. A computer readable storage medium having stored thereon a computer program or instructions, which when executed cause a computer to perform the method of any of claims 1 to 4.
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