CN115865053A - Ring oscillator circuit - Google Patents
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- CN115865053A CN115865053A CN202211163431.0A CN202211163431A CN115865053A CN 115865053 A CN115865053 A CN 115865053A CN 202211163431 A CN202211163431 A CN 202211163431A CN 115865053 A CN115865053 A CN 115865053A
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Abstract
The present invention provides a ring oscillator circuit, comprising: a bias circuit and a delay circuit; the bias circuit is used for generating a first bias current and a second bias current, and the first bias current is inversely proportional to a voltage drop resistor in the bias circuit and is in direct proportion to the square root of the reference current; in the delay circuit, a first input end of the delay control circuit is used for obtaining a first bias current, a second input end of the delay control circuit is used for obtaining a second bias current, and a first capacitor is configured in the delay control circuit, so that the rising delay time of an output end of the delay control circuit is in direct proportion to the first capacitor, in inverse proportion to the first bias current, and in direct proportion to a turnover threshold of a delay inverter in the delay control circuit, wherein the turnover threshold of the delay inverter is in direct proportion to the square root of a reference current, so that the oscillation period of the ring oscillator circuit is mainly determined by the proportion of the square root of a resistor, a capacitor and the reference current in the circuit, and the relation between the oscillation period and the magnitude of the reference current is weakened.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a ring oscillator circuit.
Background
Synchronous sequential logic circuits require clock triggering. The communication protocol requires a very precise level transition time for the digital logic circuit, which necessitates a highly precise and stable clock. Oscillator circuits are a conventional way of generating clock signals for integrated circuits. The following oscillator circuits are commonly used to provide clock signals to the chip:
one is to use a quartz crystal oscillator, which occupies a large area and weight of a circuit system on a circuit board, and the usage rate of a large area occupied circuit represented by the quartz crystal oscillator is gradually reduced.
One is a relaxation oscillator, and the basic principle is to apply triangular wave excitation to the input end of a hysteresis comparator, so that the output of the hysteresis comparator is continuously switched between a high level and a low level to generate a clock signal, and the clock frequency is usually low.
A ring oscillator is a common circuit that can generate a high frequency clock signal within an integrated circuit. The basic principle of the ring oscillator is that an odd number of inverters are connected in series to form a positive feedback loop to cause oscillation, and the oscillation period is the sum of delay and addition of 2 times of the inverters. A conventional ring circuit structure is shown in fig. 1, in which a delay controlled inverter and an even number of inverters are connected in series to form a ring. Only one node in the inverter ring is hung with a large capacitance load, so the oscillation period is mainly determined by the rising delay of the delay control unit.
In the above formula V TH2 Referring to M in the circuit disclosed in FIG. 1 P2 And M N2 The flip threshold of the constructed inverter. The period of oscillation is inversely proportional to the magnitude of the reference current. A2 frequency divider composed of D flip-flops is cascaded behind an oscillator to obtain a clock signal with the duty ratio close to 50%.
Oscillation time t of ring oscillator in prior art solutions r1 Will obviously receive the reference current I REF The size of (c). However, it is difficult to implement a reference current source that is not affected by manufacturing processes, power supply voltage, and temperature in the current analog electronic technology.
Disclosure of Invention
Embodiments of the present invention provide a ring oscillator circuit to reduce the influence of the reference current on the oscillation time of the ring oscillator.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
a ring oscillator circuit, comprising:
a bias circuit and a delay circuit;
the bias circuit is configured to generate a first bias current and a second bias current, wherein the first bias current is inversely proportional to a voltage drop resistance within the bias circuit, and the first bias current is further proportional to a square root of a reference current of the ring oscillator circuit;
the delay circuit: the method comprises the following steps:
the delay circuit comprises a delay control circuit, an inverter cascade circuit and a frequency divider;
a first input end of the delay control circuit is used for obtaining the first bias current, a second input end of the delay control circuit is used for obtaining the second bias current, a first capacitor is configured in the delay control circuit, and the rising delay time of the output end of the delay control circuit is in direct proportion to the first capacitor, in inverse proportion to the first bias current and in direct proportion to a turnover threshold of a delay inverter in the delay control circuit through the first capacitor, wherein the turnover threshold of the delay inverter is in direct proportion to the square root of the reference current;
the input end of the phase inverter cascade circuit is connected with the output end of the delay control circuit, the output end of the phase inverter cascade circuit is connected with the control end of the delay control circuit and the input end of the frequency divider, and the output end of the frequency divider serves as the output end of the ring oscillator circuit.
Optionally, in the ring oscillator circuit, the bias circuit includes:
the bias circuit includes: the circuit comprises a first current mirror circuit, a second current mirror circuit, a voltage follower and a voltage drop resistor;
the first output end of the second current mirror circuit is used for providing a first bias current, the second output end of the second current mirror circuit is connected with the first output end of the voltage follower, and the magnitude of the first bias current is inversely proportional to the voltage drop resistor;
the first current mirror circuit is used for providing a reference current, a second bias current and a third bias current;
the third bias current is connected with the target node and is used for generating a stable node voltage on the target node;
and the in-phase input end of the voltage follower is connected with the target node, and the in-phase output end of the voltage follower is connected with the voltage-drop resistor and used for generating and outputting a reference current matched with the resistance value of the voltage-drop resistor based on the virtual short effect.
Optionally, in the ring oscillator circuit, the delay control circuit: the method comprises the following steps:
the input end of the first inverter is used for acquiring the first bias current;
the input end of the delay inverter is used for acquiring the second bias current;
the first capacitor is arranged between the first inverter and the delay inverter, so that the delay time of the voltage of the output end of the first inverter rising from 0 to the overturning threshold of the delay inverter 2 is in direct proportion to the boost capacitor and the voltage drop resistor;
the inverter cascade circuit includes: the cascade connection of odd number of inverters, the input end of the first inverter cascade in the cascade connection of odd number of inverters is connected with the output end of the delay inverter, the output end of the last inverter cascade is connected with the control end of the first inverter;
and the input end of the frequency divider halver is connected with the output end of the cascade of the phase inverters at the tail end.
Optionally, in the ring oscillator circuit, the first current mirror circuit includes:
a first field effect transistor, a second field effect transistor, a third field effect transistor, and a reference current source;
the control ends of the first field effect transistor, the second field effect transistor and the third field effect transistor are interconnected, and the control end of the first field effect transistor is connected with the output end of the first field effect transistor;
the reference current source is connected with the output end of the first field effect transistor;
and the input ends of the first field effect transistor, the second field effect transistor and the third field effect transistor are connected with a direct current power supply.
Optionally, in the ring oscillator circuit, the second current mirror circuit includes:
a fourth field effect transistor and a fifth field effect transistor;
the control ends of the fourth field effect transistor and the fifth field effect transistor are interconnected, and the control end of the fourth field effect transistor is connected with the output end of the fifth field effect transistor.
Optionally, in the ring oscillator circuit, the voltage follower includes:
a first operational amplifier and a first transistor;
the non-inverting input end of the first operational amplifier is connected with the target node;
the control end of the first transistor is connected with the output end of the first operational amplifier;
the output end of the first transistor is connected with the inverting input end of the first operational amplifier and is grounded through a voltage drop resistor.
Optionally, in the ring oscillator circuit, the bias circuit further includes:
a second transistor;
the control end and the input end of the second transistor are connected with the target node;
the output end of the second transistor is grounded.
Optionally, in the ring oscillator circuit, the first inverter includes:
a third transistor, a fourth transistor, and a first capacitor;
the control ends of the third transistor and the fourth transistor are interconnected, the input end of the third transistor is used for obtaining the first bias current, the output end of the third transistor is connected with the input end of the fourth transistor, and the output end of the fourth transistor is grounded;
the first end of the first capacitor is connected with the input end of the fourth transistor, and the second end of the first capacitor is connected with the output end of the fourth transistor.
Optionally, in the ring oscillator circuit, the delay inverter includes:
a fifth transistor;
the input end of the fifth transistor is used for acquiring the second bias current;
the control end of the fifth transistor is connected with the output end of the first inverter;
the output end of the fifth transistor is grounded.
Optionally, in the ring oscillator circuit, each inverter cascade includes:
a sixth transistor and a seventh transistor;
the control ends of the sixth transistor and the seventh transistor are interconnected, the input end of the sixth transistor is connected with the direct-current power supply, the output end of the sixth transistor is connected with the input end of the seventh transistor, the output end of the seventh transistor is grounded, the control ends of the sixth transistor and the seventh transistor serve as the cascade input end of the phase inverter, and the output end of the sixth transistor serves as the cascade output end of the phase inverter.
Optionally, in the ring oscillator circuit, the voltage drop resistor is an adjustable resistor.
Optionally, in the ring oscillator circuit, the first capacitor is an adjustable capacitor.
Based on the above technical solution, in the above solution provided by the embodiment of the present invention, the ringThe oscillation period of the oscillator circuit is mainly composed of resistance, capacitance and reference current I REF Is determined by the ratio of the square root of (a) to (b), weakening the oscillation period from the reference current I REF The relationship of size.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a circuit diagram of a ring oscillator according to the prior art;
FIG. 2 is a schematic diagram of a ring oscillator circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a specific structure of a bias circuit A in a ring oscillator circuit disclosed in an embodiment of the present application;
fig. 4 is a schematic diagram of a specific structure of a delay circuit B in a ring oscillator circuit disclosed in the embodiment of the present application;
FIG. 5 shows a diagram of V in the delay circuit B according to the embodiment of the present application 1 Node and V 2 The voltage change of the node is shown schematically.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
To solve the problem that the oscillation time of the ring oscillator is obviously influenced by a reference current I REF The present application discloses a ring oscillator circuit, see fig. 2, comprising:
a bias circuit A and a delay circuit B;
the bias circuit A is used for generating a first bias current I1 and a second bias current I2, wherein the first bias current I 1 And a voltage drop resistor R in the bias circuit A 0 Inversely proportional, the first bias current also being equal to a reference current I of the ring oscillator circuit REF Is proportional to the square root of;
the delay circuit B: the method comprises the following steps:
the delay circuit comprises a delay control circuit B1, an inverter cascade circuit B2 and a frequency divider B3;
a first input end of the delay control circuit B1 is configured to obtain the first bias current I1, a second input end of the delay control circuit B1 is configured to obtain the second bias current I2, and a first capacitor C is configured in the delay control circuit B1 1 Through said first capacitance C 1 So that the rising delay time of the output end of the delay control circuit is in direct proportion to the first capacitor and in inverse proportion to the first bias current I1, that is, the rising delay time of the output end of the delay control circuit is in direct proportion to the first capacitor and the voltage drop resistor and in direct proportion to the turnover threshold of a delay inverter in the delay control circuit, wherein the turnover threshold of the delay inverter is in direct proportion to the square root of the reference current; (ii) a
The input end of the phase inverter cascade circuit B2 is connected with the output end of the delay control circuit B1, the output end of the phase inverter cascade circuit is connected with the control end of the delay control circuit and the input end of the frequency divider B3, and the output end of the frequency divider B3 is used as the output end of the ring oscillator circuit.
In the above scheme provided by the embodiment of the present invention, by configuring the voltage drop resistor and the first capacitor in the ring oscillator circuit, the rise delay time of the output terminal of the delay control circuit is proportional to the first capacitor and the voltage drop resistor, so that the oscillation period of the ring oscillator circuit is mainly determined by the proportion of the voltage drop resistor, the first capacitor, the transistor turn-on threshold and the current mirror in the circuit, and the oscillation period is weakenedOscillation period and reference current I of ring oscillator circuit REF The relationship of size.
In the following specific embodiments, the present application also discloses specific structures of the bias circuit a and the delay circuit B.
Referring to fig. 3, the bias circuit a includes: a first current mirror circuit 101, a second current mirror circuit 102, and a voltage follower 103;
a first output terminal of the second current mirror circuit 102 is configured to provide a first bias current I1, and a second output terminal of the second current mirror circuit 102 is connected to an output terminal of the voltage follower 103;
the first current mirror circuit 101 is used for providing a reference current I REF A second bias current I2 and a third bias current I3;
the third bias current I3 is connected to the target node O for generating a stable node voltage at the target node O;
the non-inverting input terminal of the voltage follower 103 is connected to the target node O, and the voltage follower 103 is configured to generate a reference current at an output terminal thereof;
referring to fig. 4, the delay control circuit B1 includes:
a first delay inverter 201, wherein an input end of the first delay inverter 201 is used for obtaining the first bias current I1;
the input end of the delay inverter 202 is used for acquiring the second bias current I2;
a first capacitor C is arranged between the first delay inverter 201 and the delay inverter 202 1 。
The inverter cascade circuit B2 includes:
an odd number of inverter cascades 203 connected in series, wherein the input end of the first inverter cascade 203 of the odd number of inverter cascades 203 is connected with the output end of the delay inverter 202, and the output end of the last inverter cascade 203 is connected with the control end of the first delay inverter 201;
and the input end of the frequency-halving device B3 is connected with the output end of the inverter cascade 203 at the tail, and the output end of the frequency-halving device B3 is used as the output end of the ring oscillator circuit.
Referring to fig. 3, the first current mirror circuit 101 includes:
first field effect transistor M m0 A second field effect transistor M m1 A third field effect transistor M m2 And a reference current source for providing a reference current I REF ；
The first field effect transistor M m0 A second field effect transistor M m1 And a third field effect transistor M m2 The first field effect transistor M m0 And the first field effect transistor M m0 The output ends of the two are connected;
the reference current source and the first field effect transistor M m0 The output ends of the two are connected;
the first field effect transistor M m0 A second field effect transistor M m1 And a third field effect transistor M m2 Input terminal and DC power supply V DD Are connected.
Referring to fig. 3, in the above embodiment, the first field effect transistor M m0 Is connected in diode form to an output terminal (drain), a first field effect transistor M m0 A second field effect transistor M m1 A third field effect transistor M m2 Are connected together to form a current mirror circuit. A reference current source and the first field effect transistor M m0 The first current mirror circuit 101 generates two bias currents: a second bias current I2 and a third bias current I3. In this embodiment, the first field effect transistor M m0 Second field effect transistor M m1 A third field effect transistor M m2 May be 1 m, wherein m and n are greater than 0, when the second bias current I2= mI REF Said third bias current I3= nI REF 。
Referring to fig. 3, the third field effect transistorM m2 Is connected to the target node O such that the third bias current I3 generates a stable node voltage VGS, REF at said target node O. Referring to fig. 3, in order to realize that the third bias current I3 generates a stable node voltage VGS, REF at the target node O, in the present scheme, the bias circuit a further includes a second transistor M n0 The second transistor M n0 Is connected to the gate and drain of the diode-connected second transistor M for the third bias current I3 n0 Generating a stable node voltage VGS, REF, whose voltage value can be expressed as:
wherein, the mu n Denotes the second transistor M n0 Electron mobility of (c) of ox Denotes the second transistor M n0 Represents the gate oxide capacitance per unit area of the second transistor M, and W represents the second transistor M n0 The channel width of (a), the L represents the second transistor M n0 N0 represents the second transistor M n0 Said V is t，N0 Denotes the second transistor M n0 Threshold voltage of
Referring to fig. 3, the voltage follower 103 includes:
a first operational amplifier OP and a first transistor M p0 ；
The non-inverting input end of the first operational amplifier OP is connected with the target node O;
the first transistor M p0 The control terminal of (a) is connected with the output terminal of the first operational amplifier OP;
the first transistor M p0 Is connected to the inverting input of the first operational amplifier OP and via a voltage dropping resistor R 0 And is grounded.
Referring to fig. 3, in the technical solution disclosed in the embodiment of the present application, the first operational amplifier OP and the first transistor M P0 Forming a voltage follower 103, a non-inverting input of the first operational amplifier OP and a second transistor M N0 Of a grid electrodeAnd a drain electrode connected to the first transistor M and an inverting input terminal p0 Source and drop resistor R 0 Is connected to the common terminal of the first operational amplifier OP, the output terminal of the first operational amplifier OP and the first transistor M p0 Is connected to the gate of (a). By utilizing the virtual short effect of the first operational amplifier OP, the voltages of the non-inverting input terminal and the inverting input terminal of the first operational amplifier OP are equal. The aforementioned node voltage VGS, REF is applied across the voltage drop resistor R by the voltage follower 103 0 A reference current is generated. This reference current is scaled by k times by the current mirror of the second current mirror circuit 102 to obtain the first bias current I1.
Referring to fig. 3, the second current mirror circuit 102 includes:
fourth field effect transistor M m3 And a fifth field effect transistor M m4 ；
The fourth field effect transistor M m3 And a fifth field effect transistor M m4 Is interconnected with the control terminal of the fourth field effect transistor M m3 And the fifth field effect transistor M m4 Are connected with each other.
Referring to fig. 4, the third transistor M in the delay control circuit B1 P1 The fourth transistor M N1 Constituting a first delayed inverter 201. The fifth transistor M N2 And the switch tube M m1 Forming a delay inverter 202, the first capacitor C 1 Disposed between the first delayed inverter 201 and the delayed inverter 202. Each inverter cascade 203 of the inverter cascade circuits comprises: sixth transistor M p3 And a seventh transistor M m3 ；
The third transistor M P1 And the fourth transistor M N1 Is connected to the control terminal of the third transistor M P1 For obtaining the first bias current I1, the third transistor M P1 And the fourth transistor M N1 Is connected to the input terminal of the fourth transistor M, the fourth transistor M N1 The output end of the voltage converter is grounded;
the first capacitor C 1 And the fourth transistor M N1 Is connected to the input terminal of the first capacitor C 1 And the second terminal of the fourth transistor M N1 Are connected.
The fifth transistor M N2 Is used for obtaining the second bias current I2;
the fifth transistor M N2 Is connected to the output of the first delayed inverter 201;
the fifth transistor M N2 The output terminal of (a) is grounded.
The sixth transistor M p3 And the seventh transistor M m3 Is interconnected, the sixth transistor M p3 And the input end of the DC power supply V DD To the sixth transistor M p3 And the seventh transistor M m3 Is connected to the input terminal of the seventh transistor M m3 Is grounded, the sixth transistor M p3 And the seventh transistor M m3 As an input of the inverter cascade 203, the sixth transistor M p3 As the output of the inverter cascade 203.
In the above solution, the turning threshold of the delay inverter 2 is approximately equal to the gate-source voltage of the fifth transistor MN2 entering the saturation region, and its value is:
N2 denotes a fifth transistor M N2 ，V t，N2 Is a fifth transistor M N2 Threshold value ofVoltage, in the formula said μ n Denotes a fifth transistor M N2 Electron mobility of (c) c ox Denotes a fifth transistor M N2 Represents the gate oxide capacitance per unit area of the fifth transistor M, and W represents the fifth transistor M N2 L denotes a channel width of the fifth transistor M, and L denotes a channel width of the fifth transistor M N2 The channel length of (a).
V 1 The node voltage rises from 0 to V TH2 The time delay is as follows:
it can be seen that, in the ring oscillator circuit disclosed in the embodiment of the present application, the drop resistance R can be set appropriately 0 And the capacitance value C of the first capacitor 1 Let t be r1 The oscillation period T is far larger than other delays tod in the oscillation period, and is determined by the rising delay of the delay circuit B, so that the weak correlation between the oscillation period and the reference current can be realized. In particular, the voltage V of a key node in the circuit 1 And V 2 The waveform of (2) is shown in fig. 5.
In the technical scheme disclosed in the embodiment of the application, t can be adjusted according to requirements r1 The voltage drop resistance is an adjustable resistance. The first capacitor C 1 Is an adjustable capacitor.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A ring oscillator circuit, comprising:
a bias circuit and a delay circuit;
the bias circuit is configured to generate a first bias current and a second bias current, wherein the first bias current is inversely proportional to a voltage drop resistance within the bias circuit, and the first bias current is further proportional to a square root of a reference current of the ring oscillator circuit;
the delay circuit: the method comprises the following steps:
the delay circuit comprises a delay control circuit, an inverter cascade circuit and a frequency divider;
a first input end of the delay control circuit is used for obtaining the first bias current, a second input end of the delay control circuit is used for obtaining the second bias current, a first capacitor is configured in the delay control circuit, and the rising delay time of the output end of the delay control circuit is in direct proportion to the first capacitor, in inverse proportion to the first bias current and in direct proportion to a turnover threshold of a delay inverter in the delay control circuit through the first capacitor, wherein the turnover threshold of the delay inverter is in direct proportion to the square root of the reference current;
the input end of the phase inverter cascade circuit is connected with the output end of the delay control circuit, the output end of the phase inverter cascade circuit is connected with the control end of the delay control circuit and the input end of the frequency divider, and the output end of the frequency divider serves as the output end of the ring oscillator circuit.
2. The ring oscillator circuit of claim 1, wherein the bias circuit comprises:
the bias circuit includes: the voltage follower circuit comprises a first current mirror circuit, a second current mirror circuit, a voltage follower and a voltage drop resistor;
the first output end of the second current mirror circuit is used for providing a first bias current, the second output end of the second current mirror circuit is connected with the first output end of the voltage follower, and the magnitude of the first bias current is inversely proportional to the voltage drop resistance;
the first current mirror circuit is used for providing a reference current, a second bias current and a third bias current;
the third bias current is connected with the target node and is used for generating a stable node voltage on the target node;
and the in-phase input end of the voltage follower is connected with the target node, and the in-phase output end of the voltage follower is connected with the voltage-drop resistor and used for generating and outputting a reference current matched with the resistance value of the voltage-drop resistor based on the virtual short effect.
3. The ring oscillator circuit of claim 1, wherein the delay control circuit: the method comprises the following steps:
the input end of the first inverter is used for acquiring the first bias current;
the input end of the delay inverter is used for acquiring the second bias current;
the first capacitor is arranged between the first inverter and the delay inverter, so that the delay time of the voltage of the output end of the first inverter rising from 0 to the turnover threshold of the delay inverter 2 is in direct proportion to the boost capacitor and the voltage drop resistor;
the inverter cascade circuit includes: the cascade connection of odd inverters is realized, the input end of the first inverter cascade in the odd inverter cascades is connected with the output end of the delay inverter, and the output end of the last inverter cascade is connected with the control end of the first inverter;
and the input end of the frequency halving device is connected with the output end of the cascade of the inverter at the tail end.
4. The ring oscillator circuit according to claim 2, wherein the first current mirror circuit comprises:
a first field effect transistor, a second field effect transistor, a third field effect transistor, and a reference current source;
the control ends of the first field effect transistor, the second field effect transistor and the third field effect transistor are interconnected, and the control end of the first field effect transistor is connected with the output end of the first field effect transistor;
the reference current source is connected with the output end of the first field effect transistor;
and the input ends of the first field effect transistor, the second field effect transistor and the third field effect transistor are connected with a direct current power supply.
5. A ring oscillator circuit according to claim 4, wherein the second current mirror circuit comprises:
a fourth field effect transistor and a fifth field effect transistor;
the control ends of the fourth field effect transistor and the fifth field effect transistor are interconnected, and the control end of the fourth field effect transistor is connected with the output end of the fifth field effect transistor.
6. The ring oscillator circuit of claim 5, wherein the voltage follower comprises:
a first operational amplifier and a first transistor;
the non-inverting input end of the first operational amplifier is connected with the target node;
the control end of the first transistor is connected with the output end of the first operational amplifier;
the output end of the first transistor is connected with the inverting input end of the first operational amplifier and is grounded through a voltage drop resistor.
7. The ring oscillator circuit of claim 6, wherein the bias circuit further comprises:
a second transistor;
the control end and the input end of the second transistor are connected with the target node;
the output end of the second transistor is grounded.
8. The ring oscillator circuit of claim 3, wherein the first inverter comprises:
a third transistor, a fourth transistor and a first capacitor;
the control ends of the third transistor and the fourth transistor are interconnected, the input end of the third transistor is used for acquiring the first bias current, the output end of the third transistor is connected with the input end of the fourth transistor, and the output end of the fourth transistor is grounded;
the first end of the first capacitor is connected with the input end of the fourth transistor, and the second end of the first capacitor is connected with the output end of the fourth transistor.
9. The ring oscillator circuit of claim 8, wherein the delayed inverter comprises:
a fifth transistor;
the input end of the fifth transistor is used for acquiring the second bias current;
the control end of the fifth transistor is connected with the output end of the first inverter;
the output end of the fifth transistor is grounded.
10. The ring oscillator circuit of claim 9, wherein each inverter cascade comprises:
a sixth transistor and a seventh transistor;
the control ends of the sixth transistor and the seventh transistor are interconnected, the input end of the sixth transistor is connected with the direct-current power supply, the output end of the sixth transistor is connected with the input end of the seventh transistor, the output end of the seventh transistor is grounded, the control ends of the sixth transistor and the seventh transistor serve as the cascade input end of the phase inverter, and the output end of the sixth transistor serves as the cascade output end of the phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211163431.0A CN115865053A (en) | 2022-09-23 | 2022-09-23 | Ring oscillator circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211163431.0A CN115865053A (en) | 2022-09-23 | 2022-09-23 | Ring oscillator circuit |
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| CN115865053A true CN115865053A (en) | 2023-03-28 |
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| CN202211163431.0A Pending CN115865053A (en) | 2022-09-23 | 2022-09-23 | Ring oscillator circuit |
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