CN115863333A

CN115863333A - Si-SiC power integration module with low parasitic inductance

Info

Publication number: CN115863333A
Application number: CN202211096361.1A
Authority: CN
Inventors: 周云艳; 胡娟; 鲍婕; 芦莎; 孙太明; 赵年顺; 汪礼; 刘梓灿; 刘永辉
Original assignee: Huangshan University
Current assignee: Huangshan University
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2023-03-28

Abstract

The invention discloses a Si-SiC power integrated module with low parasitic inductance, which comprises a three-phase inverter circuit, a brake circuit and a three-phase rectifier circuit. The silicon-based rectifier diode chip comprises a silicon-based IGBT chip, a silicon carbide SBD chip, a silicon-based FRD chip, a silicon-based rectifier diode chip, a copper-clad ceramic substrate, a solder layer, a bonding lead, a copper gasket, a pin electrode and the like. The three-phase inverter circuit adopts three groups of direct current bus pin electrodes to be respectively connected with the collector electrodes of each phase of the upper bridge arm, so that the parasitic inductance of the three-phase power converter circuit is ensured to be lower and the requirement of three-phase balanced work is met. The grid of the IGBT chip in the braking circuit is placed at a position close to the lead frame at the edge of the copper-clad ceramic substrate, and a local double-layer substrate structure is adopted, namely a copper sheet is used for replacing a bonding wire of an emitter of the braking circuit, so that the grid loop parasitic inductance and the power conversion loop parasitic inductance of the braking circuit are reduced.

Description

Si-SiC power integration module with low parasitic inductance

Technical Field

The invention relates to the technical field of semiconductors, in particular to a Si-SiC power integrated module with low parasitic inductance.

Background

The power integration module encapsulates a rectifying circuit, a braking circuit, an inverter circuit and the like in the same module so as to meet the application requirements of large current and high power, has the advantages of small volume, light weight, low switching loss and the like, and has attracted extensive attention in recent years. With the development of the third generation of semiconductors, the adoption of silicon carbide (SiC) devices instead of silicon (Si) devices in power modules can increase power density and reduce power loss. Naturally, higher requirements are also put on the packaging technology of the power integrated module. In China patent application 202110426392.8 of Juanjuan et al, a silicon carbide-based SBD chip is adopted to replace a silicon-based FRD chip in an inverter circuit, so that the layout space inside a Si-SiC power integrated module is enlarged, and a Cu/GN heterogeneous film is adopted to replace a local bonding wire, so that the local heat of a chopper circuit IGBT chip in a high-power PIM is dissipated through an upper heat conduction path and a lower heat conduction path, and the temperature of a local hot spot on the chip is reduced; meanwhile, graphene is uniformly added into epoxy resin to serve as a potting material, so that the overall thermal resistance of the high-power PIM from a chip to the environment is reduced, and the heat dissipation efficiency is improved. The switching frequency of the silicon carbide-based power semiconductor device is continuously improved, so that the influence of parasitic parameters of the device is increased, the switching loss is increased, and the EMI is increased. The parasitic inductance can generate larger voltage at the moment of switching on and off the device, and the larger voltage is superposed with the voltage or current of the device, so that the normal working state of the device is influenced, the EMI is increased, the aging of the device can be accelerated, even the device fails, and meanwhile, the loss of the device is increased due to the existence of the parasitic parameters.

In order to reduce parasitic inductance brought by packaging of the power module and maintain the characteristic that a traditional packaging structure is easy to process, the parasitic inductance of a current conversion loop of an inverter circuit is reduced by optimizing the layout of chips in the Si-SiC power module and reasonably setting the positions of pin electrodes by adopting a method of a local double-layer substrate, the balance of three-phase loop inductance is ensured, and grid loop inductance and common source parasitic inductance of a brake circuit are reduced, so that the electrical performance of the Si-SiC power integrated module is improved.

Disclosure of Invention

To overcome the above-mentioned deficiencies of the prior art, the present invention provides a Si-SiC power integrated module with low parasitic inductance. The inverter circuit effectively ensures that the U, V and W three-phase wires are consistent from the internal structure, the power conversion loop is small, and the parasitic inductance of the inverter circuit is small and balanced. The grid loop parasitic inductance and the common emitter parasitic inductance of the braking circuit are further reduced in the braking circuit.

In order to achieve the aim, the invention discloses a Si-SiC power integrated module with low parasitic inductance, which structurally comprises a three-phase inverter circuit, a brake circuit and a three-phase rectifier circuit.

All circuits are manufactured on a copper-clad ceramic substrate, a plurality of copper substrates are etched on the surface of the copper-clad ceramic substrate to serve as wiring layers, and pin electrodes serving as lead frames are welded on one part of the copper substrates; in the three-phase inverter circuit, each phase of U, V and W is provided with a special direct current bus pin electrode, an upper bridge arm is welded on the same copper substrate, three groups of pin electrodes are led out, the upper bridge arm is externally connected with the anode of a direct current voltage source, a lower bridge arm is welded on three different copper substrates, each phase is respectively connected to three different lead frame copper substrates through bonding wires, three groups of pin electrodes are led out, and the lower bridge arm is externally connected with the cathode of the direct current voltage source; the cathode of a silicon-based FRD chip in the brake circuit is welded on a copper substrate where a bridge arm on the three-phase inverter circuit is positioned, is close to the U-phase upper bridge arm chip and shares the same pin electrode with the U-phase upper bridge arm to be externally connected with the anode of a direct current voltage source; the collector of the silicon-based IGBT chip in the brake circuit is welded on the other copper substrate, and the copper substrate is connected with the anode of the silicon-based FRD chip through a bonding wire and leads out an output pin electrode of the brake circuit; a lead frame copper substrate externally connected with the negative electrode of a direct current voltage source is arranged beside an emitting electrode of a silicon-based IGBT chip in the braking circuit, and the emitting electrode of the silicon-based IGBT chip is connected with the lead frame copper substrate externally connected with the negative electrode of the direct current voltage source through a copper sheet.

A three-phase inverter circuit, a brake circuit and a three-phase rectifier circuit are sequentially arranged on a copper-clad ceramic substrate from left to right.

The three silicon-based IGBT chips are arranged side by side from left to right and are uniformly distributed, the three silicon-based IGBT chips are positioned on one side close to the upper edge of the copper-coated ceramic substrate, the grid electrodes of the IGBT chips face outwards, the three silicon-based SBD chips correspond to positions below the three silicon-based IGBT chips at equal intervals, three groups of pin electrodes are respectively led out from the copper substrate on the right side of the three silicon-based SBD chips and are used as positive pins of the DC voltage source of the three phases of U, V and W, and one group of two pin electrodes are arranged; the emitting electrodes of the three IGBT chips of the upper bridge arm are connected with the anodes of the three silicon carbide-based SBD chips through bonding wires, and the anodes of the silicon carbide-based SBD chips are connected to the copper substrate of the lower bridge arm through the bonding wires.

The three silicon-based IGBT chips and the three silicon-carbide-based SBD chips of the lower bridge arm of the three-phase inverter circuit are grouped in pairs and are respectively positioned below the phase chip of the upper bridge arm, the three groups of chips are also arranged side by side from left to right and are consistent in layout, wherein the three silicon-based IGBT chips are positioned on one side close to the lower edge of the copper-coated ceramic substrate, the grid electrodes of the silicon-based IGBT chips face outwards, and the three silicon-carbide-based SBD chips are correspondingly positioned above the three silicon-based IGBT chips at equal intervals; the three groups of chips are positioned on three different copper substrates, wherein a collector of the silicon-based IGBT chip and a cathode of the SBD chip are welded on the copper substrate, an emitter of the silicon-based IGBT chip and an anode of the silicon carbide SBD chip are connected through bonding wires, the emitter of the IGBT chip is respectively connected to the three lead frame copper substrates through the bonding wires, and a group of pin electrodes externally connected with a direct current voltage source negative electrode is respectively led out of each copper substrate.

The U, V and W phases in the three-phase inverter circuit adopt different direct current bus pin electrodes, the direct current bus pin electrodes are positioned at the edge of the copper-clad ceramic substrate and close to the respective corresponding silicon-based IGBT chips, the power commutation loops of all the phases are mutually independent, and the path shapes of the commutation loops are kept consistent.

In the braking circuit, a lead frame copper substrate externally connected with a negative electrode of a direct current voltage source is positioned between a silicon-based IGBT chip and a three-phase rectification circuit, a copper gasket with the same thickness as the silicon-based IGBT chip is arranged on the lead frame copper substrate externally connected with the negative electrode of the direct current voltage source, a copper sheet is welded on the upper surfaces of an emitter of the silicon-based IGBT chip and the copper gasket to connect the emitter and the copper gasket to form a double-layer substrate structure, and a pin electrode of the emitter of the silicon-based IGBT chip of the braking circuit and the negative electrode of an externally connected direct current bus are led out through the lead frame copper substrate externally connected with the negative electrode of the direct current voltage source; the grid of the silicon-based IGBT chip of the brake circuit is close to the lower edge of the copper-clad ceramic substrate and is connected to the copper substrate of the lead frame at the lower edge through a bonding wire.

In the three-phase rectifying circuit, cathodes of three silicon-based rectifier diode chips of an upper arm common cathode group of three phases are welded on the same copper substrate, a pin electrode is led out of the copper substrate and is used as an anode of a rectifying output, cathodes of three silicon-based rectifier diode chips of a lower arm common anode group are respectively welded on three copper substrates, anodes of the upper arm silicon-based rectifier diode chips are respectively connected to the three copper substrates where the lower arm silicon-based rectifier diode chips are located through bonding wires, and three corresponding groups of pin electrodes are led out of the three copper substrates and externally connected with a three-phase alternating current power supply; the anodes of the three diodes of the lower arm are connected together by bonding wires and to another separate copper substrate from which a pin electrode is drawn as the negative pole of the rectified output.

Compared with the prior art, the invention has the beneficial effects that:

1. the upper bridge arm of the three-phase inverter circuit adopts three groups of pin electrodes as the positive pins of the direct current buses of the U-phase, the V-phase and the W-phase respectively, so that the condition that external direct current voltage sources are added into the U-phase, the V-phase and the W-phase of the inverter circuit from the inside and the wiring is the same can be ensured, the three-phase power current conversion loop structure is the same, and the current backflow path is the minimum, thereby reducing the parasitic inductance of the three-phase inverter circuit, ensuring that the overshoot and the oscillation of an IGBT in the switching-on and switching-off processes are smaller, and ensuring that the inverter circuit can work safely. And the same backflow path enables the three-phase parasitic inductances to be basically consistent in size, so that the three-phase current can be guaranteed to work in a balanced mode.

2. The invention adopts the silicon carbide-based SBD to reduce the switching loss on one hand and to facilitate the layout of the brake circuit on the other hand. The brake circuit adopts a local double-layer substrate structure, and a copper substrate is utilized to replace a bonding wire from an emitter to a pin electrode copper substrate of the traditional package, so that the module forms the local double-layer substrate structure, and the grid loop inductance and the common emitter parasitic inductance of the brake circuit are reduced. Therefore, the switching overshoot caused by parasitic inductance in the working process of the braking circuit is reduced.

3. The invention adopts the local double-layer substrate structure in the brake circuit, so that the heat generated by the IGBT chip is simultaneously dissipated from the upper surface and the lower surface of the chip, and the heat dissipation efficiency of the module is improved.

Drawings

FIG. 1 is an internal equivalent circuit diagram of the present invention.

Fig. 2 is a top view of the internal layout of the present invention.

Fig. 3 is a side view of the internal layout of the present invention.

Fig. 4 is a diagram of an internal layout and pin location identification of an embodiment of the present invention without bond wires.

FIG. 5 is a cross-sectional view of the present invention.

FIG. 6 is a side view of a layout of a low parasitic inductance braking circuit without pins.

FIG. 7 is a commutation loop of a Si-SiC power integrated module inverter circuit with low parasitic inductance.

FIG. 8 is a commutation loop of a Si-SiC power integrated module inverter circuit with a conventional layout.

Detailed Description

The invention is further illustrated by the following examples in conjunction with the drawings.

Like elements in the various figures are denoted by like reference numerals. For ease of illustration, the pin names found in the present invention are described in detail in the following table, see fig. 4.

TABLE 1 Pin description of Si-SiC Power integration Module

Pin name	Description of the preferred embodiment
		P	Rectifier circuit output DC voltage source positive terminal
N	Negative terminal of output direct current voltage source of rectifying circuit
		L1、L2、L3	Three-phase AC power input end of rectification circuit
P1	U phase of inverter circuit and positive end of external direct current voltage source of brake circuit
		P2	V-phase external direct-current voltage source positive terminal of inverter circuit
P3	W-phase external direct-current voltage source positive terminal of inverter circuit
		NB	The braking circuit is externally connected with the negative end of a direct current voltage source
EU	Negative terminal of inverter circuit U-phase external DC voltage source
		EV	Negative terminal of inverter circuit V-phase external DC voltage source
EW	W-phase external DC voltage source negative terminal of inverter circuit
		U	Inverter circuit U-phase output
V	Inverter circuit V-phase output
		W	W-phase output of inverter circuit
B	Brake circuit output
		GB	Braking circuit gate input
G1	Inverter circuit U-phase upper bridge arm grid input
		G2	Inverter circuit U-phase lower bridge arm grid input
G3	Inverter circuit V-phase upper bridge arm grid input
		G4	Inverter circuit V-phase lower bridge arm grid input
G5	Inverter circuit W-phase upper bridge arm grid input
		G6	Inverter circuit W-phase lower bridge arm grid input

The internal equivalent circuit of the low parasitic inductance Si-SiC power integrated module is shown in figure 1, and a three-phase rectification circuit 3, a brake circuit 2 and a three-phase inverter circuit 1 are sequentially arranged from left to right.

The three-phase alternating current power supply is connected to alternating current input pins L1, L2 and L3 of the three-phase rectification circuit 3, the three-phase rectification circuit 3 is composed of six silicon-based rectifier diodes, and rectified direct current signals are led out through direct current voltage source pins P and N.

The brake circuit 2 is composed of a silicon-based IGBT chip and a silicon-based FRD chip, a grid GB of the IGBT is connected with an external control signal to control the on-off of the IGBT, an emitting electrode NB of the IGBT is externally connected with a negative electrode of a direct current voltage source, a negative electrode P1 of the silicon-based FRD chip is externally connected with a positive electrode of the direct current voltage source, and the positive electrode of the silicon-based FRD chip is connected with a collector electrode of the silicon-based IGBT chip and is led out through a pin B.

The three-phase inverter circuit 1 is composed of six silicon-based IGBT chips and six silicon carbide-based SBDs and is divided into three phases of U, V and W, each IGBT is connected with one SBD in parallel to form a bridge arm, an upper bridge arm and a lower bridge arm are connected in series to form one phase, each IGBT is controlled to be switched on and switched off through an external grid driving signal, a collector electrode of the upper bridge arm IGBT is connected with positive electrodes P1, P2 and P3 of an external direct-current voltage source, an emitter electrode of the lower bridge arm IGBT is connected with negative electrodes EU, EV and EW of the external direct-current voltage source, pin electrodes U, V and W are led out through connecting points of the upper bridge arm and the lower bridge arm (namely connecting points of the emitter electrode of the upper bridge arm and the collector electrode of the lower bridge arm) to be externally connected with a three-phase load, and grid pins G1, G2, G3, G4, G5 and G6 of the six IGBTs are connected with external control signals to control the on-off of the IGBTs. When the three-phase inverter circuit 1 works, the power commutation loop of each phase is staggered, namely the upper bridge arm IGBT and the lower bridge arm SBD form a power commutation loop, the lower bridge arm IGBT and the upper bridge arm diode IGBT form another power commutation loop, the whole inverter circuit has six power commutation loops in total, the parasitic inductance of the loops is reduced, and the corresponding power commutation loop path is required to be reduced.

The top view and the side view of the internal layout of the low parasitic inductance Si-SiC power integrated module are shown in fig. 2 and fig. 3, and in order to make the internal layout structure appear more clearly, the bonding wires are removed and the names of the leads are marked in fig. 4. The internal structure of the module comprises a silicon-based IGBT chip, a silicon carbide SBD chip, a silicon-based FRD chip, a silicon-based rectifier diode chip, a copper-clad ceramic substrate (DBC), a solder layer, a bonding lead, a copper gasket, a pin electrode and the like. Pins U, V, W, G1, G3, L1 are located at the upper edge of the DBC, and EU, EV, EW, G2, G4, G6, GB, N are located at the lower edge of the DBC.

A three-phase inverter circuit 1, a brake circuit 2 and a three-phase rectification circuit 3 are sequentially distributed on a copper-clad ceramic substrate 11 from left to right, wherein the three-phase inverter circuit 1 occupies more than half of the area. Etching a plurality of copper substrates on a copper-clad ceramic substrate 11 to serve as a wiring layer, coating a solder layer 13 on the surface of the wiring layer of the copper substrates, respectively attaching the back surfaces (namely a cathode and a collector) of a silicon-based diode FRD chip, a silicon carbide diode SBD, a silicon-based rectifier diode chip and a silicon-based IGBT chip to corresponding positions on the DBC copper substrate downwards, welding pins 16 on corresponding positions on the wiring layer of the copper substrates, and welding the copper substrates with the pin electrodes to serve as lead frame copper substrates. In the examples, the connection relationship of the respective copper substrates will be described, and reference numerals 4 to 9, 15, 17 to 21 are referred to. Wherein, the copper substrates 4-7 are positioned at the left side of the copper-clad ceramic substrate 11, the copper substrates 17-21 are positioned at the right side of the copper-clad ceramic substrate 11, and the

copper substrates

8,9 and 15 are clamped between the copper substrates.

As shown in fig. 4, the three-phase inverter circuit 1 includes three phases U, V, and W, and each phase includes two upper and lower arms. The third IGBT chip 1-3 and the third SBD chip 1-9 form an upper bridge arm of a U phase, and the sixth IGBT chip 1-6 and the sixth SBD chip 1-12 form a lower bridge arm of the U phase. The second IGBT chip 1-2 and the second SBD chip 1-8 form an upper bridge arm of a V phase, and the fifth IGBT chip 1-5 and the fifth SBD chip 1-11 form a lower bridge arm of the V phase. The first IGBT chip 1-1 and the first SBD chip 1-7 form an upper bridge arm of a W phase, and the fourth IGBT chip 1-4 and the fourth SBD chip 1-10 form a lower bridge arm of the W phase.

In the three-phase inverter circuit 1, IGBT chips and SBD chips of three upper bridge arms of U, V and W phases are welded on the same copper substrate 7, collectors of a third IGBT chip 1-3 of the U phase, a second IGBT chip 1-2 of the V phase and a first IGBT chip 1-1 of the W phase are welded on the copper substrate 7, and cathodes of a third SBD chip 1-9 of the U phase, a second SBD chip 1-8 of the V phase and a first SBD chip 1-7 of the W phase are welded on the copper substrate 7. And a pin electrode P3 is led out from the right side of the first SBD chip 1-7 and is used as an external direct-current voltage anode of the W phase. And a pin electrode P2 is led out from the right side of the second SBD chip 1-8 and is used as an external direct-current voltage anode of a V phase. And a pin electrode P1 is led out from the right side of the second SBD chip 1-9 and is used as an external direct-current voltage anode of the U phase. The three electrodes P1, P2 and P3 adopt two electrodes as a group to improve the current capacity because the passing current is large. In order to reduce loop inductance, three pin electrodes need to be close to an SBD chip as much as possible, the U, V and W three-phase chips and the pin electrodes are equidistant as much as possible to ensure that the areas of the three-phase loops are consistent, internal wiring of an external direct current voltage source added into an inverter circuit is effectively ensured to be the same, the three-phase power current conversion loops are identical in structure, and a current backflow path is minimum, so that parasitic inductance of the three-phase inverter circuit is reduced, the sizes of the three-phase parasitic inductances are basically consistent, and balanced three-phase operation is ensured. The three groups of pin electrodes are kept consistent as much as possible, and because the U phase and the braking circuit FRD share one group of electrodes, the inductance of the U phase loop is considered to be small, and meanwhile, the inductance of the braking circuit loop is also small, and the positions of the braking circuit loop can be slightly different.

Emitting electrodes of an IGBT chip of the U, V and W three-phase upper bridge arm are connected with an anode of the SBD chip through bonding wires, each emitting electrode is connected with a corresponding lead frame copper substrate through three bonding wires, and corresponding pin electrodes U, V and W are led out of the lead frame copper substrate. And each grid of the IGBT chip of the U, V and W three-phase upper bridge arm is respectively connected with a corresponding lead frame copper substrate through a bonding wire, and corresponding pin electrodes G1, G3 and G5 are led out of the lead frame copper substrate. IGBT chips in each phase are distributed on two sides of the substrate, the SBD chips are placed close to the middle, and the grid electrodes of the IGBT chips are made to be close to the outer sides, so that the length of grid electrode lead wires of each IGBT chip is shortest, and grid electrode inductance is reduced. And the layout of each phase is basically kept consistent, so that the three-phase electro-thermal parameters are ensured to be consistent, and the balanced work can be realized.

The anode of a third SBD chip 1-9 of the U-phase upper bridge arm is connected to a lower bridge arm copper substrate 6 through a bonding wire, the collector of a sixth IGBT chip 1-6 of the U-phase lower bridge arm and the cathode of the sixth SBD chip 1-12 are welded on the copper substrate 6, the emitter of the sixth IGBT chip 1-6 and the anode of the sixth SBD chip 1-12 are connected through the bonding wire, the emitter of the sixth IGBT chip 1-6 and the grid are connected to a corresponding lead frame copper substrate through the bonding wire, and corresponding pin electrodes EU and G2 are led out of the copper substrate.

The anode of a second SBD chip 1-8 of the V-phase upper bridge arm is connected to a lower bridge arm copper substrate 5 through a bonding wire, the collector of a fifth IGBT chip 1-5 of the V-phase lower bridge arm and the cathode of a fifth SBD chip 1-11 are welded on the copper substrate 5, the emitter of the fifth IGBT chip 1-5 and the anode of the fifth SBD chip 1-11 are connected through the bonding wire, the emitter of the fifth IGBT chip 1-5 and the grid are connected to corresponding lead frames copper substrates through the bonding wire, and corresponding pin electrodes EV and G4 are led out of the copper substrates.

The anode of a first SBD chip 1-7 of the W-phase upper bridge arm is connected to a lower bridge arm copper substrate 4 through a bonding wire, the collector of a fourth IGBT chip 1-4 of the W-phase lower bridge arm and the cathode of the fourth SBD chip 1-10 are welded on the copper substrate 4, the emitter of the fourth IGBT chip 1-4 and the anode of the fourth SBD chip 1-10 are connected through the bonding wire, the emitter and the grid of the fourth IGBT chip 1-4 are connected to the corresponding lead frame copper substrate through the bonding wire, and corresponding lead electrodes EW and G6 are led out of the lead frame copper substrate.

The brake circuit 2 is composed of a seventh silicon-based IGBT chip 2-1 and a silicon-based FRD chip 2-2, and a local double-layer substrate structure is adopted.

The cathode of an FRD chip 2-2 in the brake circuit 2 and the upper bridge arm of the three-phase inverter circuit 1 are welded on the same copper substrate 7, the FRD chip 2-2 is positioned on the right side of the SBD chip 1-9, and a pin electrode P1 of the U phase of the three-phase inverter circuit 1 and the positive electrode of an external direct current voltage source shared by the brake circuit 2 is led out between the FRD chip 2-2 and the SBD chip 1-9. The collector of the seventh silicon-based IGBT chip 2-1 in the braking circuit 2 is welded on the copper substrate 8, and the copper substrate 8 is connected with the anode of the silicon-based FRD chip 2-2 through a bonding wire. The grid electrode of the seventh silicon-based IGBT chip 2-1 is connected to the corresponding lead frame copper substrate 15 through a bonding wire, and a corresponding pin electrode GB is led out. As shown in fig. 5 and 6, the emitter of the seventh silicon-based IGBT chip 2-1 is connected to the copper pad 14 through the copper sheet 10, the copper pad 14 and the seventh silicon-based IGBT chip 2-1 have the same thickness, the copper pad 14 is welded to the copper substrate 9, and the pin electrode NB is led out of the copper substrate 9 and is externally connected to the negative electrode of the dc bus. The copper sheet 10 is equivalent to a copper substrate to replace a bonding wire from an emitter to a lead frame copper substrate in the traditional packaging mode, so that the module forms a local double-layer substrate structure, and the common emitter parasitic inductance of the braking circuit 2 is reduced. Meanwhile, the grid is arranged at the lower right corner of the IGBT chip, is close to the lower edge of the DBC and is connected to the copper substrate at the lower edge of the DBC through a bonding wire, and therefore grid loop parasitic inductance of the braking circuit is reduced.

The three-phase rectification circuit 3 is composed of six silicon-based rectifier diode chips, each two of the six silicon-based rectifier diode chips form three phases, each group is divided into an upper arm and a lower arm, cathodes of three silicon-based rectifier diodes of the upper arm of the three phases are connected together to form a common cathode group, and anodes of three silicon-based rectifier diodes of the lower arm of the three phases are connected together to form a common anode group. The upper bridge arm common cathode group consists of silicon-based rectifier diode chips 3-4, 3-5 and 3-6, and the lower bridge arm common anode group consists of silicon-based rectifier diode chips 3-1, 3-2 and 3-3.

Cathodes of three silicon-based rectifier diode chips of an upper bridge arm common cathode group of the three-phase rectifier circuit 3 are welded on the same copper substrate 20, and a pin electrode P is led out from the lower part of the copper substrate 20 and serves as a positive electrode of rectification output. The cathodes of the silicon-based rectifier diode chips of the lower bridge arm common anode group are welded on three different copper substrates 17, 18 and 19, the copper substrate 17 is connected with the silicon-based rectifier diode chips 3-4 through bonding wires, the copper substrate 18 is connected with the silicon-based rectifier diode chips 3-5 through the bonding wires, the copper substrate 19 is connected with the silicon-based rectifier diode chips 3-6 through the bonding wires, pin electrodes L1, L2 and L3 are respectively led out of the copper substrates 17, 18 and 19, and the three-phase alternating current power supply is externally connected. Anodes of the silicon-based rectifier diode chips 3-1, 3-2 and 3-3 of the common anode group are connected together through bonding wires and are finally connected to a lead frame copper substrate 21 with a relatively large area (the loss resistance is reduced when the limited space area is larger), and a pin electrode N led out from the copper substrate 21 is used as a cathode of the rectifier output.

In the embodiment of the invention, in order to improve the thermal performance, the area of an inverter circuit module is enlarged, and three phases work independently, a bridge arm copper substrate 7 on the inverter circuit does not adopt a standard rectangular area, but five small rectangles (the length is used as the transverse dimension, and the width is used as the longitudinal dimension) are cut off from a rectangular area with the length of 36-37mm and the width of 15-16mm, wherein the length of the cut rectangle at the lower left corner is 10-10.5mm, the width is 1.9-2.1mm, the length of the cut rectangle at the upper right corner is 6-6.4mm, the width is 6-6.4mm, the length of the cut rectangle at the lower right corner is 2.8-3.1mm, the width is 6.8-7.2mm, and the rectangle with the length of 13.8-14.2mm and the width is 1.9-2.1mm is cut off at the left side of the rectangle. The IGBT chip is 8mm multiplied by 8mm, the SBD chip is 3mm multiplied by 3mm, the distance between the first IGBT chip 1-1 and the left side of the copper substrate 7 is 0.5-0.6mm, the distance between the first IGBT chip 1-1 and the upper side is 0.5-0.6mm, the distance between the IGBT chips is about 2-2.4mm, the distance between the first SBD chip 1-7 and the left side of the copper substrate is 3-3.4mm, the distance between the first SBD chip and the lower side is 3-3.4mm, and the distance between the diodes is 7-7.5mm. And a rectangle with the length of 11-11.5mm and the width of 1.4mm-1.6mm is cut along the copper substrate 7 between the first IGBT chip 1-1 and the third IGBT chip 1-3, so that the position of the upper bridge arm V-phase chip is slightly staggered with the U-phase chip and the W-phase chip.

And a U-phase lower bridge arm copper substrate 6, a V-phase lower bridge arm copper substrate 5 and a W-phase lower bridge arm copper substrate 4 are respectively arranged below the upper bridge arm copper substrate 7 from right to left. The U-phase lower bridge arm copper substrate 6 is 9-9.5mm long and 15-16mm wide, a square is cut at the upper right corner, and the side length is 4-4.3mm. The length of the V-phase lower bridge arm copper substrate 5 is 9-9.5mm, and the width of the V-phase lower bridge arm copper substrate is 13-14mm. The W-phase lower bridge arm copper substrate 4 is 9-9.5mm long and 15-16mm wide. The distance between the copper substrates of the lower bridge arms is 0.8-1.1mm.

The brake circuit IGBT chip copper substrate 8 is located on the right side of the U-phase lower bridge arm copper substrate 6, two rectangles are cut in a rectangular area which is 13.5-14mm long and 15-16mm wide, wherein a rectangle which is 5.5-6mm long and 3-3.5mm wide is cut in the lower left corner, and a rectangle which is 10-11mm long and 7-7.5mm wide is cut in the upper right corner vertically.

The copper substrate 20 where the common cathode group of the upper bridge arm of the three-phase rectification circuit 3 is located is 4.9-5.1mm long and 22-23mm wide and is located at the right edge of the DBC. The copper substrates 17, 18 and 19 of the common anode group of the lower bridge arm on the left side are arranged from top to bottom. Three small rectangles are cut off from a rectangular area of the copper substrate 17 with the length of 15-16mm and the width of 9.5-10mm, the rectangle with the length of 3-3.5mm and the width of 3.8-4.4mm is cut off from the upper left corner, the rectangle with the length of 9.5-10mm and the width of 2.8-3.1mm is cut off from the lower right corner, and the rectangle with the length of 5.8-6.3mm and the width of 3.8-4.1mm is cut off from the adjacent upper right corner. Two small rectangles are cut off from the rectangular area with the length of 12.5-13.1mm and the width of 8.8-9.1mm of the lower bridge arm common anode group copper substrate 18, the rectangle with the length of 9.8-10.1mm and the width of 2.8-3.1mm is cut off at the upper left corner, and the rectangles are adjacent and then cut off downwards to form a rectangle with the length of 2.8-3.1mm and the width of 5.4-5.6 mm. The length of the copper substrate 19 of the lower bridge arm common anode group is 12.8-13.2mm, and the width is 5.8-6.2mm. The minimum spacing of the copper substrates is 0.9-1.1mm.

In the embodiment, the pin electrode 16 is cylindrical, the diameter is 0.64-0.70mm, the height is 10-14mm, one gate pin electrode is provided, one emitter pin electrode of the brake circuit IGBT chip is provided, other pin electrodes are provided in a group, and the distance between the two pins is 1.8-2.4mm.

In the embodiment, the gate current of the IGBT chip is very small, one bonding wire is used for connection, and the current of a power loop in the three-phase inverter circuit 1 is very large, so that three bonding wires are connected into a group to improve the through-current capacity and reduce the loop inductance at the same time. The power loop current of the brake circuit 2 is smaller than that of the three-phase inverter circuit 1, and two bonding wires of the silicon-based FRD chip and the copper substrate are used in one group. The current passing through the rectifying circuit 3 is large, and four bonding wires are used in one group. The bonding wire is made of aluminum, the diameter of the bonding wire is 0.3-0.32mm, the length of the bonding wire is 4.8-5.2mm, and the height of the bonding wire is 0.3-0.56mm.

The upper arm power commutation circuit of the three-phase inverter circuit 1 of the present invention is shown in fig. 7, and fig. 8 shows the upper arm power commutation circuit of the three-phase inverter circuit of the conventional module. The power commutation path is a path with the minimum impedance of the power loop, and under the direct current excitation, the impedance is mainly resistance, so that the backflow path is a path with the minimum resistance, namely a straight line segment connecting terminals of each power device. In the invention, the parasitic inductance brought by the internal layout of the module is considered, and excitation is applied to the positive and negative positions of the external direct-current voltage Source, namely the input end (Source) and the output end (Sink) of the excitation Source are marked in the figure. In the traditional module, an upper bridge arm and a brake circuit share a direct current bus positive pin electrode, the pin electrode is close to a collector electrode of an IGBT chip of the upper bridge arm of a U phase, but is far away from a V phase and a W phase, so that a U-phase power commutation loop is minimum, a W-phase commutation loop is maximum, and a part of the power commutation loops of the V phase and the W phase is overlapped, namely the part of current is twice of single-phase current. Therefore, the parasitic inductance of the power commutation loop, namely the parasitic inductance of the phase W, is very large, and the parasitic inductance of the phase U is relatively small, which causes a large voltage overshoot to be generated at the turn-off moment of the phase W and the phase V IGBT chips, and in addition, the current of the overlapped part is doubled, the variation of the current is doubled, and the voltage overshoot of the phase V and the phase W is further increased. In the fig. 7, different direct current bus pins are adopted for the three phases of U, V and W of the Si-SiC power integrated module inverter circuit with low parasitic inductance, each power commutation loop is completely independent, a direct current bus positive electrode pin electrode abuts against the upper bridge arm IGBT chip collector, each phase of power commutation loop is very small, and the shapes of the three phases are basically consistent, so that the parasitic inductance is small, and the parasitic inductance difference of each phase is small. The voltage overshoot generated at the moment of turning off the collectors of the U, V and W three-phase IGBT chips is small, and the working states of the three-phase IGBT chips are balanced.

The power commutation loop of the lower bridge arm of the three-phase inverter circuit is not shown, and because the lower bridge arm IGBT chip and the upper bridge arm SBD chip form the commutation loop, the commutation loop only needs to pass through the silicon carbide-based SBD chips 1-7, 1-8 and 1-9 when passing through the upper bridge arm, the uppermost IGBT chips 1-1, 1-2 and 1-3 are not needed, and the commutation loop is smaller than the upper bridge arm IGBT chip commutation loop.

In the embodiment, the grid of the brake circuit IGBT chip is placed on the lower right side, so that the distance between the grid and the lead frame is short, and the grid parasitic inductance is reduced by adopting a shorter bonding wire. An emitter of the brake circuit IGBT chip adopts a copper sheet to replace a bonding wire, the length of a current path is not changed greatly, but the conductive area is increased, so that the parasitic inductance of the emitter is reduced.

In order to verify the characteristic of low parasitic inductance of the embodiment of the invention, a certain commercial module and the parasitic inductance of the embodiment of the invention are simulated by software modeling, the parasitic inductance of a power loop given in a commercial module data manual is 30nH, the parasitic inductances of the U, V and W three-phase upper bridge arm power loops of the commercial module for modeling simulation are respectively 18.88nH, 23.40nH and 29.48nH, and the parasitic inductances of the U, V and W three-phase lower bridge arm power loops are respectively 15.82nH, 20.24nH and 26.41nH. The parasitic inductances of the U, V and W three-phase upper bridge arm power circuits of the modeling simulation are 14.22nH, 12.92nH and 14.496nH respectively, and the parasitic inductances of the U, V and W three-phase lower bridge arm power circuits are 17.56nH, 16.08nH and 17.68nH respectively. The simulated commercial module braking circuit grid parasitic inductance is 9.28nH, the common emitter parasitic inductance is 3.77nH, the simulated embodiment of the invention has the braking circuit grid parasitic inductance of 3.80nH and the common emitter parasitic inductance of 1.77nH. The parasitic inductance of the inverter circuit power loop is reduced by 30.8% on average, the maximum value is reduced by 40.0%, and meanwhile, the difference of the parasitic inductances of six three-phase power loops is reduced to 26.9% from the original 46.4%. The gate inductance and emitter inductance of the braking circuit are reduced by 59.1% and 53.1%, respectively.

According to the Si-SiC power integrated module structure with low parasitic inductance, the silicon carbide-based SBD is adopted in the inverter circuit, so that the recovery loss of the circuit is reduced, more space is reserved for other circuits, and the heat dissipation area is enlarged. Three pin electrodes are led out from an upper bridge arm of the inverter circuit, so that the U, V and W three-phase power current conversion loops are mutually independent, the length of the current conversion loop is reduced, and the three phases are uniform, thereby realizing the characteristics of reduction and uniformity of parasitic inductance. The layout structure is optimized in the braking circuit, the length of a grid conductor is reduced, parasitic inductance is reduced, a local double-layer substrate structure is adopted to replace a bonding wire of an emitter, and the parasitic inductance of the common emitter is greatly reduced, so that the switching performance of a power module is improved, the voltage process quantity in the switching process is reduced, the loss is reduced, and meanwhile, the heat dissipation performance of the power module is utilized.

Claims

1. A low parasitic inductance Si-SiC power integrated module comprises a three-phase inverter circuit (1), a brake circuit (2) and a three-phase rectifier circuit (3) which are manufactured on a copper-clad ceramic substrate (11), wherein the three-phase inverter circuit (1) comprises six silicon-based IGBT chips and six silicon carbide SBD chips, one silicon-based IGBT chip and one silicon carbide SBD chip form one group, six groups are formed, two groups form a phase circuit, three phases are formed, the groups are respectively called as a U phase, a V phase and a W phase, and the upper group and the lower group in each phase are respectively called as an upper bridge arm and a lower bridge arm; the brake circuit (2) comprises a silicon-based IGBT chip and a silicon-based FRD chip; the three-phase rectifying circuit (3) comprises six silicon-based rectifying diodes, each two of which form three phases, each group is divided into an upper arm and a lower arm, the cathodes of the three silicon-based rectifying diodes on the upper arm of the three phases are connected together to form a common cathode group, and the anodes of the three silicon-based rectifying diodes on the lower arm of the three phases are connected together to form a common anode group; the copper-clad ceramic substrate is characterized in that a plurality of copper substrates are etched on the surface of a copper-clad ceramic substrate (11) to serve as wiring layers, and pin electrodes serving as lead frames are welded on one part of the copper substrates; in the three-phase inverter circuit (1), each phase of U, V and W is provided with a special direct current bus pin electrode, an upper bridge arm is welded on the same copper substrate, three groups of pin electrodes are led out and externally connected with the anode of a direct current voltage source, a lower bridge arm is welded on three different copper substrates, each phase is respectively connected to three different lead frame copper substrates through a bonding wire, three groups of pin electrodes are led out respectively and externally connected with the cathode of the direct current voltage source; the cathode of a silicon-based FRD chip in the braking circuit (2) is welded on a copper substrate where an upper bridge arm of the three-phase inverter circuit (1) is located, is close to the U-phase upper bridge arm chip, and shares the same pin electrode with the U-phase upper bridge arm to be externally connected with the anode of a direct-current voltage source; the collector of the silicon-based IGBT chip in the braking circuit (2) is welded on another copper substrate, the copper substrate is connected with the anode of the silicon-based FRD chip through a bonding wire, and an output pin electrode of the braking circuit (2) is led out; a lead frame copper substrate (9) externally connected with the negative electrode of a direct current voltage source is arranged beside an emitting electrode of a silicon-based IGBT chip in the braking circuit (2), and the emitting electrode of the silicon-based IGBT chip is connected with the lead frame copper substrate (9) externally connected with the negative electrode of the direct current voltage source through a copper sheet (10).

2. The low parasitic inductance Si-SiC power integration module of claim 1, wherein: the copper-clad ceramic substrate (11) is sequentially provided with a three-phase inverter circuit (1), a brake circuit (2) and a three-phase rectifier circuit (3) from left to right.

3. The low parasitic inductance Si-SiC power integration module of claim 2, wherein: collectors of three silicon-based IGBT chips of U, V and W three-phase upper bridge arms and cathodes of three silicon-based SBD chips in the three-phase inverter circuit (1) are welded on the same copper substrate, the three groups of chips are arranged side by side from left to right and are consistent in layout, the three silicon-based IGBT chips are positioned on one side close to the upper edge of the copper-clad ceramic substrate (11), grids of the IGBT chips are outward, the three silicon-based SBD chips are correspondingly positioned at equal intervals below the three silicon-based IGBT chips, three groups of pin electrodes are respectively led out from the copper substrate on the right side of the three silicon-based SBD chips and serve as positive pins of DC voltage sources of the U, V and W three phases, and the pin electrodes are two in one group; the emitting electrodes of the three IGBT chips of the upper bridge arm are connected with the anodes of the three silicon carbide-based SBD chips through bonding wires, and the anodes of the silicon carbide-based SBD chips are connected to the copper substrate of the lower bridge arm through the bonding wires.

4. The low parasitic inductance Si-SiC power integration module of claim 3, wherein: the three silicon-based IGBT chips and the three silicon-based SBD chips of the lower bridge arm of the three-phase inverter circuit (1) are grouped in pairs and are respectively positioned below the phase chip of the upper bridge arm, the three groups of chips are also arranged side by side from left to right and are consistent in layout, wherein the three silicon-based IGBT chips are positioned on one side close to the lower edge of the copper-clad ceramic substrate (11), the grid electrodes of the silicon-based IGBT chips face outwards, and the three silicon-based SBD chips are correspondingly positioned at equal intervals above the three silicon-based IGBT chips; the three groups of chips are positioned on three different copper substrates, wherein a collector of the silicon-based IGBT chip and a cathode of the SBD chip are welded on the copper substrate, an emitter of the silicon-based IGBT chip and an anode of the silicon carbide SBD chip are connected through bonding wires, the emitter of the IGBT chip is connected to the three lead frame copper substrates through the bonding wires, and a group of pin electrodes externally connected with a direct current voltage source cathode is led out of each copper substrate.

5. The low parasitic inductance Si-SiC power integration module of claim 1, wherein: in the three-phase inverter circuit (1), different direct current bus pin electrodes are adopted for the U, V and W phases, the direct current bus pin electrodes are positioned at the edge of the copper-clad ceramic substrate (11) and are close to the corresponding silicon-based IGBT chips, power commutation loops of each phase are mutually independent, and the path shapes of the commutation loops are kept consistent.

6. The low parasitic inductance Si-SiC power integration module of claim 2, wherein: in the braking circuit (2), a lead frame copper substrate (9) externally connected with a negative pole of a direct current voltage source is positioned between a silicon-based IGBT chip and a three-phase rectification circuit (3), a copper gasket (14) with the thickness the same as that of the silicon-based IGBT chip is arranged on the lead frame copper substrate (9) externally connected with the negative pole of the direct current voltage source, a copper sheet (10) is welded on the upper surfaces of an emitting electrode of the silicon-based IGBT chip and the copper gasket (14) to connect the emitting electrode and the copper gasket to form a double-layer substrate structure, a pin electrode of the emitting electrode of the IGBT silicon-based chip of the braking circuit (2) is led out through the lead frame copper substrate (9) externally connected with the negative pole of the direct current voltage source, and the negative pole of an external direct current bus is connected; the grid of the silicon-based IGBT chip of the braking circuit (2) is close to the lower edge of the copper-clad ceramic substrate (11) and is connected to the copper substrate of the lead frame at the lower edge through a bonding wire.

7. The low parasitic inductance Si-SiC power integration module of claim 2, wherein: in the three-phase rectifying circuit (3), the cathodes of three silicon-based rectifying diode chips of an upper arm common cathode group of three phases are welded on the same copper substrate, a pin electrode is led out of the copper substrate and is used as the anode of a rectifying output, the cathodes of the three silicon-based rectifying diode chips of the lower arm common anode group are respectively welded on the three copper substrates, the anodes of the upper arm silicon-based rectifying diode chips are respectively connected to the three copper substrates on which the lower arm silicon-based rectifying diode chips are positioned through bonding wires, and the three copper substrates are led out of three groups of corresponding pin electrodes and are externally connected with a three-phase alternating current power supply; the anodes of the three diodes of the lower arm are connected together by bonding wires and to another separate copper substrate from which a pin electrode is drawn as the negative pole of the rectified output.