CN115862528A - Splicing display method and device, LED splicing controller, storage medium and system - Google Patents

Abstract

The application provides a splicing display method, a splicing display device, an LED splicing controller, a storage medium and a splicing display system, and relates to the technical field of display. The method comprises the following steps: acquiring a preset resolution and a preset frame rate corresponding to each display component; determining a target candidate clock which satisfies that the quotient of dividing the preset frame rate of any display component is greater than or equal to the product of the preset effective width and the preset effective height of any display component; determining the smallest one of the target candidate clocks as a target clock; determining a target resolution corresponding to each display component based on the target clock; and sending the sub-video image to each display assembly according to the target resolution corresponding to each display assembly, so that each display assembly displays the sub-video image according to the corresponding target resolution. The method is suitable for the splicing display process and used for solving the problem of poor splicing display flexibility.

Description

Splicing display method and device, LED splicing controller, storage medium and system

Technical Field

The application relates to the technical field of display, in particular to a splicing display method, a splicing display device, an LED splicing controller, a storage medium and a splicing display system.

Background

A Light Emitting Diode (LED) tiled display system includes a video source, a tile, and one or more LED display components. A video source may output multiple video images. The video image splicing controller can splice a plurality of video images output by the video source into one video image and then divide the video image into a plurality of video images, and the divided video images are respectively sent to one or a plurality of LED display assemblies. Each LED display component can respectively display a corresponding video image, and the video images displayed by one or more LED display components are combined together to form a video image spliced by the splicing controller.

In order to ensure that the video images displayed by one or more LED display components are normal and smooth and the phenomenon of picture asynchronism between spliced seams such as tearing does not exist, the video images are embedded in a standard resolution ratio by the splicing controller after being spliced and divided, the clock phase output to each LED display component is ensured to be synchronous, and then the video images are displayed on the LED display components according to the standard resolution ratio.

However, the clock of the segmented video image is usually smaller than the clock of the corresponding nested standard resolution, and the larger the clock is, the higher the requirement on the data transmission link is, and the clock is increased by nesting the segmented video image in the standard resolution, so that the requirement on the data transmission link is also increased. And after the LED display assembly receives the video image nested in the standard resolution, the LED display assembly further needs to perform cropping and segmentation on the portion of the standard resolution outside the video image in the effective width and the effective height, that is, the video image nested in the standard resolution requires the LED display assembly to have the cropping and segmentation function. Therefore, the scheme of nesting video images in a standard resolution has high requirements on data transmission links and LED display components, and the scheme has low flexibility.

Disclosure of Invention

Based on the foregoing technical problems, the present application provides a tiled display method, apparatus, LED tiled controller, storage medium and system, which can generate a set of customized resolutions (detailed time sequence) for each potential display wide-high frame rate (W × H P/I FPS), and the generated customized resolutions have a smaller clock, so as to implement synchronous output of one or more display components, reduce requirements on data transmission links and display components, and improve flexibility of a tiled display scheme.

In a first aspect, the present application provides a tiled display method, the method being applied to a tile connected to one or more led display elements, the method comprising: acquiring a preset resolution and a preset frame rate corresponding to each display component; the preset resolution comprises a preset effective width and a preset effective height; determining one or more target candidate clocks according to the preset frame rate of each display component; the target candidate clock is a clock satisfying the following first condition: dividing the quotient of the preset frame rate of any display component by more than or equal to the product of the preset effective width and the preset effective height of any display component; determining a smallest target candidate clock of the one or more target candidate clocks as a target clock of the one or more display components; determining a target resolution corresponding to each display component based on the target clock; sending the sub-video image to each display assembly according to the target resolution corresponding to each display assembly, so that each display assembly displays the sub-video image according to the corresponding target resolution; the sub-video images are obtained by segmenting the video images through the mosaic controller, and the sub-video images displayed by each display assembly are spliced together to obtain the video images.

According to the tiled display method provided by the embodiment of the application, the target resolution corresponding to each display component can be generated for each display component according to the preset effective width, the preset effective height and the preset frame rate required to be displayed by each display component, and for the display components with different preset effective widths, different preset effective heights and different preset frame rates, the tiled controller firstly determines the target candidate clocks meeting each display component, selects the smallest one from the target candidate clocks as the target clock, and generates the target resolution corresponding to each display component based on the smallest target clock. And because the target clock is smaller, the product of the effective width and the effective height in the target resolution determined based on the target clock is smaller, the area of the effective display area corresponding to the target resolution is smaller, and the area of the effective display area corresponding to the preset resolution is better fit, after the video image is transmitted to the display assembly by the splicing controller according to the target resolution, the display assembly (or a sending card in the display assembly) does not need to cut and segment the received video image, the requirement on the function of the display assembly is reduced, and the flexibility of the splicing display scheme is improved.

In addition, target clocks in target resolutions corresponding to the multiple display components are the same, clocks of the mosaic controller under any resolution are consistent, and frame asynchronism among video images displayed by the multiple display components cannot be caused by clock (or pixel frequency) deviation (offset frequency).

In one possible implementation, determining one or more candidate clocks according to a preset frame rate of each display component includes: determining a plurality of initial clocks from a plurality of clocks between a minimum clock and a maximum clock according to a preset clock stepping precision; presetting clock stepping precision for indicating the clock interval of adjacent initial clocks; determining one or more initial candidate clocks meeting a second condition from the plurality of initial clocks according to the number of the quotient factors obtained by dividing each initial clock by the preset frame rate of any display component and the second condition; the second condition is that: the number of quotient factors obtained by dividing the preset frame rate of any display component is larger than the number threshold; one or more target candidate clocks are determined from the one or more initial candidate clocks based on initial resolutions corresponding to the one or more initial candidate clocks, each initial candidate clock corresponding to one or more initial resolutions.

Optionally, determining one or more initial candidate clocks satisfying a second condition from the plurality of initial clocks according to the number of factors of a quotient obtained by dividing each initial clock by the preset frame rate of any one display component and the second condition, includes: acquiring one or more first initial clocks of which the number of quotient factors obtained by dividing the preset frame rate of any display component is larger than a number threshold from the plurality of initial clocks, and determining initial candidate clocks from the one or more first initial clocks; determining one or more target candidate clocks from the one or more initial candidate clocks based on an initial resolution corresponding to the one or more initial candidate clocks, including: if the initial candidate clocks meeting the first condition are included in the one or more initial candidate clocks, one or more target candidate clocks are determined from the one or more initial candidate clocks based on the initial resolution corresponding to the one or more initial candidate clocks.

Optionally, the method further comprises: if the initial candidate clock meeting the first condition is not included in the one or more initial candidate clocks, acquiring one or more second initial clocks, wherein the number of quotient factors obtained by dividing the preset frame rate of any display component in the initial clocks is smaller than or equal to a number threshold value; one or more initial candidate clocks are determined from the one or more second initial clocks.

Optionally, determining one or more initial candidate clocks from the one or more first initial clocks comprises: taking a first initial clock which is the same as the standard clock in the one or more first initial clocks as an initial candidate clock; determining one or more initial candidate clocks from the one or more second initial clocks, including: and taking the first initial clock which is the same as the standard clock in the one or more first initial clocks as the initial candidate clock.

Optionally, the one or more initial candidate clocks comprise a first clock, and the preset frame rate of the one or more display components is the first frame rate; before determining one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, the method further includes: performing one or more times of factorization on a first area obtained by dividing a first clock by a first frame rate, and decomposing the first area into two factors each time; for each factorization, taking one of two factors obtained by factorization as a maximum width, and taking the other of the two factors obtained by factorization as a maximum height; determining an effective width according to the maximum width and determining an effective height according to the maximum height; one of a plurality of initial resolutions is generated based on the maximum width, the maximum height, the effective width, and the effective height.

Optionally, the one or more display elements include M rows and N columns of display elements, M and N are integers greater than or equal to 1, and when N is greater than or equal to 2, the method further includes: and adjusting the horizontal front shoulder HFP in the target resolution corresponding to each line of display components in the M lines, so that the horizontal blanking size of each line of display components in the M lines is decreased gradually from left to right.

It will be appreciated that when each of the M rows of display elements comprises a plurality, reducing the horizontal blanking of that row of display elements may reduce the lack of synchronisation between adjacent display elements of a row due to scanning precedence.

In a second aspect, the present application provides a tiled display arrangement comprising modules for use in the method of the first aspect described above.

In a third aspect, the present application provides an LED tile comprising a processor and a memory; the memory stores instructions executable by the processor; the processor is configured to execute the instructions to cause the LED mosaic to implement the method of the first aspect described above.

In a fourth aspect, the present application provides a computer program product for causing a mosaic device to perform the steps of the method according to the first or third aspect, when the computer program product is run on the mosaic device, so as to implement the method according to the first aspect.

In a fifth aspect, the present application provides a readable storage medium comprising: software instructions; when the software instructions are run in the mosaic, the mosaic is caused to carry out the method of the first aspect as described above.

In a sixth aspect, the present application provides a tiled display system, the system comprising a tile and one or more display assemblies connected to the tile; the mosaic device and one or more display components are adapted to cooperate to implement the method of the first aspect.

The beneficial effects of the second to sixth aspects may refer to the description of the first aspect, and are not described in detail.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a mosaic display;

FIG. 2 is a schematic diagram of cropping;

fig. 3 is a schematic composition diagram of an LED tiled display system provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a composition of a mosaic controller provided in an embodiment of the present application;

fig. 5 is a schematic flowchart of a tiled display method according to an embodiment of the present application;

fig. 6 is another schematic flow chart of a tiled display method according to an embodiment of the present application;

fig. 7 is a schematic flowchart of another tiled display method according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a simulation algorithm provided in an embodiment of the present application;

FIG. 9 is a diagram illustrating the display effect of customized resolution provided by an embodiment of the present application;

FIG. 10 is a schematic view of another configuration of a control mosaic provided in the embodiment of the present application;

FIG. 11 is a functional diagram of a timing control module according to an embodiment of the present disclosure;

FIG. 12 is a schematic structural diagram of a synchronization constraint provided in an embodiment of the present application;

FIG. 13 is a schematic structural diagram of other constraints provided by embodiments of the present application;

fig. 14 is a schematic composition diagram of a mosaic display device provided in an embodiment of the present application.

Detailed Description

In the following, the terms "first", "second" and "third", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," or "third," etc., may explicitly or implicitly include one or more of that feature.

First, terms related to embodiments of the present application will be described.

1. Resolution (or may also be referred to as detailed timing): an attribute of digital video includes a combination of a set of data information describing the pixel transmission and display process. Some parameters of the resolution are the (effective) width of a single-frame digital image, the (effective) height of a single-frame digital image, and the frame rate (i.e., the number of frames refreshed in one second), and are generally described as width (W, W) × height (H), progressive, P)/interlaced, I, and Frames Per Second (FPS). Wherein the width is represented by the number of active pixels comprised in a row of a frame of the digital image and the height is represented by the number of active pixels comprised in a column of the digital image (or the number of rows). For example, 1920 × 1080p60 indicates that a digital image is composed of 1920 effective pixels in each row and 1080 effective pixels in each row, and the refresh frame rate is 60 frames per second. Another part of the parameters of the resolution is the relevant parameters of the blanking part. For example, a horizontal front shoulder (HFP), a horizontal back shoulder (HBP), a Horizontal Synchronization (HSYNC) period, a vertical front shoulder (VFP), a vertical back shoulder (VBP), and a Vertical Synchronization (VSYNC) period, and the like.

2. Standard resolution: the resolution is standardized by Video Electronics Standards Association (VESA) and Consumer Technology Association (CTA), and various standard resolutions are given in standard documents. For example, 640 × 350p85 and its relevant parameter of the blanking portion, 720 × 400p85 and its relevant parameter of the blanking portion, 800 × 600p100 and its relevant parameter of the blanking portion, 1600 × 1200p60 and its relevant parameter of the blanking portion, 1920 × 1400p60 and its relevant parameter of the blanking portion, and the like.

3. Aspect ratio: the (effective) width of the single frame digital image in resolution/the (effective) height of the single frame digital image in resolution, the aspect ratio of standard resolution is typically 4.

4. Clock (which may be referred to as pixel clock or pixel frequency): the total number of pixels included in the video image (digital image) for representing a unit time can be calculated according to the total width (effective width + blanking width) of the single-frame digital image and the total height (effective height + blanking height) of the single-frame digital image and the frame rate.

The LED tiled display system includes a video source, a tile, and one or more LED display assemblies. The video source may output a plurality of high resolution video images (i.e., the digital images described above). The video image splicing controller can splice a plurality of video images output by the video source into one video image and then divide the video image into a plurality of video images, and the divided video images are respectively sent to one or a plurality of LED display assemblies. Each LED display assembly can respectively display a corresponding video image, and the video images displayed by one or more LED display assemblies are combined together to form one video image spliced by the mosaic device.

Illustratively, fig. 1 is a schematic diagram of a mosaic display. As shown in fig. 1, taking an example where a user needs to display a 9920 × 1440 video image, a video source can output 4 2480 × 1440 high-resolution video images, a mosaic controller can splice the 4 2480 × 1440 high-resolution video images output by the video source into 1 9920 × 1440 video image, divide the 9920 × 1440 video image into 4 1920 × 900 video images, 2 3840 × 540 video images, 1 2240 × 900 video image and 1 2240 × 540 video image, respectively send the divided video images to the corresponding LED display modules, and combine the video images displayed by the LED display modules to form a mosaic controller-spliced 9920 × 1440 video image.

In order to make the video images displayed by one or more LED display assemblies normally smooth without tearing and the like, the mosaic device needs to segment the video images (or referred to as original video images) with multiple resolutions from the source video image and then nest the segmented video images in the standard resolution. It is understood that nesting video images in standard resolution may refer to: the video image is transmitted at a standard resolution.

However, the scheme of nesting video images in a standard resolution time sequence (which may be referred to as a nesting scheme) has high requirements on data transmission links and LED display components, and the universality of the scheme is not strong.

For example, for a data transmission link, if the picture area of a video image is not large, but the aspect ratio is large or small, the current scheme needs a larger standard resolution for nesting, and thus a higher transmission link standard and bandwidth are needed.

Taking the video image of 3840 by 540P60 as an example, the video image has a small picture area but a large width and height, and needs to be nested in the standard 4K (3840 by 2160P60) resolution, and the video image after the nesting is transmitted to the LED display component by the mosaic controller.

3840 × 540p60 calculates a clock/pixel frequency (pixel frequency) of 134.5 megahertz (Mhz) according to the VESA-coordinated video timing (VESA-CVT) standard, and a video image having a transmission clock of 340Mhz is supported at maximum in the High Definition Multimedia Interface (HDMI) 1.4 standard. That is, a transmission link using the HDMI1.4 standard can transmit 3840 × 540p60 video images. Whereas the standard 4K (3840 × 2160p60) resolution is calculated as 594Mhz according to the CTA-861-G standard, which is larger than 340Mhz, the maximum transmission capacity of the transmission link adopting the HDMI1.4 standard. That is, after the 3840 × 540p60 video image is nested in the standard 4K (3840 × 2160p60) resolution, the HDMI2.0 standard transmission link with a larger bandwidth is required to be adopted to transmit the video image.

For another example, for the LED display module, after receiving the nested video image sent by the mosaic device, the LED display module needs to cut and segment the nested video image to obtain an original video image, and then display the original video image.

Illustratively, fig. 2 is a schematic diagram of cropping. As shown in fig. 2 (a), the total width of the standard 4K resolution is 4400, the total height is 2250, the effective width is 3840, the effective height is 2160, and a blanking area is included in addition to the effective area. As shown in fig. 2 (b), also in the case of the aforementioned standard 4K resolution timing in which the video image of 3840 × 540p60 is nested into the standard 4K resolution timing of 3840 × 2160p60, after the video image of 3840 × 540p60 is nested into the standard 4K resolution timing of 3840 × 2160p60, the redundant region is filled with black data (illustrated by hatching in fig. 2). After the LED display module receives the nested video image, the LED display module needs to cut out the invalid black data to display the valid 3840 × 540 video image.

But not all LED display assemblies support the crop split function, current schemes for nesting video images in standard resolution place high demands on the LED display assemblies.

On this basis, embodiments of the present application provide a tiled display method, apparatus, LED tiled controller, storage medium, and system, which can generate a set of customized resolutions with smaller clock for each potential effective width, effective height, and frame rate (W × H P/I FPS), thereby reducing the requirements on the data transmission link and the LED display module, and improving the versatility of the tiled display scheme.

It should be noted that, the following description is given by taking an LED as an example, and the tiled display method provided in the embodiment of the present application may also be applied to other types of display devices, that is, the LED in the following embodiments may also be replaced by a Liquid Crystal Display (LCD) or other types of display devices. The embodiments of the present application do not limit this.

The following description is made with reference to the accompanying drawings.

Fig. 3 is a schematic composition diagram of an LED tiled display system according to an embodiment of the present application. As shown in fig. 3, the tiled display system includes: a video source 100, an LED mosaic 200, and one or more LED display assemblies 300. The video source 100, the LED mosaic 200, and the one or more LED display assemblies 300 may be connected via a wired network or a wireless network.

The video source 100 may be a computer or a server or other computing device with computing processing function. The server may be a single server, or may be a server cluster including a plurality of servers. In some embodiments, the server cluster may also be a distributed cluster. The video source 100 may also be implemented on a cloud platform, for example, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud (community cloud), a distributed cloud, an inter-cloud, or a multi-cloud (multi-cloud), etc., or any combination thereof.

For example, video source 100 may be an ultra high resolution server/ultra high resolution server.

A video source 100 for acquiring video images. For example, the video source 100 may be connected to an image capturing device, and the video source 100 may receive a video image transmitted by the image capturing device.

In some embodiments, the video source 100 is also configured to send video images to the LED mosaic 200.

As described above, the video source 100, the LED mosaic 200, and the one or more LED display assemblies 300 may be connected via a wired or wireless network. The wired or wireless network may include one or more media or devices capable of transmitting video images from the video source 100 to the LED mosaic 200.

In some embodiments, the wired or wireless network may include one or more communication media that enable the video source 100 to transmit video images directly to the LED mosaic 200 in real-time. In this embodiment, the video source 100 may modulate the video image according to a communication standard (e.g., a wireless communication protocol) and transmit the modulated video image to the LED tile 200. The one or more communication media may include wireless, and/or wired communication media such as a Radio Frequency (RF) spectrum or one or more physical transmission lines. Alternatively, the one or more communication media may form part of a packet-based network, which may be, for example, a local area network, a wide area network, or a global network (e.g., the Internet). Optionally, the one or more communication media may include a router, switch, base station, or other device that facilitates communication from the video source 100 to the LED mosaic 200.

The LED tile 200 may also be referred to as a LED tile controller (split tile controller), and the specific form thereof may be described with reference to the related art, which is not described herein.

The LED mosaic controller 200 may be configured to receive a plurality of video images sent by the video source 100, mosaic the plurality of video images sent by the video source 100 into one video image, segment the one video image obtained by the mosaic to obtain a video image corresponding to each LED display assembly, obtain a target resolution corresponding to each LED display assembly, and send the video image to each LED display assembly according to the target resolution corresponding to each LED display assembly. The detailed process of obtaining the resolution corresponding to each LED display module may refer to the following splicing display method, which is not described herein again.

The LED display assembly 300 may include a plurality of LED display assemblies, and each LED display assembly 300 may include one transmitting card, a plurality of receiving cards, and a plurality of LED lamp bead modules.

The transmitting card is a video protocol conversion system, the transmitting card can strip video data sent by the splicing controller, the video data are sent to the receiving card after internal processing, and the receiving card can control the LED lamp bead module to emit light to display images according to the video data which are sent by the transmitting card and are subjected to the internal processing.

The data transmission between the LED controller 200 and the sending card in the LED display assembly 300 can be described with reference to the data transmission between the video source 100 and the LED controller 200, and will not be described herein again.

The execution main body of the tiled display method provided by the embodiment of the present application may be the LED tiled controller 200, or an Application (APP) installed in the LED tiled controller 200 and providing a resolution obtaining function; still alternatively, a processor (e.g., a Central Processing Unit (CPU)) in the LED tile 200; or, a functional module for executing the tiled display method in the LED tile 200. The embodiments of the present application do not limit this.

For convenience of description, the following description is uniformly given by taking an LED mosaic controller as an example of an execution main body of the mosaic display method provided by the embodiment of the present application.

Fig. 4 is a schematic composition diagram of an LED mosaic provided in the embodiment of the present application. As shown in fig. 4, the LED mosaic may include: a processor 10, a memory 20, a communication line 30, a communication interface 40, and an input-output interface 50.

The processor 10, the memory 20, the communication interface 40, and the input/output interface 50 may be connected via a communication line 30.

And a processor 10, configured to execute the instructions stored in the memory 20 to implement the tiled display method provided in the following embodiments of the present application. The processor 10 may be a CPU, a general purpose processor Network Processor (NP), a Digital Signal Processor (DSP), a microprocessor, a microcontroller, a Programmable Logic Device (PLD), or any combination thereof. The processor 10 may also be any other device having a processing function, such as a circuit, a device, or a software module, which is not limited by the embodiments of the present application. In one example, processor 10 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 4. As an alternative implementation, the electronic device may comprise a plurality of processors, for example, a processor 60 (illustrated in fig. 4 by a dashed line) in addition to the processor 10.

A memory 20 for storing instructions. For example, the instructions may be a computer program. Alternatively, the memory 20 may be a read-only memory (ROM) or other types of static storage devices that can store static information and/or instructions, an access memory (RAM) or other types of dynamic storage devices that can store information and/or instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), a magnetic disc storage medium or other magnetic storage devices, and the like, which are not limited in this embodiment.

It should be noted that the memory 20 may exist independently from the processor 10, or may be integrated with the processor 10. The memory 20 may be located inside the LED tile or outside the LED tile, which is not limited in this embodiment of the application.

A communication line 30 for communicating information between the various components comprised by the LED mosaic. The communication line 30 may be an Industry Standard Architecture (ISA) line, a Peripheral Component Interconnect (PCI) line, an Extended ISA (EISA) line, or the like. The communication line 30 may be divided into an address line, a data line, a control line, and the like. For ease of illustration, only one solid line is shown in fig. 4, but does not indicate only one line or type of line.

A communication interface 40 for communicating with other devices (e.g., the video source 100, or the LED display assembly 300, etc., as described above) or other communication networks. For example, the communication interface 40 may be a Digital Visual Interface (DVI) or an HDMI video interface.

Alternatively, other communication networks in communication with communication interface 40 may be ethernet, radio Access Network (RAN), wireless Local Area Network (WLAN), etc. Communication interface 40 may be a module, circuitry, transceiver, or any device capable of enabling communication.

And the input and output interface 50 is used for realizing human-computer interaction between a user and the LED mosaic controller. For example, the action interaction, the text interaction or the voice interaction between the user and the LED mosaic controller are realized.

Illustratively, the input/output interface 50 may be a mouse, a keyboard, a display screen, a touch display screen, or the like, and work interaction or text interaction between a user and the LED controller may be realized through the keyboard, the mouse, the display screen, the touch display screen, or the like.

It should be noted that the configuration shown in fig. 4 does not constitute a limitation of the LED tile, and the LED tile may include more or less components than those shown in fig. 4, or a combination of certain components, or a different arrangement of components, in addition to those shown in fig. 4.

The tiled display method provided by the embodiment of the application is described below with reference to the accompanying drawings.

Fig. 5 is a schematic flow chart of a tiled display method according to an embodiment of the present application. Alternatively, the method may be performed by an LED tile having the hardware configuration shown in fig. 3 described above. As shown in fig. 5, the method includes S101 to S105.

S101, the LED mosaic controller obtains a preset resolution and a preset frame rate corresponding to each LED display component.

Wherein each LED display assembly is also each of the one or more LED display assemblies described above. The one or more LED display assemblies may include M rows and N columns of LED display assemblies. M and N are integers greater than or equal to 1. As described above, one LED display module may include one sending card, a plurality of receiving cards, and a plurality of LED lamp bead modules, and M rows and N columns of LED display modules may also be understood as M rows and N columns of sending cards. A sending card can correspond to a plurality of receiving cards and a plurality of LED lamp bead modules, and the embodiment of the application does not limit the specific number of the receiving cards and the LED lamp bead modules corresponding to the sending card. The preset resolution may include a preset effective width, a preset effective height, and the like.

As described above, the LED mosaic may include an input-output interface, which may be a mouse, a keyboard, or a touch display screen, etc. The LED pin controller can receive preset effective width, preset effective height and preset frame rate required to be displayed by one or more LED display components input by a user through a mouse, a keyboard, a touch display screen and the like.

S102, the LED mosaic controller determines one or more target candidate clocks according to the preset frame rate of each LED display component.

Wherein the target candidate clock is a clock satisfying the following first condition: and the quotient of the division by the preset frame rate of any one LED display assembly is greater than or equal to the product of the preset effective width and the preset effective height corresponding to any one LED display assembly.

Optionally, the LED tile may determine a plurality of initial clocks from a plurality of clocks between a minimum clock supported by the LED tile and a maximum clock supported by the LED tile according to a preset clock stepping accuracy, determine one or more initial candidate clocks satisfying a second condition from the plurality of initial clocks according to a number of factors of a quotient obtained by dividing each initial clock by a preset frame rate of any one of the LED display assemblies and the second condition, and determine one or more target candidate clocks from the one or more initial candidate clocks based on an initial resolution corresponding to the one or more initial candidate clocks.

Wherein, the clock stepping precision can be preset in the LED pin controller by managers, and the clock stepping precision is used for indicating the clock interval of adjacent initial clocks. For example, the clock stepping accuracy may be 1 kilohertz (khz), or 1Mhz, etc. The embodiment of the present application does not limit the specific value of the clock stepping precision. Minimum clock also can be preset in the LED spelling accuse ware by managers, and this application embodiment does not do the restriction to the concrete numerical value of minimum clock yet. The maximum clock can also be preset in the LED controller by a manager, or the LED controller can first determine the maximum limit clock corresponding to the maximum limit bandwidth of the current scene as the maximum clock according to the maximum limit bandwidth and the corresponding relationship between the preset maximum limit bandwidth and the maximum limit clock, where the maximum limit bandwidth is input by the user. The embodiment of the present application also does not limit the specific value of the maximum clock. The second condition is: the number of the quotient factors obtained by dividing the preset frame rate of any one LED display assembly is larger than the number threshold value.

Alternatively, the LED tile may determine a plurality of initial clocks among a plurality of clocks between the minimum clock and the maximum clock in a preset order.

For example, the LED tile may choose an initial clock at every other clock step precision starting with the minimum clock until traversing from the minimum clock to the maximum clock.

The clock stepping accuracy is used to indicate a minimum interval for selecting a candidate clock from a plurality of clocks between a minimum clock and a maximum clock.

For example, with a minimum clock of 100Mhz, a clock stepping precision of 1Mhz, and a maximum limit bandwidth of a current scene of 10.2 gigabits per second (Gbps) (i.e., the current scene uses a transmission link of HMDI1.4 standard to transmit video image data), the LED mosaic can determine a maximum limit clock 340Mhz corresponding to 10.2 (Gbps) as a maximum clock according to a corresponding relationship between the maximum limit bandwidth and the maximum limit clock, and traverse the minimum clock 100Mhz and the maximum clock 340Mhz with the stepping precision of 1Mhz to obtain a plurality of clocks 101Mhz, 102Mhz, 103Mhz, 8230, mx, and 340Mhz, and determine a plurality of initial clocks from the plurality of clocks.

For example, the initial resolutions corresponding to the one or more initial candidate clocks may be as shown in table 1 below.

TABLE 1

Resolution ID

Initial candidate clock

Total width

Total height of

Effective width

Effective height

Frame rate

Resolution 1

Clock 1

Total width 1

Overall height 1

Effective width 1

Effective height 1

Frame rate 1

Resolution 2

Clock 1

Total width 2

Total height 2

Effective width 2

Effective height 2

Frame rate 2

Resolution 3

Clock 2

Total width 3

Total height 3

Effective width 3

Effective height 3

Frame rate 3

As shown in table 1, the initial resolutions corresponding to the one or more initial candidate clocks may include a resolution ID entry, an initial candidate clock entry, a total width entry, a total height entry, an effective width entry, an effective height entry, and a frame rate entry. The resolution ID entry may include resolution 1, resolution 2, and resolution 3, among others. The initial candidate clock entries may include clock 1 and clock 2. The total width term may include total width 1, total width 2, and total width 3. The overall height items may include overall height 1, overall height 2, and overall height 3. The effective width term may include an effective width 1, an effective width 2, and an effective width 3. The effective height terms may include an effective height 1, an effective height 2, and an effective height 3. Frame rate entries may include frame rate 1, frame rate 2, and frame rate 3. Resolution 1, clock 1, total width 1, total height 1, effective width 1, effective height 1, and frame rate 1 have a correspondence. Resolution 2, clock 1, total width 2, total height 2, effective width 2, effective height 2, and frame rate 2 have a correspondence. Resolution 3, clock 2, total width 3, total height 3, effective width 3, effective height 3, and frame rate 3 have a correspondence.

Optionally, for example, if the one or more initial candidate clocks include a first clock, and the preset frame rates corresponding to the one or more LED display assemblies are all the first frame rates, before the LED tile determines the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolution corresponding to the one or more initial candidate clocks, the LED tile may further generate the initial resolution based on the one or more initial candidate clocks.

Optionally, the LED tile generating the initial resolution based on the one or more initial candidate clocks may comprise the following four steps:

step 1, the LED mosaic controller carries out one or more times of factorization on a first area obtained by dividing a first clock by a first frame rate, and the first area is decomposed into two factors each time.

And 2, for each factorization, taking one of the two factorized factors (for example, the larger factor) as the maximum width and taking the other of the two factorized factors (for example, the smaller factor) as the maximum height by the LED mosaic controller.

And 3, determining the effective width of the LED mosaic controller according to the maximum width, and determining the effective height according to the maximum height.

For example, the LED tiles may subtract 80 from the maximum width to obtain the effective width. Also taking the first frame rate and the first area as examples, the LED mosaic may calculate the first clock, the first frame rate, the first area, and the like according to the VESA-CVT standard to obtain a first value, and subtract the first value from the maximum height to obtain the effective height.

And 4, generating one of multiple initial resolutions on the basis of the maximum width, the maximum height, the effective width and the effective height of the LED mosaic controller.

In a possible implementation manner, the determining, by the LED tile, one or more initial candidate clocks from the plurality of initial clocks according to a factor of a quotient obtained by dividing each initial clock by the target frame rate of any one LED display assembly and a second condition may include: the LED mosaic controller obtains one or more first initial clocks with the number of the quotient obtained by dividing the target frame rate of any one LED display assembly into a whole number larger than a number threshold value from the plurality of initial clocks, and determines initial candidate clocks from the one or more first initial clocks.

Wherein, the number threshold value can be preset by a manager. For example, the number threshold may be 8, 10, 12, or the like. The embodiment of the present application does not limit the specific numerical value of the number threshold. In this possible implementation, the second condition may be understood as determining the initial clock as the first initial clock when the number of factors of the quotient obtained by dividing the target frame rate of any one LED display assembly is greater than the number threshold.

Optionally, in this possible implementation manner, the determining, by the LED tile, one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolution corresponding to the one or more initial candidate clocks may include: if the initial candidate clock meeting the first condition is included in the one or more initial candidate clocks, the LED controller determines one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolution corresponding to the one or more initial candidate clocks.

In another possible implementation manner, the LED tile may filter out initial candidate clocks of different gradient queues according to different granularities from the initial clocks. In this case, the method may further include: if the initial candidate clock meeting the first condition is not included in the one or more first initial clocks, one or more second initial clocks, of which the number of the quotient obtained by dividing the preset frame rate of any one LED display component is smaller than or equal to the number threshold, are obtained, and one or more initial candidate clocks are determined from the one or more second initial clocks.

Optionally, the LED tile may also obtain standard clock instructions. After determining the one or more initial candidate clocks, the LED tile may also delete clocks other than the standard clock in the initial candidate clocks, such that the LED tile retains only the standard clock in the initial candidate clocks.

The standard clock refers to a clock in a standard protocol. The obtaining manner of the standard clock instruction may refer to the point where the preset resolution of the one or more LED display elements is obtained through the input/output interface in S101, and is not described herein again.

Optionally, the LED mosaic may also default to a standard clock to filter one or more initial candidate clocks. In this case, the determining one or more initial candidate clocks from the one or more first initial clocks includes: taking a first initial clock which is the same as the standard clock in the one or more first initial clocks as an initial candidate clock; the determining one or more initial candidate clocks from the one or more second initial clocks comprises: and taking the first initial clock which is the same as the standard clock in the one or more first initial clocks as the initial candidate clock.

Optionally, the LED mosaic may further obtain capability information of one or more LED display assemblies, and determine a clock supported by any one of the LED display assemblies and a clock supported by the LED mosaic according to the capability information of the one or more LED display assemblies and the capability information of the LED mosaic. After determining the one or more initial candidate clocks, the LED tile may also delete clocks from the initial candidate clocks that are outside the union of the clocks supported by the one or more LED display components and the clocks supported by the LED tile.

Wherein the capability information of the LED display assembly is used for indicating clocks supported by a sending card and a receiving card in the LED display assembly.

In a possible implementation manner, taking the first initial candidate clock as an example, the determining, by the LED tile, one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolution corresponding to the one or more initial candidate clocks may include: for each initial resolution of one or more initial resolutions corresponding to the first initial candidate clock, the LED mosaic controller judges whether the initial resolution supports any one LED display component; and if the initial resolution supporting any one LED display component exists in the one or more initial resolutions corresponding to the first initial candidate clock, determining the first initial candidate clock as a target candidate clock.

For example, the LED mosaic may compare the effective width and the effective height in the initial resolution with a preset effective width and a preset effective height of a certain LED display assembly, and when the effective width in the initial resolution is greater than or equal to the preset effective width of the LED display assembly and the effective height in the initial resolution is greater than or equal to the preset effective height of the LED display assembly, the LED mosaic may determine that the initial resolution supports the LED display assembly.

S103, the LED controller determines the smallest target candidate clock in the one or more target candidate clocks as the target clock of the one or more LED display components.

For example, the LED mosaic may sort one or more target candidate clocks in order from small to large, obtain a second sorting result, and determine a first target candidate clock in the second sorting result as the target clock.

S104, the LED mosaic controller determines the target resolution corresponding to each LED display component based on the target clock.

The target resolution includes a target effective width, a target effective height, a target frame rate, and the like.

Optionally, as described above, the LED tile may generate an initial resolution based on one or more initial candidate clocks. After the target clock is determined, the LED mosaic may further traverse the generated initial resolutions by using the target clock as an index, determine one or more initial resolutions corresponding to the target clock as candidate resolutions, and determine the target resolution corresponding to each LED display component from the one or more candidate resolutions based on a preset effective width and a preset effective height in a preset resolution corresponding to each LED display component.

Optionally, the LED mosaic may sort the one or more candidate resolutions in an order from small to large in effective width to obtain a first sorting result, and select a target resolution according to the first sorting result. Fig. 6 is another schematic flow chart of the tiled display method according to the embodiment of the present application. As shown in fig. 6, taking the first LED display assembly as an example, S104 may specifically include S201 to S211.

S201, the LED mosaic controller obtains the preset effective width and the preset effective height of the first LED display assembly.

S201 may refer to S101 described above, and is not described herein again.

S202, the LED mosaic controller sorts one or more candidate resolutions according to the sequence of the effective widths from small to large to obtain a first sorting result.

S203, the LED mosaic controller judges whether the current times of selecting the candidate resolution is larger than or equal to the number of the candidate resolutions in the first sequencing result.

If yes, executing S204; if not, go to S205.

S204, the LED splicing controller sends out first information.

Wherein the first information is used for indicating the end of the process of screening the target resolution from the initial candidate resolution.

As described above, the LED tile may include an input/output interface, the input/output interface may be a touch display screen, and the LED tile may display a first interface in the touch display screen, where the first interface includes the first information.

S205, the LED mosaic controller judges whether the effective width of the currently selected candidate resolution is larger than or equal to the preset effective width corresponding to the first LED display assembly or not, and whether the effective height of the currently selected candidate resolution is larger than or equal to the preset effective height corresponding to the first LED display assembly or not.

If yes, go to S206; if not, go to S207.

S206, the LED mosaic controller determines the currently selected candidate resolution as the target resolution corresponding to the first LED display assembly.

S207, the LED mosaic controller judges whether the effective width of the currently selected candidate resolution is larger than or equal to the preset effective width of the first LED display assembly or not and whether the effective height of the currently selected candidate resolution is smaller than the preset effective height of the first LED display assembly or not.

If yes, executing S208 and S209 and then returning to S203; if not, go to S210.

S208, the LED mosaic controller selects the candidate resolution ratio before the currently selected candidate resolution ratio in the first sequencing result to judge.

S209, the LED mosaic controller adds 1 to the number of the currently selected candidate resolutions.

S210, the LED mosaic controller judges whether the effective width of the currently selected candidate resolution is smaller than the preset effective width of the first LED display assembly or not and whether the effective height of the currently selected candidate resolution is larger than or equal to the preset effective height of the first LED display assembly or not.

If yes, executing S211 and S209 and then returning to S203; if not, executing S204.

S211, the LED mosaic controller selects candidate resolutions after the currently selected candidate resolution in the first sequencing result for judgment.

It should be noted that, in S201 to S211, reference is made to the LED mosaic controller obtaining the preset effective width and the preset effective height of one LED display assembly at a time for judgment, and selecting the target resolution corresponding to the LED display assembly as an example, the LED mosaic controller may judge one or more LED display assemblies according to the steps in S201 to S211, and select the target resolution corresponding to each LED display assembly.

Optionally, after determining the target resolution corresponding to each LED display component, the LED mosaic may further correct the target resolution according to a resolution standard. For example, the target resolution is modified according to the VESA-CVT standard or the VESA-image interchange Format (GIF) standard, so that the target resolution meets the resolution standard, and compatibility between the LED mosaic and the LED display component is guaranteed.

Optionally, after the target resolution corresponding to each LED display assembly is determined, the LED mosaic controller may also correct the target resolution according to the hardware bit width limitation of the transmission link, so that when the LED mosaic controller sends the target resolution to the LED display assembly, the bit width of each parameter in the sent target resolution is smaller than the hardware bit width limitation of the transmission link. In this case, taking the clock in the target resolution as an example, the method may further include: the LED splicing controller acquires bit width information of each LED display component; and the LED mosaic controller modifies the target clock in the target resolution corresponding to each LED display assembly according to the bit width information sent by each LED display assembly and the bit width information of the LED mosaic controller, so that the bit width of the target clock in the target resolution corresponding to one or more LED display assemblies is smaller than or equal to the minimum value of the maximum bit width of the transmission link transmission clock indicated by the bit width information sent by each LED display assembly and the maximum bit width of the LED mosaic controller transmission clock indicated by the bit width information of the LED mosaic controller.

Wherein, the bit width information of the LED pin controller can be preset in the LED pin controller. For example, preset in the memory of the LED mosaic. The embodiment of the application does not limit the specific content of the bit width information of the LED pin controller and the indicated maximum bit width value.

Optionally, the LED mosaic controller may modify the target resolution according to a resolution standard, and then modify the target resolution according to the hardware bit width limitation of the transmission link. In this case, fig. 7 is another schematic flow chart of the tiled display method according to the embodiment of the present application. As shown in fig. 7, after S104, the method may further include S301 to S305.

S301, the LED mosaic controller obtains bit width information of each LED display component.

The bit width information of the LED display assembly is used for indicating the maximum bit width of a transmission link transmission clock between the LED mosaic controller and the LED display assembly. For example, the LED mosaic may be obtained by receiving bit width information sent by each LED display component.

S302, the LED mosaic controller corrects the target resolution corresponding to each LED display component according to the resolution standard.

The specific correction process may be described with reference to the related art of the resolution standard, and is not described herein again.

And S303, the LED mosaic controller judges whether the bit width of the target clock in the target resolution corresponding to each LED display component is smaller than or equal to the minimum value of the maximum bit width of the transmission link transmission clock indicated by the bit width information sent by each LED display component and the maximum bit width of the LED mosaic controller transmission clock indicated by the bit width information of the LED mosaic controller.

If yes, go to S304; if not, S304 is executed after S305 is executed.

And S304, outputting the target resolution by the LED mosaic controller.

S305, the LED mosaic controller adjusts the target resolution corresponding to each LED display component, so that the bit width of the target clock in the target resolution corresponding to each LED display component is smaller than or equal to the minimum value of the maximum bit width of the transmission link transmission clock indicated by the bit width information sent by each LED display component and the maximum bit width of the LED mosaic controller transmission clock indicated by the bit width information of the LED mosaic controller.

It should be noted that, the correction process is described by taking the clock in the target resolution as an example, and the correction process of other parameters in the target resolution, such as the maximum width, the maximum height, the effective width, the effective height, and the like, may also be described with reference to S301 to S305, which is not described herein again.

Optionally, referring to fig. 8, fig. 8 is a schematic diagram of a simulation algorithm provided in the embodiment of the present application, and as shown in fig. 8, before S104, the LED tile may further determine the maximum bandwidth M of the output interface based on the interface standard of the current output interface of the LED tile ₀ Screening out the globally optimal pixel clock solution matching the maximum bandwidth through an off-line computer simulation algorithm, andthe database of the total width and total height frame rate at this pixel clock is output as a basis for determining the target resolution of each LED display element in S104 described above. For downward compatibility, a total width and total height frame rate database matched by the globally optimal pixel clock solution matched under other bandwidths can be simultaneously output.

Optionally, as described above, the one or more LED display assemblies may comprise M rows and N columns of LED display assemblies. When N is greater than or equal to 2, the method may further include: the LED mosaic adjusts the size of a horizontal front shoulder (HFP) in a target resolution corresponding to each row of the LED display assemblies in the M rows, so that the horizontal blanking size of each row of the LED display assemblies in the M rows is gradually reduced from left to right.

For example, the LED tile may obtain the number of rows and columns of one or more LED display assemblies, when the number of columns is greater than 2, that is, each row includes one or more LED display assemblies, and at this time, the LED display assemblies in each row need to be synchronously displayed, at this time, the LED tile (or a timing control module in the LED tile described below) may turn on an internal row synchronization flag, and (or an output module in the LED tile described below) adjust the size of a horizontal front shoulder (HFP) in a target resolution corresponding to each LED display assembly in the M rows in response to the internal row synchronization flag, so that the horizontal blanking size of each LED display assembly in the M rows is sequentially decreased from left to right.

It will be appreciated that when there are a plurality of LED display elements in each of the M rows, reducing the horizontal blanking of the row of LED display elements may reduce the lack of synchronization between adjacent LED display elements of a row due to scanning precedence.

Optionally, as described above, the one or more LED display assemblies may comprise M rows and N columns of LED display assemblies. M and N are integers greater than or equal to 1. When M and N are both greater than or equal to 2, that is, when one or more LED display assemblies include multiple rows and multiple columns, each frame of video image of the LED display assemblies in the multiple rows and multiple columns needs to be displayed synchronously, at this time, the LED tile may turn on the intra frame synchronization flag, and in response to the intra frame synchronization flag, obtain the target resolution according to the steps described in S101 to S104 above. When one or more LED display assemblies include 1 row and 1 column, that is, 1 LED display assembly, the LED mosaic may turn off the internal frame synchronization flag, and only obtain the target resolution corresponding to the 1 LED display assembly. For a specific process, reference may also be made to the above S101 to S104, which are not described herein again.

S105, the LED mosaic controller sends the sub-video image to each LED display assembly according to the target resolution corresponding to each LED display assembly, so that each LED display assembly displays the sub-video image according to the corresponding target resolution.

The sub-video images are obtained by segmenting the video images (namely, the video images obtained by splicing a plurality of video images output by the video source by the LED splicing device) by the LED splicing device, and the sub-video images displayed by each LED display assembly are spliced together to obtain the video images.

Illustratively, fig. 9 is a display effect diagram of the customized resolution provided by the embodiment of the present application. As shown in fig. 9, taking the target effective widths and target effective heights corresponding to the LED display components as 2240 × 540, 2240 × 900, 1920 × 900 and 3840 × 540 as examples, and assuming that the solid line area and the dotted line area shown in fig. 2 also represent the total width and height area, respectively, after the customized resolution is generated for the target effective width and the target effective height corresponding to each of the obtained LED display components by using the tiled display method according to the embodiment of the present application, the area of the total width and height area is small, the corresponding clock is small, and the outline of the total width and height area fits the outline of the effective display area, so that the video image does not need to be cut and divided by the transmission card receiving the video image.

According to the splicing display method provided by the embodiment of the application, the target resolution corresponding to each LED display component can be generated for each LED display component according to the preset effective width, the preset effective height and the preset frame rate required to be displayed by each LED display component, aiming at the LED display components with different preset effective widths, different preset effective heights and different preset frame rates, the LED splicing controller firstly determines the target candidate clocks meeting each LED display component, selects the smallest one from the target candidate clocks as the target clock, and generates the target resolution corresponding to each LED display component based on the smallest target clock. And moreover, because the target clock is smaller, the product of the effective width and the effective height in the target resolution determined based on the target clock is smaller, the area of the effective display area corresponding to the target resolution is smaller, and the area of the effective display area corresponding to the preset resolution is better fit, after the LED splicing controller transmits the video image to the LED display assembly according to the target resolution, the LED display assembly (or a sending card in the LED display assembly) does not need to cut and divide the received video image, the requirements on the functions of the LED display assembly are reduced, and the flexibility of the splicing display scheme is improved.

In addition, target clocks in target resolutions corresponding to the LED display components are the same, clocks of the LED mosaic controller under any resolution are consistent, and frame asynchronism among video images displayed by the LED display components due to clock (or pixel frequency) deviation (offset frequency) is avoided.

It should be noted that, the above-mentioned LED is taken as an example to describe the tiled display method provided in the embodiments of the present application, and as described above, the method may also be applied to an LCD or other types of display devices. When the method is suitable for the LCD, the corresponding LCD splicing controller can perform splicing display according to the standard resolution, or the customized resolution is generated according to the splicing display method for displaying. The embodiments of the present application do not limit this.

In an exemplary embodiment, the present application provides another composition structure of the LED mosaic. Fig. 10 is another schematic composition diagram of an LED mosaic provided in the embodiment of the present application. As shown in fig. 10, the LED mosaic may include one input subsystem and K output subsystems, K being an integer greater than or equal to 1, and each output subsystem may include a clock synchronization module, a timing control module, and an output module.

The input subsystem can receive a plurality of video images input by the video source, the plurality of video images input by the video source are spliced into one video image, the spliced video image is segmented, and the segmented K video images are respectively sent to the K output subsystems through the internal/external buses.

The output subsystems can ensure the clock phase synchronization among the K output subsystems through the clock synchronization module, and ensure the synchronization of the K picture contents output by the K output subsystems through the internal logic of the output module. The detailed description may refer to the related art, and is not repeated here.

The timing control module may be configured to execute steps in the tiled display method, and fig. 11 is a functional schematic diagram of the timing control module according to an embodiment of the present disclosure. As shown in fig. 11, the timing control module has a database generation (according to constraint generation) function, a database filtering (according to constraint filtering) function, a resolution filtering (according to target effective width and target effective height of one or more LED display components) function, and a resolution generation (according to constraint generation) function.

The database generation function may refer to the initial resolution corresponding to the initial candidate clock generated in S102, which is not described herein again. The database screening function may be described with reference to the step of screening the target candidate clock from the initial candidate clock in S102, and details thereof are not repeated here. The resolution filtering function can be described with reference to the above S201 to S211, and is not described herein again. The resolution generation function may refer to the above-mentioned S301 to S305, and is not described herein again.

As can be seen from the above description of the tiled display method, the design constraints of the present application mainly include two aspects: synchronization constraints and other constraints.

Fig. 12 is a schematic structural diagram of synchronization constraint provided in an embodiment of the present application. As shown in fig. 12, for LED tiled display systems, synchronization constraints can include LED tile related constraints, LED display assembly related constraints, and the like. The constraints related to the LED mosaic can include synchronization constraints of the transmission link, synchronization constraints of image content, and the like. The synchronization constraints of the transmission link may include frame synchronization constraints, line synchronization constraints, and clock source synchronization constraints, among others.

Fig. 13 is a schematic structural diagram of another constraint provided in an embodiment of the present application. As shown in fig. 13, other constraints referred to in the present application refer to various constraints in the actual demand scenario of the user, including clock compatibility constraints, output scale scenario constraints, data transmission link constraints, and the like.

The compatibility constraint of the clocks means that a part of brands of sending cards only support or preferentially support the clocks specified in the standard resolution on the receiving clocks, and therefore two modes of 'global clock coverage' and 'standard clock coverage' can be selected in the tiled display method. When selecting standard clock coverage, the clock on which the resolution of generation depends is only selected among the standard clocks (i.e., the target clocks of the standard sequence). When the global clock overlay is selected, the clock on which the resolution is generated may be selected from clocks other than the standard clock (i.e., the initial candidate clock determined from the first clock and the second clock as described above).

The output scale scene constraint is mainly a generation strategy for adjusting the resolution ratio according to the actual splicing form. For example, in a 1 × 1 output splicing scenario, all synchronization constraints are skipped directly inside the LED splicer. In an output splicing scene of M × N (M ≧ 2), a line synchronization constraint link (i.e., the above-mentioned line synchronization flag is turned on) is executed inside the LED tile, or in an output splicing scene of M × N (M =1, N ≧ 2), the line synchronization constraint inside the LED tile is skipped for mitigation. Under the output splicing scene of M multiplied by N (M is more than or equal to 2, N is more than or equal to 2), all synchronous constraint links (namely the opening of the line synchronous mark and the opening of the frame synchronous mark) are executed inside the LED splicing controller.

The data transmission link constraint mainly aims at the requirements of maximum limit bandwidth, hardware bit length, clock holes and the like on the data transmission link.

For example, some of the transmitting cards use DVI interface, the maximum supported clock is 170Mhz, some of the transmitting cards use HDMI1.4 interface, the maximum supported clock is 340Mhz, some of the transmitting cards use HDMI2.0 interface, and the maximum supported clock is 600 Mhz.

The limitation of hardware bit length means that the resolutions in the sending card and the receiving card are obtained or configured through corresponding registers in the chip, and the bit length of the registers limits the generation and the obtaining of the resolutions.

The limitation on the aspect of the clock holes means that a manufacturer of a chip may have some clock holes inside when designing hardware or software, and the clock holes are also unsupported clocks, so that when a target clock is screened from candidate clocks, the unsupported candidate clocks can be removed.

The scheme provided by the embodiment of the application is mainly introduced from the perspective of a method. To implement the above functions, it includes hardware structures and/or software modules for performing the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In an exemplary embodiment, the present application further provides a mosaic display device, and the device may apply the above-mentioned LED mosaic. Fig. 14 is a schematic composition diagram of a mosaic display device provided in an embodiment of the present application. As shown in fig. 14, the apparatus includes an acquisition module 1401, a processing module 1402, and a transmission module 1403.

An obtaining module 1401, configured to obtain a preset resolution and a preset frame rate corresponding to each LED display component; the preset resolution comprises a preset effective width and a preset effective height;

a processing module 1402, configured to determine one or more target candidate clocks according to a preset frame rate of each LED display component; the target candidate clock is a clock satisfying the following first condition: dividing the quotient of the preset frame rate of any one LED display component by being more than or equal to the product of the preset effective width and the preset effective height of any one LED display component; determining a smallest one of the one or more target candidate clocks as a target clock of the one or more LED display components; determining a target resolution corresponding to each LED display component based on the target clock;

a sending module 1403, configured to send the sub-video image to each LED display component according to the target resolution corresponding to each LED display component, so that each LED display component displays the sub-video image according to the corresponding target resolution; the sub-video images are obtained by segmenting the video images through the splicing controller, and the sub-video images displayed by each LED display assembly are spliced together to obtain the video images.

In some possible embodiments, the processing module 1402 is specifically configured to determine a plurality of initial clocks from a plurality of clocks between the minimum clock and the maximum clock according to a preset clock stepping precision; presetting clock stepping precision for indicating the clock interval of adjacent initial clocks; determining one or more initial candidate clocks meeting a second condition from a plurality of initial clocks according to the number of factors of a quotient obtained by dividing each initial clock by the preset frame rate of any one LED display component and the second condition; the second condition is: the number of quotient factors obtained by dividing the preset frame rate of any one LED display assembly is larger than a number threshold value; determining one or more target candidate clocks from the one or more initial candidate clocks based on initial resolutions corresponding to the one or more initial candidate clocks, each initial candidate clock corresponding to one or more initial resolutions;

in other possible embodiments, the processing module 1402 is specifically configured to obtain, from the multiple initial clocks, one or more first initial clocks in which the number of the factors obtained by dividing the preset frame rate of any one LED display assembly is greater than the number threshold, and determine an initial candidate clock from the one or more first initial clocks; if the one or more initial candidate clocks comprise initial candidate clocks meeting a first condition, determining one or more target candidate clocks from the one or more initial candidate clocks based on initial resolutions corresponding to the one or more initial candidate clocks;

in some possible embodiments, the processing module 1402 is further configured to, if an initial candidate clock satisfying the first condition is not included in the one or more initial candidate clocks, obtain one or more second initial clocks, of the plurality of initial clocks, in which a number of quotients obtained by dividing the preset frame rate of any one LED display component is smaller than or equal to a number threshold; determining one or more initial candidate clocks from the one or more second initial clocks;

in some possible embodiments, the processing module 1402 is specifically configured to use a first initial clock that is the same as the standard clock in the one or more first initial clocks as the initial candidate clock; taking a first initial clock which is the same as the standard clock in the one or more first initial clocks as an initial candidate clock;

in yet other possible embodiments, the one or more initial candidate clocks comprise a first clock, and the preset frame rate of the one or more LED display assemblies is the first frame rate; before determining one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolution corresponding to the one or more initial candidate clocks, the processing module 1402 is further configured to perform one or more factorizations on a first area obtained by dividing the first clock by the first frame rate, each time decomposing the first area into two factors; for each factorization, taking one of two factors obtained by factorization as a maximum width, and taking the other of the two factors obtained by factorization as a maximum height; determining an effective width according to the maximum width and determining an effective height according to the maximum height; generating one of a plurality of initial resolutions based on the maximum width, the maximum height, the effective width, and the effective height;

in still other possible embodiments, the one or more LED display assemblies include M rows and N columns of LED display assemblies, where M and N are integers greater than or equal to 1, and when N is greater than or equal to 2, the processing module 1402 is further configured to adjust the horizontal front shoulders HFP in the target resolution corresponding to each row of the M rows of LED display assemblies, so that the horizontal blanking size of each row of the M rows of LED display assemblies decreases from left to right.

It should be noted that the division of the modules in fig. 14 is schematic, and is only one logical function division, and there may be another division manner in actual implementation. For example, two or more functions may also be integrated in one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

In an exemplary embodiment, the present application further provides a readable storage medium, which includes executable instructions that, when executed on a tile, cause the tile to perform any one of the methods provided by the above embodiments.

In an exemplary embodiment, the present application further provides a computer program product containing computer executable instructions, which when run on a tile causes the tile to perform any one of the methods provided by the above embodiments.

In an exemplary embodiment, an embodiment of the present application further provides a chip, including: a processor coupled to the memory through the interface, and an interface, the processor causing any one of the methods provided by the above embodiments to be performed when the processor executes the computer program in the memory or when the processor executes the instructions by the tile.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer-executable instructions. The processes or functions according to the embodiments of the present application are generated in whole or in part when the computer-executable instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer executable instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer executable instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available media that can be accessed by a computer or data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), etc.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the present application has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely illustrative of the present application as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A tiled display method applied to a tile connected to one or more display elements, the method comprising:

acquiring a preset resolution and a preset frame rate corresponding to each display component; the preset resolution comprises a preset effective width and a preset effective height;

determining one or more target candidate clocks according to the preset frame rate of each display component; the target candidate clock is a clock satisfying a first condition: dividing the quotient of the preset frame rate of any display component by more than or equal to the product of the preset effective width and the preset effective height of any display component;

determining a smallest one of the one or more target candidate clocks as a target clock of the one or more display components;

determining a target resolution corresponding to each display component based on the target clock;

sending the sub-video image to each display assembly according to the target resolution corresponding to each display assembly, so that each display assembly displays the sub-video image according to the corresponding target resolution; the sub-video images are obtained by segmenting the video images through the splicing controller, and the sub-video images displayed by each display assembly are spliced together to obtain the video images.

2. The method of claim 1, wherein determining one or more candidate clocks according to a predetermined frame rate for each display component comprises:

determining a plurality of initial clocks from a plurality of clocks between a minimum clock and a maximum clock according to a preset clock stepping precision; the preset clock stepping precision is used for indicating the clock interval of adjacent initial clocks;

determining one or more initial candidate clocks meeting a second condition from the plurality of initial clocks according to the number of factors of a quotient obtained by dividing each initial clock by the preset frame rate of any display component and the second condition; the second condition is: the number of quotient factors obtained by dividing the preset frame rate of any display component is larger than the number threshold;

determining the one or more target candidate clocks from the one or more initial candidate clocks based on initial resolutions corresponding to the one or more initial candidate clocks, each initial candidate clock corresponding to one or more initial resolutions.

3. The method according to claim 2, wherein the determining one or more initial candidate clocks satisfying a second condition from the plurality of initial clocks according to the number of factors of a quotient obtained by dividing each initial clock by a preset frame rate of any one display component and the second condition comprises:

acquiring one or more first initial clocks, the number of the quotient of which is obtained by dividing the preset frame rate of any display component into whole numbers is larger than a number threshold value, from the plurality of initial clocks, and determining initial candidate clocks from the one or more first initial clocks;

the determining the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks comprises:

if the one or more initial candidate clocks comprise initial candidate clocks meeting the first condition, determining the one or more target candidate clocks from the one or more initial candidate clocks based on initial resolutions corresponding to the one or more initial candidate clocks.

4. The method of claim 3, further comprising:

if the one or more initial candidate clocks do not comprise the initial candidate clock meeting the first condition, one or more second initial clocks, in which the number of the quotient factors obtained by dividing the preset frame rate of any display component in the plurality of initial clocks is smaller than or equal to the number threshold, are obtained;

determining the one or more initial candidate clocks from the one or more second initial clocks.

5. The method according to claim 3 or 4,

said determining said one or more initial candidate clocks from said one or more first initial clocks comprises: taking a first initial clock of the one or more first initial clocks, which is the same as a standard clock, as the initial candidate clock;

said determining said one or more initial candidate clocks from said one or more second initial clocks comprises: and taking a second initial clock which is the same as the standard clock in the one or more second initial clocks as the initial candidate clock.

6. The method of any of claims 2-4, wherein the one or more initial candidate clocks comprise a first clock, and wherein the predetermined frame rate of the one or more display components is the first frame rate; before the determining the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, the method further includes:

performing one or more factorizations on a first area obtained by dividing the first clock by the first frame rate, wherein the first area is factored into two factors each time;

for each factorization, taking one of two factors obtained by factorization as a maximum width, and taking the other of the two factors obtained by factorization as a maximum height;

determining an effective width according to the maximum width and determining an effective height according to the maximum height;

generating one of the plurality of initial resolutions based on the maximum width, the maximum height, the effective width, and the effective height.

7. The method of claim 1, wherein the one or more display elements comprise M rows and N columns of display elements, M and N each being an integer greater than or equal to 1, and wherein when N is greater than or equal to 2, the method further comprises:

adjusting a horizontal front shoulder HFP in a target resolution corresponding to each line of display components in the M lines, so that a horizontal blanking size of each line of display components in the M lines is decreased from left to right in sequence.

8. A tiled display apparatus, the apparatus comprising: the device comprises an acquisition module, a processing module and a sending module;

the acquisition module is used for acquiring the preset resolution and the preset frame rate corresponding to each display component; wherein the preset resolution comprises a preset effective width and a preset effective height;

the processing module is used for determining one or more target candidate clocks according to the preset frame rate of each display component; the target candidate clock is a clock satisfying a first condition: dividing the quotient of the preset frame rate of any display component by more than or equal to the product of the preset effective width and the preset effective height of any display component; determining a smallest one of the one or more target candidate clocks as a target clock of the one or more display components; determining a target resolution corresponding to each display component based on the target clock;

the sending module is used for sending the sub-video image to each display assembly according to the target resolution corresponding to each display assembly, so that each display assembly displays the sub-video image according to the corresponding target resolution; the sub-video images are obtained by segmenting the video images through the splicing controller, and the sub-video images displayed by each display assembly are spliced together to obtain the video images.

9. The apparatus of claim 8,

the processing module is specifically configured to determine a plurality of initial clocks from a plurality of clocks between a minimum clock and a maximum clock according to a preset clock stepping precision; the preset clock stepping precision is used for indicating the clock interval of adjacent initial clocks; determining one or more initial candidate clocks meeting a second condition from the plurality of initial clocks according to the number of factors of a quotient obtained by dividing each initial clock by the preset frame rate of any display component and the second condition; the second condition is that: the number of quotient factors obtained by dividing the preset frame rate of any display component is larger than the number threshold; determining the one or more target candidate clocks from the one or more initial candidate clocks based on initial resolutions corresponding to the one or more initial candidate clocks, each initial candidate clock corresponding to one or more initial resolutions;

and/or the presence of a gas in the gas,

the processing module is specifically configured to obtain one or more first initial clocks, in which the number of quotient factors obtained by dividing the preset frame rate of any one display component is greater than a number threshold, from the plurality of initial clocks, and determine an initial candidate clock from the one or more first initial clocks; if the one or more initial candidate clocks comprise initial candidate clocks meeting the first condition, determining one or more target candidate clocks from the one or more initial candidate clocks based on initial resolutions corresponding to the one or more initial candidate clocks;

and/or the presence of a gas in the atmosphere,

the processing module is further configured to, if the one or more initial candidate clocks do not include an initial candidate clock that satisfies the first condition, obtain one or more second initial clocks, of the plurality of initial clocks, in which a number of quotient factors obtained by dividing an entire preset frame rate of any display component is smaller than or equal to the number threshold; determining the one or more initial candidate clocks from the one or more second initial clocks;

and/or the processing module is specifically configured to use a first initial clock that is the same as a standard clock in the one or more first initial clocks as the initial candidate clock; taking a second initial clock which is the same as a standard clock in the one or more second initial clocks as the initial candidate clock;

and/or the presence of a gas in the gas,

the one or more initial candidate clocks comprise a first clock, and the preset frame rate of the one or more display components is a first frame rate; before the determining of the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolution corresponding to the one or more initial candidate clocks, the processing module is further configured to perform one or more factorizations on a first area obtained by dividing the first clock by the first frame rate, each time decomposing the first area into two factors; for each factorization, taking one of two factors obtained by factorization as a maximum width, and taking the other of the two factors obtained by factorization as a maximum height; determining an effective width according to the maximum width and determining an effective height according to the maximum height; generating one of the plurality of initial resolutions based on the maximum width, the maximum height, the effective width, and the effective height;

and/or the presence of a gas in the gas,

the one or more display components include M rows and N columns of display components, M and N are integers greater than or equal to 1, and when N is greater than or equal to 2, the processing module is further configured to adjust a horizontal front shoulder HFP in a target resolution corresponding to each of the M rows of display components, so that a horizontal blanking size of each of the M rows of display components decreases sequentially from left to right.

10. An LED mosaic, characterized in that, the LED mosaic comprises: a processor and a memory;

the memory stores instructions executable by the processor;

the processor is configured to, upon execution of the instructions, cause the LED mosaic to implement the method of any one of claims 1-7.

11. A readable storage medium, characterized in that the readable storage medium comprises: software instructions;

the software instructions, when executed in a tile, cause the tile to implement the method of any of claims 1-7.

12. A mosaic display system, characterized in that, the system comprises a mosaic device and one or more display components connected with the mosaic device;

the mosaic controller is used for acquiring the preset resolution corresponding to each display component; the preset resolution comprises a preset effective width, a preset effective height and a preset frame rate; determining one or more target candidate clocks according to the preset frame rate of each display component; the target candidate clock is a clock satisfying a first condition: dividing the quotient of the preset frame rate of any display component by more than or equal to the product of the preset effective width and the preset effective height of any display component; determining a smallest target candidate clock of the one or more target candidate clocks as a target clock; determining a target resolution corresponding to each display component based on the target clock; sending the sub video image to each display assembly according to the target resolution corresponding to each display assembly; the sub video image is obtained by segmenting the video image by the mosaic controller;

the one or more display components are used for displaying the sub-video images sent by the splicing device according to the respective corresponding target resolution, and the sub-video images displayed by each display component are spliced together to obtain the video image.

Images