CN115858267A

CN115858267A - Circuit testing method and device, electronic equipment and storage medium

Info

Publication number: CN115858267A
Application number: CN202211697804.2A
Authority: CN
Inventors: 惠君龙; 王水莲; 谢晋飞
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-03-28

Abstract

The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for testing a circuit, an electronic device, and a storage medium, so as to improve accuracy of detecting a function of a tracking encoder circuit. The method comprises the following steps: acquiring a target compressed data packet normally output by a memory in a tracking encoder to be tested and an overflow prompt data packet output when the memory overflows; the target compressed data packet is input into the memory after the retirement instruction address and other attribute information output by the processor are compressed by the tracking encoder; generating an actual instruction address file by analyzing a target compressed data packet and an overflow prompt data packet; and comparing the expected instruction address file with the actual instruction address file, and analyzing and tracking the circuit function of the encoder according to the comparison result. Based on the mode, the condition of inconsistent contrast caused by incorrect circuit function can be identified and avoided, and the accuracy of detecting the circuit function of the tracking encoder is improved.

Description

Circuit testing method and device, electronic equipment and storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for testing a circuit, an electronic device, and a storage medium.

Background

With the rapid development of computer technology, before software with various functions is put into use, it is necessary to test whether a Central Processing Unit (CPU) can normally execute according to a Program corresponding to the software, so that it is necessary to reproduce all retired instruction addresses (Program Counter, PC) executed by the CPU, thereby implementing software testing.

In the related art, all retired PCs executed by a CPU can be reproduced by a Trace Encoder (TE) circuit. Therefore, whether the TE circuit can work normally is important for software testing.

Generally, it is mainly to compare the actual PC file with the expected PC file to test whether there is a bug in the TE circuit. If the actual PC file is not consistent with the expected PC file, the TE circuit function is incorrect. However, during the execution of a large number of consecutive non-speculatable instructions by the CPU, a TE First Input First Output (FIFO) memory overflow may occur, and a part of retired PCs may be discarded, so that the discarded retired PCs are lacked in the generated actual PC file, and such incorrect circuit function may also result in inconsistent comparison between the actual PC file and the expected PC file.

Therefore, how to identify and avoid the situation of inconsistent contrast caused by incorrect circuit functions, and improve the accuracy of circuit function detection becomes a problem to be solved urgently.

Disclosure of Invention

The circuit testing method and device, the electronic device and the storage medium are used for improving the accuracy of circuit function detection.

The circuit testing method provided by the embodiment of the application comprises the following steps:

acquiring a target compressed data packet normally output by a memory in a tracking encoder to be tested and an overflow prompt data packet output when the memory overflows; the target compressed data packet is input into the memory after a retired instruction address and other attribute information output by the processor are compressed by the tracking encoder;

generating an actual instruction address file by analyzing the target compressed data packet and the overflow prompt data packet;

and comparing an expected instruction address file with the actual instruction address file, and analyzing the circuit function of the tracking encoder according to the comparison result, wherein the expected instruction address file is generated based on the retired instruction address.

The embodiment of the application provides a testing arrangement of circuit, includes:

the first acquisition unit is used for acquiring a target compressed data packet normally output by a memory in a tracking encoder to be tested and an overflow prompt data packet output when the memory overflows; the target compressed data packet is input into the memory after a retired instruction address and other attribute information output by the processor are compressed by the tracking encoder;

the generating unit is used for generating an actual instruction address file by analyzing the target compressed data packet and the overflow prompt data packet;

and the comparison unit is used for comparing an expected instruction address file with the actual instruction address file and analyzing the circuit function of the tracking encoder according to a comparison result, wherein the expected instruction address file is generated based on the retired instruction address.

Optionally, the expected instruction address file contains a plurality of rows of expected instruction addresses, and the actual instruction address file contains a plurality of rows of actual instruction addresses and at least one row of miss flags; the loss mark is used for representing that the memory overflows and is mark information corresponding to an overflow prompt data packet; the expected instruction address and the actual instruction address both belong to retired instruction addresses;

the comparison unit is specifically configured to:

taking each continuously existing line loss mark in the actual instruction address file as a batch of loss marks, and taking each continuously existing line actual instruction address after the batch of loss marks as a corresponding group of actual instruction addresses;

comparing the actual instruction addresses of each line before the first batch of loss marks with the expected instruction addresses of the corresponding lines in the expected instruction address file respectively;

if the inconsistency exists, determining that the circuit function of the tracking encoder is incorrect;

and if the actual instruction addresses are consistent with the expected instruction address file, comparing the corresponding groups of actual instruction addresses with the expected instruction address file in sequence according to the sequence of each batch of lost marks, and analyzing the circuit function of the tracking encoder according to the comparison result.

Optionally, the comparison unit is specifically configured to:

comparing the corresponding groups of actual instruction addresses with the expected instruction address file in sequence according to the sequence of the lost marks of each group;

if the comparison result corresponding to the actual instruction address of the current group is determined to represent and compare consistently, continuing to compare the next group;

and if the comparison result corresponding to the current group of actual instruction addresses represents that the comparison is inconsistent, determining that the circuit function of the tracking encoder is incorrect.

Optionally, the second obtaining unit is configured to obtain a comparison result corresponding to the current group of actual instruction addresses in the following manner:

taking an expected instruction address corresponding to a first lost mark in the current batch of lost marks in the expected instruction address file as a reference expected instruction address, and taking a first row of actual instruction addresses in a current group of actual instruction addresses as actual initial instruction addresses;

sequentially inquiring the expected instruction address which is the same as the actual starting instruction address from the reference expected instruction address in the expected instruction address file;

if not, determining that the comparison result represents inconsistent comparison;

if the target expected instruction address is found, taking the expected instruction address which is the same as the actual initial instruction address in the expected instruction address file as the target expected instruction address; and comparing the expected instruction address behind the target expected instruction address with the actual instruction address at the corresponding position behind the actual starting instruction address to obtain a corresponding comparison result.

Optionally, the comparison unit is specifically configured to:

if the expected instruction address behind the target expected instruction address is inconsistent with the actual instruction address at the corresponding position behind the actual starting instruction address, determining that the comparison result representation and comparison corresponding to the actual instruction address of the current group are inconsistent;

and if the expected instruction address behind the target expected instruction address is consistent with the actual instruction address at the corresponding position behind the actual starting instruction address, determining that the comparison results corresponding to the actual instruction addresses of the current group are consistent in representation and comparison.

Optionally, the generating unit is specifically configured to:

analyzing the target compressed data packet through a tracking decoder corresponding to a tracking protocol to obtain a target decompressed data packet, and writing a nonlinear instruction address and a jump instruction address in the target decompressed data packet into an actual instruction address file; and

analyzing the overflow prompt data packet through the tracking decoder to obtain an overflow prompt decompression data packet, and writing a loss mark into an actual instruction address file based on prompt information in the overflow prompt decompression data packet; the loss mark is used for representing that the memory overflows and is mark information corresponding to the overflow prompt data packet.

Optionally, the apparatus further comprises:

a writing unit, configured to, if there are multiple consecutive target decompressed data packets, perform the following operations for each two adjacent target decompressed data packets, respectively:

and writing the linear instruction address between the jump instruction address in the previous target decompression data packet and the nonlinear instruction address in the next target decompression data packet into an actual instruction address file.

Optionally, the memory is a first-in first-out memory.

An electronic device provided in an embodiment of the present application includes a processor and a memory, where the memory stores a computer program, and when the computer program is executed by the processor, the processor is caused to execute the steps of any one of the above-mentioned circuit testing methods.

A computer-readable storage medium includes a computer program, and when the computer program runs on an electronic device, the computer program is configured to enable the electronic device to execute the steps of the method for testing any one of the circuits.

A computer program product provided by an embodiment of the present application includes a computer program, where the computer program is stored in a computer-readable storage medium; when the processor of the electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the electronic device performs the steps of the method for testing the circuit.

The beneficial effect of this application is as follows:

the embodiment of the application provides a circuit testing method and device, electronic equipment and a storage medium. Considering that during the execution of a large number of non-speculatable instructions by the CPU, the FIFO memory in the TE circuit may overflow, and part of retired instruction addresses may be discarded, such non-circuit function may also cause the actual instruction address file to be inconsistent with the expected instruction address file. In the embodiment of the application, the situation is considered when the actual instruction address file is generated, the overflow prompting data packet for representing the overflow of the FIFO memory is introduced, and the actual instruction address file is generated by analyzing the overflow prompting data packet output when the FIFO memory overflows and the target compressed data packet normally output by the FIFO memory.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application.

Fig. 1 is a schematic view of an application scenario in an embodiment of the present application;

FIG. 2 is a flow chart of an embodiment of a method for testing a circuit;

FIG. 3 is a diagram illustrating a compressed data packet file according to an embodiment of the present application;

FIG. 4 is a diagram illustrating an example of decompressing a packet file according to an embodiment of the present application;

FIG. 5 is a diagram of a first actual PC file in the embodiment of the present application;

FIG. 6 is a diagram illustrating a desired PC file in an embodiment of the present application;

FIG. 7 is a diagram of a second actual PC file in the embodiment of the present application;

FIG. 8 is a diagram of a third actual PC file in an embodiment of the present application;

FIG. 9 is a schematic illustration of a first comparison in an embodiment of the present application;

FIG. 10 is a diagram showing a second comparison in examples of the present application;

FIG. 11 is a diagram showing a comparison of a third document in the examples of the present application;

FIG. 12 is a diagram showing a fourth comparison of documents in the examples of the present application;

FIG. 13 is a diagram showing a fifth comparison in the examples of the present application;

FIG. 14 is a flowchart illustrating an embodiment of a method for testing a circuit;

FIG. 15 is a flowchart illustrating an embodiment of a document comparison process in the examples of the present application;

FIG. 16 is a flowchart illustrating an embodiment of obtaining a comparison result of an actual PC of a current group according to the present application;

FIG. 17 is a schematic diagram illustrating an exemplary embodiment of a circuit testing apparatus;

fig. 18 is a schematic structural diagram of an electronic device in an embodiment of the present application;

fig. 19 is a schematic diagram of a hardware component of a computing device to which an embodiment of the present invention is applied.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments, but not all embodiments, of the technical solutions of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments described in the present application without any creative effort belong to the protection scope of the technical solution of the present application.

Some concepts related to the embodiments of the present application are described below.

Retirement and retirement PC: the retirement representation instruction completes all operations and normally exits, and the instruction address corresponding to the retirement instruction is the retirement PC. The embodiment of the application relates to a non-linear PC and a jump PC. Wherein, the non-linear PC refers to an instruction address corresponding to the non-linear retirement instruction; jump PC refers to the next instruction address corresponding to the non-linear address.

Trace protocol: including but not limited to the 5001 Forum standard (Nexus 5001 Forum) ^TM Standard), efficient Trace (Efficient Trace for RISC-V) protocol.

Tracking the encoder: for all retired PCs that are replicated CPU execution. In the embodiment of the application, based on the trace protocol, the trace encoder is used for generating the compressed data packet by using the retired PC and other attribute information output by the CPU. For example, based on Nexus 5001 Forum ^TM In the Standard protocol, a compressed data packet generated by compression of a tracking encoder is called as: nexus Public information (Nexus Public Message); tracking compressed data generated by compression of encoder based on Efficient Trace for RISC-V protocolThe package is called: the Instruction Trace encoder outputs a packet (Instruction Trace encoder output packet).

FIFO memory: is a first-in first-out double-port buffer, i.e. the first data entering it is shifted out first, one of them is the input port of the memory and the other is the output port of the memory. In the embodiment of the present application, the compressed data packet output by the TE circuit is input to the input port of the memory, and then output from the output port of the memory.

Overflowing: in the embodiment of the application, the FIFO memory overflows to represent that the FIFO memory has reached the maximum memory capacity, and when a subsequently input compressed data packet cannot be stored, the partial compressed data packet is discarded, and then an overflow prompt data packet is output. E.g. based on Nexus 5001 Forum ^TM The Standard protocol, the overflow hint packet is called: error message (error message); based on the Efficient Trace for RISC-V protocol, the overflow prompt packet is called: support packet (support packet).

Target compressed data packet: refers to the compressed data packet normally output by the FIFO memory.

And (3) overflowing prompt data packet: the number of the overflow prompting data packets is related to the number of times of overflow of the FIFO memory, namely, one overflow prompting data packet is generated every time the FIFO memory overflows, and two overflow prompting data packets are generated if the FIFO memory overflows twice.

The tracking decoder: and based on trace protocol, decompressing the compressed data packet output by the FIFO memory to obtain a decompressed data packet. The embodiment of the application relates to a target decompression data packet and an overflow prompt decompression data packet, wherein the target decompression data packet refers to a data packet obtained by decompressing a target compression data packet through a tracking decoder; the overflow hint decompression packet refers to a packet obtained by decompressing the overflow hint packet by a trace decoder.

Loss marking: the method is used for outputting the overflow prompt data packet when the FIFO memory overflows, and the mark information corresponding to the overflow prompt data packet.

Referring to the expected instruction address: refers to the expected instruction address in the expected instruction address file corresponding to the first missing tag in each batch of missing tags.

Actual starting instruction address: refers to the actual instruction address of the first line in the corresponding group after the first of the missing tags in each batch.

The preferred embodiments of the present application will be described below with reference to the accompanying drawings of the specification, it should be understood that the preferred embodiments described herein are merely for illustrating and explaining the present application, and are not intended to limit the present application, and that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

Fig. 1 is a schematic view of an application scenario according to an embodiment of the present application. The application scenario diagram includes a TE circuit 110 and an electronic device 120.

It should be noted that, the test method of the circuit in the embodiments of the present application may be executed by the electronic device 120, and the electronic device 120 may include an analysis module and a PC comparison module, for example, the electronic device analyzes the compressed data packet output by the TE circuit 110 through the analysis module to generate an actual PC file, and then compares the actual PC file with an expected PC file through the PC comparison module, so as to implement the detection of the function of the TE circuit.

Alternatively, the electronic device may be a terminal device or a server, that is, the method may be executed by the terminal device or the server alone, or may be executed by both the terminal device and the server. In the embodiment of the present application, the terminal device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a desktop computer, and the like; the terminal device may be installed with a client related to circuit testing, and the client may be software, or a web page, an applet, or the like. The server is a background server corresponding to the software, the web page, the applet, or the like, or a server specially used for circuit testing, which is not limited in the present application. The server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server providing basic cloud computing services such as cloud service, a cloud database, cloud computing, a cloud function, cloud storage, network service, cloud communication, middleware service, domain name service, security service, content Delivery Network (CDN), big data, an artificial intelligence platform, and the like.

In an alternative embodiment, the TE circuit 110 and the electronic device 120 may communicate via a communication network.

In an alternative embodiment, the communication network is a wired network or a wireless network.

The following describes a method for testing a circuit provided in an exemplary embodiment of the present application with reference to the drawings in conjunction with the application scenarios described above, and it should be noted that the application scenarios described above are only shown for the convenience of understanding the spirit and principles of the present application, and the embodiments of the present application are not limited in this respect.

Referring to fig. 2, which is a flowchart illustrating an implementation of a circuit testing method according to an embodiment of the present application, a terminal device is taken as an execution main body, and a specific implementation flow of the method includes the following steps S201 to S203:

s201: acquiring a target compressed data packet normally output by a memory in a tracking encoder to be tested and an overflow prompt data packet output when the memory overflows; the target compressed data packet is input into the memory after the retired instruction address and other attribute information output by the processor are compressed by the tracking encoder.

In this application, the memory may be a first-in first-out memory, that is, a FIFO memory, and is configured to buffer a target compressed data packet output by the tracking encoder, input the target compressed data packet to an input port of the memory, and then output the target compressed data packet by an output port of the memory.

Specifically, the target compressed data packet refers to a plurality of target compressed data packets corresponding to the tracking protocol, which are obtained by compressing the initial retired PC, the non-linear retired PC and corresponding attribute information in the retired instruction address by the to-be-tested tracking encoder based on the tracking protocol. Other attribute information refers to information related to retirement instructions, including but not limited to: instruction type, authority, instruction length, etc.

Tracking protocols include, but are not limited to, the following two: nexus 5001 Forum ^TM Standard protocol, efficient Trace for RISC-V protocol. Hereinafter, nexus 5001 Forum is mainly used ^TM The Standard protocol is described in detail as an example.

In this embodiment, the memory overflow means that the FIFO memory has reached the maximum storage capacity, and when a compressed packet input subsequently cannot be stored, the partial compressed packet is discarded, and then an overflow prompt packet is output.

The number of the overflow prompting data packets is related to the number of times of overflow of the FIFO memory, namely, each time the FIFO memory overflows, one overflow prompting data packet is generated, and if the FIFO memory overflows three times, three overflow prompting data packets are generated.

Based on Nexus 5001 Forum ^TM The Standard protocol can refer to the target compressed data packet output by the FIFO memory as: true compress, the overflow hint packet output by the FIFO memory is called: error message.

Fig. 3 is a schematic diagram of a compressed data packet file according to an embodiment of the present application, where compressed data packets that can be acquired by a terminal device sequentially include: true compress1, error message2, true compress3. Wherein, true compress1, true compress2, true compress3 are target compressed data packets; error message1 and error message2 are overflow prompting packets.

It should be noted that the number and sequence of the above listed compressed data packets are only simple examples, and are not limited in this document.

S202: and generating an actual instruction address file by analyzing the target compressed data packet and the overflow prompt data packet.

Specifically, the actual instruction address file is generated by analyzing the target compressed data packet and the overflow hint data packet, and an optional implementation manner is as follows:

firstly, analyzing a target compressed data packet through a tracking decoder corresponding to a tracking protocol to obtain a target decompressed data packet, and writing a nonlinear instruction address and a jump instruction address in the target decompressed data packet into an actual instruction address file.

And further, the overflow prompting data packet is analyzed through the tracking decoder to obtain an overflow prompting decompressed data packet, and the loss mark is written into the actual instruction address file based on the prompting information in the overflow prompting decompressed data packet.

The loss mark is used for representing the overflow of the memory, and mark information corresponding to the overflow prompt data packet.

In the present application, different tracking decoder models are mapped based on different tracking protocols. The tracking encoder model is used for decompressing a target compressed data packet and an overflow prompt data packet output by the FIFO memory to obtain a target decompressed data packet and an overflow prompt decompressed data packet.

Based on Nexus 5001 Forum ^TM The Standard protocol may refer to the target decompressed packet as: true decompression, which may refer to the overflow hint decompressing packet as: error message.

Still taking fig. 3 as an example, the tracking encoder parses the compressed packet in the file to obtain the decompressed packet file.

Fig. 4 is a schematic diagram of a decompressed data packet file according to an embodiment of the present application, in which the decompressed data packet file sequentially includes: true decompaction 1, error decompaction 2, true decompaction 3. Wherein, the true decompression 1, true decompression 2 and true decompression 3 are target decompression data packets; the error messages 1 and 2 are overflow prompt decompression packets.

Wherein the nonlinear PC included in the true decompressers 1 is 8000_0100, the nonlinear PC included in the true decompressers 2 is 8000_0120, the jump PC is 8000_0124, and the nonlinear instruction address included in the true decompressers 3 is 8000_0132.

Specifically, the overflow prompt decompresses the prompt information in the packet, which is used to indicate the reason for the error, and is usually indicated by a number, for example, the number 1 indicates that the FIFO memory overflows. The loss mark refers to the overflow of the FIFO memory, and the mark information corresponding to the overflow prompt data packet, for example, the loss mark can be represented by error. When the overflow prompt data packet is analyzed, the prompt information number 1 in the data packet error message is decompressed according to the obtained overflow prompt, and the error is written into an actual PC file.

For example, error1 is written into the actual PC file according to the number 1 in error message1, and error2 is written into the actual PC file according to the number 1 in error message 2.

If there are multiple consecutive target decompressed packets, the following operations are performed for each two adjacent target decompressed packets:

Still referring to FIG. 4, for two adjacent target decompressed packets, the true decompacted packets 2 and true decompacted packets 3 need to write linear instruction addresses 8000_0128 and 8000_0130 between the jump instruction address 8000_0124 in true decompacted packet 2 and the nonlinear instruction address 8000_0132 in true decompacted packet 3 into the actual PC file.

Referring to fig. 5, which is a schematic diagram of a first actual PC file provided in the embodiment of the present application, the contents of the generated actual PC files are 8000_0100, error1, error2, 8000_0120, 8000_0124, 8000_0128, 8000_0130, and 8000_0132, respectively, by parsing the compressed data packet in the above manner.

It should be noted that, the number and sequence of the decompressed packets and the overflow prompt decompressed packets, the content of the actual PC file, and the like listed above are only simple examples, and the present disclosure is not limited in detail.

In the mode, the overflow prompting data packet is analyzed, the loss mark is written into the actual PC file, and the inconsistency of comparison caused by incorrect non-circuit function can be identified and avoided when the PC file is compared with the expected PC file.

S203: and comparing the expected instruction address file with the actual instruction address file, and analyzing and tracking the circuit function of the encoder according to the comparison result.

Wherein the expected instruction address file is generated based on the retired instruction address. The expected instruction address file comprises a plurality of rows of expected instruction addresses, and the actual instruction address file comprises a plurality of rows of actual instruction addresses and at least one row of missing marks; both the expected instruction address and the actual instruction address belong to retired instruction addresses.

Fig. 6 is a schematic diagram of a desired PC file provided in an embodiment of the present application, where the desired PC file includes 16 lines of desired PCs.

Fig. 7 is a schematic diagram of a second actual PC file according to an embodiment of the present application, in which the actual PC file includes 7 lines of actual instruction addresses and 3 lines of missing flags.

Specifically, comparing the expected instruction address file with the actual instruction address file, and analyzing the circuit function of the tracking encoder according to the comparison result, an optional implementation is as follows (1) - (4):

(1) and taking each continuously existing line loss mark in the actual instruction address file as a batch of loss marks, and taking each continuously existing line actual instruction address after the batch of loss marks as a corresponding group of actual instruction addresses.

Still taking fig. 7 as an example, consecutive loss markers error1 and error2 exist in the file, error1 and error2 are used as a first batch of loss markers, and error3 is used as a second batch of loss markers; 8000_0220, 8000_0224, 8000_0228, 8000 _0230are used as the first set of actual instruction addresses and 8000_0240, 8000 _0244are used as the second set of actual instruction addresses.

(2) And comparing the actual instruction addresses of all lines before the first batch of loss marks with the expected instruction addresses of corresponding lines in the expected instruction address file respectively.

Still taking the example shown in fig. 7, a line of actual PCs, i.e., 8000 u 0200, exists in the actual PC file before the first missing markers error1 and error2, which is compared with the first line of expected PCs in the expected PC file.

Referring to fig. 8, which is a schematic diagram of a third actual PC file provided in the embodiment of the present application, in the figure, a row of actual PCs, i.e., 8000 u 0202, exists before the first missing markers error1 and error2 in the actual PC file, and the actual PC file is compared with the first row of expected PCs in the expected PC file.

(3) If there is an inconsistency, it is determined that the circuit of the tracking encoder is not functioning correctly.

For example, the first row in the PC file is 8000_0200 for the expected PC in FIG. 6 and 8000_0202 for the actual PC in FIG. 8, which are inconsistent and indicate that the tracking encoder circuit functions incorrectly.

(4) And if the actual instruction addresses are consistent with the expected instruction address files, comparing the corresponding groups of actual instruction addresses with the expected instruction address files in sequence according to the sequence of each batch of lost marks, and analyzing the circuit function of the tracking encoder according to the comparison result.

For example, the first row in the PC file expected in FIG. 6 is 8000\u0200, and the first row in the actual PC file in FIG. 7 is 8000_0202, with the comparisons being identical.

Then, according to the sequence of each batch of lost marks, comparing each group of corresponding actual instruction addresses with the expected instruction address file in sequence, and analyzing and tracking the circuit function of the encoder according to the comparison result, wherein an optional implementation mode is as follows:

(1) if the comparison result corresponding to the actual instruction address of the current group is determined to represent and compare consistently, continuing to compare the next group;

(2) and if the comparison result corresponding to the current group of actual instruction addresses represents that the comparison is inconsistent, determining that the circuit function of the tracking encoder is incorrect.

In the embodiment of the present application, the comparison result corresponding to the current group of actual instruction addresses may be obtained in the following manner:

firstly, an expected instruction address corresponding to a first lost mark in the current batch of lost marks in the expected instruction address file is used as a reference expected instruction address, and a first line actual instruction address in the current group of actual instruction addresses is used as an actual starting instruction address.

Then, the expected instruction address which is the same as the actual starting instruction address is inquired in sequence from the reference expected instruction address in the expected instruction address file.

The following two cases are specifically classified:

and if the condition I is not inquired, determining that the comparison result represents that the comparison is inconsistent.

Fig. 9 is a schematic diagram of a first file comparison provided in the embodiment of the present application, in which 1 batch loss flag and 1 group actual PC are included in an actual PC file. The batch loss marker serves as a current batch loss marker, the group of actual PCs serves as a current group of actual PCs, the actual starting PC in the group of actual PCs is 8000\u0216, and the second line 8000_0202 in the expected PC file is the reference expected PC.

The reference expected PC8000_0202 and thereafter expected PCs are different from the actual start PC8000_0216, and the comparison is inconsistent, indicating that the circuit function of the tracking encoder is incorrect.

In case II, if the target expected instruction address is found, taking the expected instruction address which is the same as the actual initial instruction address in the expected instruction address file as the target expected instruction address; and comparing the expected instruction address after the target expected instruction address with the actual instruction address at the corresponding position after the actual starting instruction address to obtain a corresponding comparison result.

Specifically, the target desired PC has two cases:

case a: when the reference desired PC coincides with the actual start PC, the reference desired PC is taken as the target desired PC.

Fig. 10 is a schematic diagram of a second file comparison provided in the embodiment of the present application, in which 1 batch loss flag and 1 group actual PC are included in an actual PC file. The batch loss marker serves as a current batch loss marker, the group of actual PCs serves as a current group of actual PCs, the actual starting PC in the group of actual PCs is 8000_0314, and the second line 8000_0314 in the expected PC file is a reference expected PC. By contrast, the reference desired PC coincides with the actual start PC, and the reference desired PC8000_0314 is taken as the target desired PC.

Case b: and when the reference expected PC is inconsistent with the actual starting PC, comparing the expected PCs after the reference expected PC with the actual starting PC, and inquiring the expected PC consistent with the actual starting PC as a target expected PC.

Referring to fig. 11, a schematic diagram of a comparison of a third file provided in the embodiment of the present application is shown, in which an actual PC file includes 2 batches of loss markers and 2 groups of actual PCs. The first batch loss marker is taken as the current batch loss marker, the first group of actual PCs is taken as the current group of actual PCs, the actual starting PC in the first group of actual PCs is 8000_0220, and the second line 8000_0204 in the expected PC file is the reference expected PC.

The reference desired PC8000_0204 is inconsistent with the actual start PC8000_0220, the desired PCs after the reference desired PC8000_0204 are all compared with the actual start PC8000_0220, and when it is queried that the 9 th row desired PC8000_0220 is consistent with the actual start PC8000_0220, the desired PC8000_0220 is taken as the target desired PC.

Then, comparing the expected instruction address after the target expected instruction address with the actual instruction address at the corresponding position after the actual start instruction address to obtain a corresponding comparison result, wherein the specific conditions are as follows:

and II1, if the expected instruction address behind the target expected instruction address is inconsistent with the actual instruction address at the corresponding position behind the actual initial instruction address, determining that the comparison result corresponding to the actual instruction address of the current group is inconsistent in representation and comparison.

Referring to fig. 12, a schematic diagram of a fourth comparison of files provided by the embodiment of the present application is shown, in which an actual PC file includes 1 batch loss marker and 1 group of actual PCs. The batch loss mark is used as a current batch loss mark, the group of actual PCs is used as a current group of actual PCs, the actual starting PC in the group of actual PCs is 8000_0414, the target expected PC is 8000_0414, the expected PC8000_0418 after the target expected PC is inconsistent with the actual PC8000_0416 after the actual starting PC, namely, the comparison result corresponding to the current group of actual instruction addresses is inconsistent in characterization and comparison, and the tracking encoder is indicated to have an incorrect circuit function.

And II2, if the expected instruction address behind the target expected instruction address is consistent with the actual instruction address at the corresponding position behind the actual initial instruction address, determining that the comparison results corresponding to the actual instruction addresses of the current group are consistent in representation and comparison.

Still taking the example shown in FIG. 11, the expected PCs after the target expected PC8000_0220 are 8000_0224, 8000_0228, 8000 _0230in that order, and the actual PCs at the corresponding locations after the actual starting PC8000_0220 are 8000_0224, 8000_0228, 8000 _0230in that order, i.e., the expected PCs after the target expected PC8000_0220 are consistent with the actual PCs at the corresponding locations after the actual starting PC8000_0220, indicating that the comparison result representations corresponding to the actual instruction addresses of the first set are consistent in comparison, and then continuing to compare the second set.

Specifically, the reference expected PC for the first miss tag error3 in the second set of miss tags is 8000\ u 0234 and the actual start PC for the second set of actual instruction addresses is 8000_0240. From the reference expected PC8000_0234, the target expected PC8000_0240 is looked up. The expected PC after the target expected PC8000_0240 is 8000_0244, and the actual PC at the corresponding position after the actual start PC8000_0240 is 8000_0244, and the comparison is consistent, i.e., the comparison result corresponding to the second set of actual instruction addresses indicates that the comparison is consistent, indicating that the circuit function of the trace encoder is correct.

Referring to fig. 13, a schematic diagram of a fifth file comparison provided by the embodiment of the present application is shown, in which the expected PC after the target expected PC8000_0240 is 8000_0244, the actual PC at the corresponding position after the actual start PC8000_0240 is 8000_0242, and the comparison inconsistency, i.e., the comparison result corresponding to the second set of actual instruction addresses represents the comparison inconsistency, indicates that the circuit function of the trace encoder is incorrect.

It should be noted that the above-listed desired PC files and actual PC files are only simple examples, and are not specifically limited herein.

Based on the mode, in the process of comparing the expected PC file with the actual PC file, the inconsistent comparison caused by abnormal non-circuit function can be identified and avoided, and therefore the accuracy of detecting the circuit function of the tracking encoder is improved.

Fig. 14 is a schematic diagram of an implementation flow of a circuit testing method in an embodiment of the present application, where the implementation flow of the method is as follows:

step S1401: acquiring an output retirement instruction address and other attribute information of a processor;

step S1402: compressing the retired instruction address and other attribute information output by the processor through a to-be-tested tracking encoder to obtain a plurality of target compressed data packets;

step S1403: inputting a plurality of target compressed data packets into a memory in a trace encoder;

step S1404: acquiring a target compressed data packet normally output by a memory and an overflow prompt data packet output when the memory overflows;

step S1405: analyzing the target compressed data packet and the overflow prompt data packet to generate an actual instruction address file;

step S1406: generating an expected instruction address file based on the retired instruction address;

step S1407: comparing the expected instruction address file with the actual instruction address file;

step S1408: judging whether the expected instruction address file is consistent with the actual instruction address file, if so, executing a step S1409, otherwise, executing a step S1410;

step S1409: determining that the tracking encoder circuit is functioning correctly;

step S1410: it is determined that the circuit of the tracking encoder is not functioning properly.

When step S1407 is executed, the expected instruction address file and the actual instruction address file may be compared specifically as follows:

fig. 15 is a schematic diagram of a specific implementation process of file comparison in the embodiment of the present application, and the specific implementation process is as follows:

step S1501: taking each continuously existing line loss mark in the actual PC file as a batch of loss marks, and taking each continuously existing line actual PC after the batch of loss marks as a corresponding group of actual PCs;

step S1502: comparing the actual PCs of all lines before the first batch of loss marks with the expected PCs of corresponding lines in the expected PC file respectively;

step S1503: judging whether the two are consistent, if so, executing a step 1504, otherwise, executing a step 1508;

step S1504: comparing the corresponding groups of actual PCs with the expected PC files in sequence according to the sequence of the lost marks of each group;

step S1505: judging whether the comparison results corresponding to the actual PCs of the current group are consistent, if so, executing a step 1506, otherwise, executing a step 1508;

step S1506: judging whether the current group is the last group, if so, executing the step 1507, otherwise, returning to execute the step 1504;

step 1507: determining that the tracking encoder circuit is functioning correctly;

step S1508: it is determined that the circuit of the tracking encoder is not functioning properly.

When step S1504 is executed, the following method may be specifically referred to compare the corresponding groups of actual PCs with the expected PC file, so as to obtain corresponding comparison results:

fig. 16 is a schematic diagram of a specific implementation process for obtaining a comparison result of an actual PC of a current group in the embodiment of the present application, where the specific implementation process is as follows:

step S1601: taking an expected PC corresponding to a first lost mark in the current batch of lost marks in the expected PC file as a reference expected PC, and taking a first row of actual PCs in a current group of actual PCs as an actual starting PC;

step S1602: sequentially inquiring expected PCs which are the same as the actual starting PC from the reference expected PC in the expected PC file;

step S1603: judging whether the query is received, if so, executing 1604, otherwise, executing 1608;

step S1604: taking an expected PC with the same actual initial instruction address in the expected PC file as a target expected PC;

step S1605: comparing the expected PC after the target PC address with the actual PC at the corresponding position after the actual starting PC;

step S1606: judging whether the two are consistent, if so, executing a step 1607, otherwise, executing a step 1608;

step S1607: the representation and comparison of comparison results corresponding to the current group of actual instruction addresses are consistent;

step S1608: and representing and contrasting inconsistent contrast results corresponding to the actual instruction addresses of the current group.

Based on the same inventive concept, the embodiment of the application provides a circuit testing device. Referring to fig. 17, a schematic diagram of a component structure of a circuit testing apparatus 1700 includes:

a first obtaining unit 1701, configured to obtain a target compressed data packet normally output by a memory in a to-be-tested tracking encoder and an overflow prompt data packet output when the memory overflows; the target compressed data packet is input into the memory after the retirement instruction address and other attribute information output by the processor are compressed by the tracking encoder;

a generating unit 1702, configured to generate an actual instruction address file by parsing the target compressed data packet and the overflow hint data packet;

and a comparison unit 1703 configured to compare the expected instruction address file with the actual instruction address file, and analyze the circuit function of the tracking encoder according to a comparison result, where the expected instruction address file is generated based on the retired instruction address.

Optionally, the expected instruction address file contains a plurality of rows of expected instruction addresses, and the actual instruction address file contains a plurality of rows of actual instruction addresses and at least one row of miss flags; the loss mark is used for representing the overflow of the memory and mark information corresponding to the overflow prompt data packet; the expected instruction address and the actual instruction address both belong to retired instruction addresses;

the comparison unit 1703 is specifically configured to:

comparing the actual instruction addresses of each line before the first batch of loss marks with the expected instruction addresses of corresponding lines in the expected instruction address file respectively;

and if the actual instruction addresses are consistent with the expected instruction address files, comparing the corresponding groups of actual instruction addresses with the expected instruction address files in sequence according to the sequence of each batch of lost marks, and analyzing the circuit function of the tracking encoder according to the comparison result.

Optionally, the comparison unit 1703 is specifically configured to:

if the comparison result representation corresponding to the actual instruction address of the current group is determined to be consistent in comparison, continuing to compare the next group;

Optionally, the second obtaining unit 1704 is configured to obtain a comparison result corresponding to the current group of actual instruction addresses in the following manner:

taking an expected instruction address corresponding to a first lost mark in the current batch of lost marks in the expected instruction address file as a reference expected instruction address, and taking a first line of actual instruction addresses in the current group of actual instruction addresses as actual initial instruction addresses;

sequentially inquiring expected instruction addresses which are the same as the actual initial instruction addresses from the reference expected instruction addresses in the expected instruction address file;

if the target expected instruction address is found, taking the expected instruction address which is the same as the actual initial instruction address in the expected instruction address file as the target expected instruction address; and comparing the expected instruction address after the target expected instruction address with the actual instruction address at the corresponding position after the actual starting instruction address to obtain a corresponding comparison result.

The second obtaining unit 1704 is represented by a dashed box, and represents that the unit is a newly added unit when the corresponding optional step is executed. Here, the method is only a simple example, and the new method may be adopted, or other methods may also be adopted, and the present disclosure is not limited specifically.

Optionally, the comparison unit 1703 is specifically configured to:

if the expected instruction address behind the target expected instruction address is inconsistent with the actual instruction address at the corresponding position behind the actual initial instruction address, determining that the representation and comparison of the comparison result corresponding to the actual instruction address of the current group are inconsistent;

Optionally, the generating unit 1702 is specifically configured to:

analyzing the overflow prompt data packet through a tracking decoder to obtain an overflow prompt decompression data packet, and writing a loss mark into an actual instruction address file based on prompt information in the overflow prompt decompression data packet; the loss mark is used for representing the overflow of the memory, and mark information corresponding to the overflow prompt data packet.

Optionally, the apparatus further comprises:

a writing unit 1705, configured to, if there are multiple consecutive target decompressed data packets, perform the following operations for each two adjacent target decompressed data packets:

The write unit 1705 is represented by a dashed box, and represents that the unit is a newly added unit when the corresponding optional step is executed. Here, the method is only a simple example, and the new method may be adopted, or other methods may also be adopted, and the present disclosure is not limited specifically.

Optionally, the memory is a first-in first-out memory.

For convenience of description, the above parts are separately described as modules (or units) according to functional division. Of course, the functionality of the various modules (or units) may be implemented in the same one or more pieces of software or hardware when implementing the present application.

Having described the method and apparatus for testing circuits according to exemplary embodiments of the present application, an electronic device according to another exemplary embodiment of the present application is next described.

As will be appreciated by one skilled in the art, aspects of the present application may be embodied as a system, method or program product. Accordingly, various aspects of the present application may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

The electronic equipment is based on the same inventive concept as the method embodiment, and the embodiment of the application also provides the electronic equipment. In this embodiment, the electronic device may be configured as shown in fig. 18, and include a memory 1801, a communication module 1803, and one or more processors 1802.

The memory 1801 is used for storing computer programs executed by the processor 1802. The memory 1801 may mainly include a program storage area and a data storage area, where the program storage area may store an operating system, a program required for running an instant messaging function, and the like; the storage data area can store various instant messaging information, operation instruction sets and the like.

The memory 1801 may be a volatile memory (RAM), such as a random-access memory (RAM); the memory 1801 may also be a non-volatile memory (non-volatile memory), such as a read-only memory (rom), a flash memory (flash memory), a hard disk (HDD) or a solid-state drive (SSD); or the memory 1801 is any other medium that can be used to carry or store a desired computer program in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 1801 may be a combination of the above memories.

The processor 1802, may include one or more Central Processing Units (CPUs), or be a digital processing unit, and the like. A processor 1802, configured to implement the test method of the above circuit when calling the computer program stored in the memory 1801.

The communication module 1803 is used for communicating with terminal devices and other servers.

The embodiment of the present application does not limit the specific connection medium among the memory 1801, the communication module 1803 and the processor 1802. In fig. 18, the memory 1801 and the processor 1802 are connected by a bus 1804, the bus 1804 is depicted by a thick line in fig. 18, and the connection manner between other components is merely illustrative and not limited. The bus 1804 may be divided into an address bus, a data bus, a control bus, and the like. For ease of description, only one thick line is depicted in FIG. 18, but only one bus or one type of bus is not depicted.

The memory 1801 stores a computer storage medium, and the computer storage medium stores computer-executable instructions for implementing a method for testing a circuit according to an embodiment of the present application. The processor 1802 is configured to perform the above-described circuit testing method, as shown in fig. 2.

A computing device 1900 according to this embodiment of the application is described below with reference to fig. 19. The computing device 1900 of fig. 19 is only one example and should not be taken as limiting the scope of use and functionality of embodiments of the present application.

As with fig. 19, computing device 1900 is embodied in a general purpose computing device. Components of computing device 1900 may include, but are not limited to: the at least one processing unit 1901, the at least one memory unit 1902, and a bus 1903 that couples various system components (including the memory unit 1902 and the processing unit 1901).

Bus 1903 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of a variety of bus architectures.

The memory unit 1902 may include readable media in the form of volatile memory, such as Random Access Memory (RAM) 1921 and/or cache memory 1922, and may further include Read Only Memory (ROM) 1923.

The memory unit 1902 may also include a program/utility 1925 having a set (at least one) of program modules 1924, such program modules 1924 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

Computing device 1900 may also communicate with one or more external devices 1904 (e.g., keyboard, pointing device, etc.), with one or more devices that enable a user to interact with computing device 1900, and/or with any devices (e.g., router, modem, etc.) that enable computing device 1900 to communicate with one or more other computing devices. Such communication may occur via an input/output (I/O) interface 1905. Also, computing device 1900 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) through network adapter 1906. As shown in fig. 19, the network adapter 1906 communicates with other modules for the computing device 1900 over the bus 1903. It should be understood that although not shown, other hardware and/or software modules may be used in conjunction with the computing device 1900, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

In some possible embodiments, various aspects of the testing method of the circuit provided by the present application may also be implemented in the form of a program product including a computer program for causing an electronic device to perform the steps in the testing method of the circuit according to various exemplary embodiments of the present application described above in this specification when the program product is run on the electronic device, for example, the electronic device may perform the steps as shown in fig. 2.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The program product of embodiments of the present application may employ a portable compact disc read only memory (CD-ROM) and include a computer program, and may be run on a computing device. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with a command execution system, apparatus, or device.

A readable signal medium may include a propagated data signal with a readable computer program embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with a command execution system, apparatus, or device.

The computer program embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer programs for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer program may execute entirely on the user computing device, partly on the user equipment, as a stand-alone software package, partly on the user computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

It should be noted that although several units or sub-units of the apparatus are mentioned in the above detailed description, such division is merely exemplary and not mandatory. Indeed, the features and functions of two or more of the units described above may be embodied in one unit, according to embodiments of the application. Conversely, the features and functions of one unit described above may be further divided into embodiments by a plurality of units.

Further, while the operations of the methods of the present application are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method of testing a circuit, the method comprising:

2. The method of claim 1, wherein the expected instruction address file contains a plurality of lines of expected instruction addresses, the actual instruction address file contains a plurality of lines of actual instruction addresses and at least one line miss flag; the loss mark is used for representing that the memory overflows and is mark information corresponding to an overflow prompt data packet; the expected instruction address and the actual instruction address both belong to retired instruction addresses;

the comparing the expected instruction address file with the actual instruction address file, and analyzing the circuit function of the tracking encoder according to the comparison result includes:

and if the actual instruction addresses are consistent with the expected instruction address file, comparing the corresponding groups of actual instruction addresses with the expected instruction address file in sequence according to the sequence of the lost marks of each group, and analyzing the circuit function of the tracking encoder according to the comparison result.

3. The method of claim 2, wherein said comparing respective sets of actual instruction addresses with said expected instruction address file in sequence according to the sequence of each batch of lost tags, and analyzing the circuit function of said tracking encoder according to the comparison result, comprises:

4. The method of claim 3, wherein the comparison result corresponding to the current set of actual instruction addresses is obtained by:

taking an expected instruction address corresponding to a first lost mark in the current batch of lost marks in the expected instruction address file as a reference expected instruction address, and taking a first line of actual instruction addresses in a current group of actual instruction addresses as actual initial instruction addresses;

5. The method as in claim 4 wherein comparing the expected instruction address after the target expected instruction address with the actual instruction address at the corresponding location after the actual starting instruction address to obtain a corresponding comparison comprises:

6. The method of claim 1, wherein generating a real instruction address file by parsing the target compressed packet and the overflow hint packet comprises:

7. The method of claim 6, wherein the method further comprises:

if a plurality of continuous target decompressed data packets exist, for every two adjacent target decompressed data packets, the following operations are respectively executed:

8. The method of any of claims 1-7, wherein the memory is a first-in-first-out memory.

9. An apparatus for testing an electrical circuit, the apparatus comprising:

the generating unit is used for generating an actual instruction address file by analyzing the target compressed data packet and the overflow prompting data packet;

10. An electronic device, characterized in that it comprises a processor and a memory, wherein the memory stores a computer program which, when executed by the processor, causes the processor to carry out the steps of the method according to any one of claims 1 to 8.