CN115858218A - Failure rate evaluation method and device suitable for CPU unit of relay protection device - Google Patents
Failure rate evaluation method and device suitable for CPU unit of relay protection device Download PDFInfo
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Abstract
The invention discloses a failure rate evaluation method and a device suitable for a CPU unit of a relay protection device, wherein the method comprises the following steps: based on the failure rate prediction criteria and the failure rate influencing factors, calculating to obtain a first failure rate of components in a CPU unit of the relay protection device; dividing a CPU unit into a plurality of functional units and establishing a fault tree; establishing and solving a state transfer equation according to the fault tree and the first failure rate of each component to obtain a second failure rate of each component; and according to the fault tree and the second failure rate of each component, the steady-state failure rate of the CPU unit is obtained through superposition. By adopting the embodiment of the invention, the specific and stable second failure rate of each component under the long-term working condition is obtained through the calculation of the fault tree and the state transfer equation, so that the change of various parameters in the long-term tracking of the component working process is avoided; in addition, the fault tree is combined with the second failure rate of each component to realize accurate evaluation of the steady-state fault rate of the CPU unit.
Description
Technical Field
The invention relates to the field of power system control, in particular to a failure rate evaluation method and device suitable for a CPU (central processing unit) of a relay protection device.
Background
With the continuous development of power systems and the continuous expansion of the scale of power grids, the total amount of equipment of a secondary system of a transformer substation is more and more, the functional requirements are more and more abundant, the system is more and more complex, the secondary protection equipment has the development trend of electronization, computerization and informatization, and the failure rate of the secondary system is in an increasing trend. In addition, the refined management and the full life cycle management of the relay protection equipment also need to carry out reliability evaluation of the secondary system so as to accurately master the life cycle and the overhaul and maintenance cycle of the system or the equipment, so that the overhaul work of national network workers is more reasonable and effective, spare parts are more economical and effective, and the optimization target of the full life cycle is finally achieved. The CPU logic operation unit of the relay protection device is used as a core unit of the relay protection device, electronic components loaded on the CPU logic operation unit are more and more, the logic operation unit is more and more complex, and the failure rate calculation of the CPU logic operation unit of the relay protection device is more and more complex. For the evaluation and design of the steady-state failure rate of the CPU logic operation unit of the relay protection device, the prior art generally uses a prediction method or an existing calculation standard, for example: calculating the failure rate of specific components according to the standards of I EC-62380, 217P plus and SR-332, and simply superposing the efficiency; in addition, in the prior art, the CPU logic operation unit of the relay protection device is generally decomposed into a plurality of working states, and failure rates are calculated and summarized in different states to obtain failure rates of components. The former will cause the failure rate of the last obtained CPU logic operation unit to have larger distortion, while the latter will cause the problem that an average working condition is emphasized more in the environment temperature evaluation process and the failure rate calculation process is complicated because the task section is difficult to subdivide and the task section calculation parameters are difficult to obtain.
Disclosure of Invention
The invention provides a failure rate evaluation method and device suitable for a CPU (central processing unit) of a relay protection device, and aims to solve the technical problems of calculation distortion and complicated calculation process when the failure rate of the CPU of the relay protection device is calculated in the prior art.
In order to solve the above technical problem, an embodiment of the present invention provides a failure rate evaluation method for a CPU unit of a relay protection device, including:
calculating to obtain a first failure rate of each component in a CPU unit of the relay protection device according to the failure rate prediction standard and failure rate influence factors;
dividing the CPU unit into a plurality of functional units, and establishing a fault tree according to the functional units;
establishing and solving a state transfer equation according to the fault tree and the first failure rate of each component to obtain a second failure rate of each component;
and superposing to obtain the steady-state failure rate of the CPU unit according to the fault tree and the second failure rate of each component.
According to the method, the first failure rate of each component of the CPU unit of the relay protection device is calculated through the failure rate prediction standard and the influence factors, and then the specific and stable second failure rate of each component under the long-term working condition is obtained through the fault tree and the state transfer equation, so that various parameter changes in the working process of the components are prevented from being tracked for a long time, and the complicated calculation process is avoided; in addition, a fault tree is established for the CPU unit, and the second failure rate of each component is combined to realize accurate evaluation of the steady-state fault rate of the CPU unit, so that the calculation distortion caused by directly and simply superposing the fault rates is avoided.
Further, the calculating, according to the failure rate prediction standard and the failure rate influence factor, to obtain the first failure rate of each component in the CPU unit of the relay protection device specifically includes:
wherein the failure rate influencing factors comprise: temperature coefficient, electrical stress, quality factor, and steady state failure rate;
determining a failure rate prediction standard formula according to the failure rate prediction standard; acquiring the temperature coefficient of each component, the electrical stress of each component, the quality factor of each component and the steady-state fault rate of each component;
and calculating to obtain a first failure rate of each component according to the failure rate prediction standard formula, the temperature coefficient of each component, the electrical stress of each component, the quality factor of each component and the steady-state failure rate of each component.
Further, the obtaining of the temperature coefficient of each component specifically includes:
after running a test program in the CPU unit for a preset time, measuring the surface temperature of each component in the CPU unit by using a thermocouple temperature sensor;
calculating to obtain the actual working temperature of each component according to the surface temperature of each component, the junction temperature of each component and the power consumption of each component;
and calculating to obtain the temperature coefficient according to the actual working temperature and the environmental temperature of each component.
According to the method, the actual working condition of the CPU unit is simulated by running the test program on the CPU unit according to the preset market, and the thermocouple temperature sensor is used for measuring each component, so that more accurate surface temperature is obtained, the accuracy of subsequent first failure rate and CPU unit steady-state failure rate evaluation is improved, and the calculation distortion is further avoided.
Further, establishing and solving a state transition equation according to the fault tree and the first failure rate of each component, and obtaining a second failure rate of each component, specifically:
setting the repair rate of the relay protection device, and establishing the state transfer equation of each component according to the repair rate and the first failure rate of each component;
solving the state transition matrix of the state transition equation of each component by the nth power to obtain a convergence matrix of each component;
and solving the convergence matrix of each component to obtain a second failure rate of each component.
According to the invention, the specific and stable second failure rate of each component under the long-term working condition can be calculated by establishing the state transfer equation of each component and combining the first failure rate, so that various parameter changes in the working process of the components are prevented from being tracked for a long time, and the complicated calculation process is avoided.
Further, the establishing the state transition equation of each component according to the repair rate and the first failure rate of each component specifically includes:
establishing the state transition equation of each component through a Markov chain according to the repair rate and the first failure rate of each component; wherein the state transition equation is:
wherein λ is 1 For the first failure rate, μ is the repair rate.
Further, the expression of the second failure rate is:
wherein λ is 2 To the second failure rate, λ 1 For the first failure rate, μ is the repair rate.
Further, the establishing a fault tree according to the functional unit specifically includes:
wherein the functional unit comprises: the device comprises a logic unit, a memory unit, a control unit and an external interface unit;
establishing a fault tree by adopting logic or as a connection relation according to the logic unit, the memory unit, the control unit and the external interface unit; and establishing respective sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit by adopting a logic or connection relation among components in the logic unit, the memory unit, the control unit and the external interface unit.
Further, the steady-state failure rate of the CPU unit is obtained by superimposing according to the fault tree and the second failure rates of the components, and specifically:
according to the second failure rate of each component and the respective sub-fault trees of the logic unit, the memory unit, the control unit and the external interface unit, the steady-state failure rates of the respective sub-fault trees of the logic unit, the memory unit, the control unit and the external interface unit are obtained through superposition;
and superposing the steady state failure rates of the sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit to obtain the steady state failure rate of the CPU unit.
According to the method, the CPU unit is divided according to functions, the fault tree and the sub fault trees of each fault tree are established according to the logical OR connection relation, after the second failure rate of each component is obtained, the second failure rate of each component is superposed and calculated according to the corresponding fault tree and the connection relation, the accurate evaluation of the steady-state failure rate of the CPU unit is realized, and the calculation distortion caused by directly and simply superposing the fault rates is avoided.
On the other hand, an embodiment of the present invention further provides a failure rate evaluation device suitable for a CPU unit of a relay protection device, including: the failure rate calculation module comprises a first failure rate calculation module, a failure tree establishment module, a second failure rate calculation module and a third failure rate calculation module;
the first failure rate calculation module is used for calculating and obtaining first failure rates of all components in a CPU unit of the relay protection device according to failure rate prediction standards and failure rate influence factors;
the fault tree building module is used for dividing the CPU unit into a plurality of functional units and building a fault tree according to the functional units;
the second failure rate calculation module is used for establishing and solving a state transition equation according to the fault tree and the first failure rates of the components to obtain second failure rates of the components;
and the third fault rate calculation module is used for obtaining the steady-state failure rate of the CPU unit by superposition according to the fault tree and the second failure rates of the components.
According to the method, the first failure rate of each component of the CPU unit of the relay protection device is calculated through the failure rate prediction standard and the influence factors, and then the specific and stable second failure rate of each component under the long-term working condition is obtained through the fault tree and the state transfer equation, so that various parameter changes in the working process of the components are prevented from being tracked for a long time, and the complicated calculation process is avoided; in addition, a fault tree is established for the CPU unit, the second failure rate of each component is combined to realize accurate evaluation of the steady-state fault rate of the CPU unit, and calculation distortion caused by direct and simple superposition of the fault rate is avoided.
Further, the second failure rate calculation module includes: the system comprises an equation establishing unit, a calculating unit and a matrix solving unit;
the equation establishing unit is used for setting a repair rate of the relay protection device and establishing the state transition equation of each component according to the repair rate and the first failure rate of each component;
the calculation unit is used for solving the state transition matrix of the state transition equation of each component by the nth power to obtain the convergence matrix of each component;
the matrix solving unit is used for solving the convergence matrix of each component to obtain a second failure rate of each component.
According to the invention, the specific and stable second failure rate of each component under the long-term working condition can be calculated by establishing the state transfer equation of each component and combining the first failure rate, so that various parameter changes in the long-term tracking of the component working process are avoided, and the complicated calculation process is avoided.
Drawings
Fig. 1 is a schematic flowchart of an embodiment of a failure rate evaluation method for a CPU unit of a relay protection device according to the present invention;
fig. 2 is a schematic flowchart of another embodiment of a failure rate evaluation method for a CPU unit of a relay protection device according to the present invention;
fig. 3 is a schematic structural diagram of an embodiment of a failure rate evaluation device suitable for a CPU unit of a relay protection device according to the present invention;
fig. 4 is a schematic structural diagram of another embodiment of the failure rate evaluation device suitable for the CPU unit of the relay protection device according to the present invention;
figure 5 is a schematic diagram of a markov chain provided by the present invention;
FIG. 6 is a schematic diagram of one embodiment of a fault tree provided by the present invention;
FIG. 7 is a diagram of an embodiment of a sub-fault tree provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Referring to fig. 1, a schematic flow chart of an embodiment of a failure rate evaluation method for a CPU unit of a relay protection device according to the present invention mainly includes steps 101 to 104, which are as follows:
step 101: and calculating to obtain the first failure rate of each component in the CPU unit of the relay protection device according to the failure rate prediction standard and the failure rate influence factors.
In this embodiment, the calculating, according to the failure rate prediction standard and the failure rate influence factor, to obtain the first failure rate of each component in the CPU unit of the relay protection device specifically includes: wherein the failure rate influencing factors comprise: temperature coefficient, electrical stress, quality factor, and steady state failure rate; determining a failure rate prediction standard formula according to the failure rate prediction standard; acquiring the temperature coefficient of each component, the electrical stress of each component, the quality factor of each component and the steady-state failure rate of each component; and calculating to obtain a first failure rate of each component according to the failure rate prediction standard formula, the temperature coefficient of each component, the electrical stress of each component, the quality factor of each component and the steady-state failure rate of each component.
In the embodiment, the failure rate prediction standard can adopt an SR-332 standard, and the SR-332 standard is compiled based on data of common telecommunication equipment and is suitable for most relay protection devices for indoor substations. According to the SR-332 standard, analyzing the influence of factors such as quality factors, temperature coefficients and electric stress of a steady-state fault rate device of equipment to obtain a steady-state failure rate formula of the device: lambda [ alpha ] BBi ＝ Gi π Qi π Si π Ti (ii) a Wherein λ is BBi To a first failure rate, λ Gi For steady state failure rate, pi Qi Is a quality factor of pi Si For electrical stress, pi Ti Is the temperature coefficient.
Further, the obtaining of the temperature coefficient of each component specifically includes:
after running a test program in the CPU unit for a preset time, measuring the surface temperature of each component in the CPU unit by using a thermocouple temperature sensor;
calculating to obtain the actual working temperature of each component according to the surface temperature of each component, the junction temperature of each component and the power consumption of each component;
and calculating to obtain the temperature coefficient according to the actual working temperature and the environment temperature of each component.
In the present embodiment, the expression of the temperature coefficient is:
wherein K is Boltzmann constant, and K =8.62 × 10 -5 eV/ ° k，E a For activation energy, the activation energy is correlated to a temperature rating, the specific temperature rating being given by the SR-332 handbook. T is a unit of 0 The temperature is ambient, kelvin temperature is adopted; t is a unit of 1 For the actual operating temperature, kelvin temperature was used.
In the embodiment, a test program is run in the CPU unit for simulating a high-load state under the actual working condition of the CPU unit; in addition, the preset time period may be 12 hours or more; the thermocouple temperature sensor for measuring the surface temperature of each component can be a PT100 thermocouple temperature sensor, and the thermocouple temperature sensor is used for detecting the temperature of a CPU (central processing unit) in the case, wherein the expression of the actual working temperature is T 1 ＝ 1top +jc×p，T 1top The surface temperature of the component, theta jc the junction temperature of the component, and p the power consumption of the component; in addition, the junction temperature and the power consumption of each component can be obtained through a data manual of the component.
According to the invention, the actual working condition of the CPU unit is simulated by running the test program on the CPU unit according to the preset market, and the surface temperature is more accurately obtained by measuring each component through the thermocouple temperature sensor, so that the accuracy of subsequent first failure rate and CPU unit steady-state failure rate evaluation is improved, and the calculation distortion is further avoided.
In this embodiment, for electrical stress, a specific analysis is required for different devices; the expression for electrical stress in the SR-332 standard is:
wherein p is 0 Is prepared from radix GinsengThe stress is taken into consideration, and the value is 50 percent; p is a radical of 1 The percentage value of the electrical stress of the component is shown, and m is the electrical stress grade. The value of the electrical stress level may be obtained by SR-332. The expression of the percentage value of the electrical stress of the component is as follows: />
Wherein V DC For applying a DC voltage, V, to the components ACmax Is the AC peak voltage of the component, and U is the rated voltage on the component.
In this embodiment, the quality factor of the device is mainly influenced by the supplier, electrical/mechanical, and device manufacturing process control, and the quality factor characterizes the efforts of the device manufacturer to improve the quality of the chip and the device. The purchased devices of the relay protection device have determined important electrical characteristics, such as: electrical, mechanical, thermal and environmental, and acceptable quality levels, components and device manufacturers of components are certified and specified on approved parts or lists. Therefore, the quality factors of the CPU units in the relay protection device can be uniformly considered as pi Qi ＝1。
In this embodiment, obtaining the steady-state failure rate of each component includes: estimating and obtaining the steady-state fault rate of each component according to the number of transistors in the chip of the CPU unit; or, carrying out experiments for preset times on the test components corresponding to the components, and simulating to obtain the steady-state fault rate of the components.
Step 102: and dividing the CPU unit into a plurality of functional units, and establishing a fault tree according to the functional units.
Further, the establishing a fault tree according to the functional unit specifically includes:
wherein the functional unit comprises: the device comprises a logic unit, a memory unit, a control unit and an external interface unit;
establishing a fault tree by adopting logic or as a connection relation according to the logic unit, the memory unit, the control unit and the external interface unit; and establishing respective sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit by adopting a logic or connection relation among components in the logic unit, the memory unit, the control unit and the external interface unit.
Fig. 6 is a schematic diagram of an embodiment of a fault tree provided in the present invention, in which a CPU logical operation unit refers to a CPU unit in the embodiment of the present invention; the external interface unit is used for acquiring a sampling value; the memory unit is used for storing the acquired sampling data; the logic unit is used for intermittently or continuously extracting data from the storage unit; the control unit is used for executing relevant specific commands.
In this embodiment, each functional unit forms a series model through logic or, that is, when any functional unit fails, it is determined that the CPU unit fails; fig. 7 is a schematic diagram of an embodiment of a sub fault tree provided in the present invention, in which elements 1 to k +1 represent k +1 components in a logic unit, and these components form a sub fault tree of the logic unit through a logic or a serial model; the components in other functional units form the respective sub fault trees of other functional units through logic or forming a series model.
Step 103: and establishing and solving a state transition equation according to the fault tree and the first failure rate of each component, and obtaining a second failure rate of each component.
In this embodiment, the state transition equation may adopt a state transition equation of a markov chain, and is used to solve a failure rate, i.e., a second failure rate, of each component under a long-term working condition, so as to avoid tracking various parameter changes in a working process of the component for a long time, thereby avoiding a cumbersome calculation process.
Step 104: and superposing the fault tree and the second failure rate of each element to obtain the steady-state failure rate of the CPU unit.
Further, the steady-state failure rate of the CPU unit is obtained by superimposing according to the fault tree and the second failure rates of the components, and specifically:
according to the second failure rate of each component and the respective sub-fault trees of the logic unit, the memory unit, the control unit and the external interface unit, the steady-state failure rates of the respective sub-fault trees of the logic unit, the memory unit, the control unit and the external interface unit are obtained through superposition;
and superposing the steady state failure rates of the sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit to obtain the steady state failure rate of the CPU unit.
According to the method, the CPU unit is divided according to functions, the fault tree and the sub fault trees of each fault tree are established according to the logical OR connection relation, after the second failure rate of each component is obtained, the second failure rate of each component is superposed and calculated according to the corresponding fault tree and the connection relation, the accurate evaluation of the steady-state failure rate of the CPU unit is realized, and the calculation distortion caused by directly and simply superposing the fault rates is avoided.
In this embodiment, the steady-state failure rates of the sub fault trees of the logic unit, the memory unit, the control unit, and the external interface unit may be respectively expressed as:
/>
wherein +>
To/is>
And the second failure rate of each of the n components in the CPU unit under the long-term working condition is shown. Superposing the second failure rates of all the components in the sub-fault tree to obtain the steady-state failure rate of the sub-fault tree, and then superposing all the sub-faultsSuperposing the steady state failure rates of the trees to obtain the steady state failure rate of the fault tree or the CPU unit; the process of the superposition calculation can be expressed as: />
Wherein λ is Subtree 1 To lambda Subtree 5 Respectively representing the steady state failure rates, lambda, of the sub-fault trees of the logic unit, the memory unit, the control unit and the external interface unit CPU Is the steady state failure rate of the CPU unit.
Fig. 2 is a schematic flow chart of another embodiment of the failure rate evaluation method for the CPU unit of the relay protection device according to the present invention. The main difference between fig. 2 and fig. 1 is that fig. 2 includes steps 201-203, which are as follows:
in this embodiment, step 103 specifically includes steps 201-203.
Step 201: and setting the repair rate of the relay protection device, and establishing the state transfer equation of each component according to the repair rate and the first failure rate of each component.
In this embodiment, in general, when a fault occurs, the relay protection device requires to be repaired within 24 hours, so the repair rate may be set to μ =1/24; wherein μ is the repair rate.
Further, the establishing the state transition equation of each component according to the repair rate and the first failure rate of each component specifically includes:
establishing the state transition equation of each component through a Markov chain according to the repair rate and the first failure rate of each component; wherein the state transition equation is:
wherein λ is 1 For the first failure rate, μ is the repair rate.
Referring to fig. 5, a schematic diagram of a markov chain provided by the present invention is shown, wherein when n is 1, the failure rate from state 0 to state 1 is λ 1 While the repair rate for state 1 to state 0 is μ.
Step 202: and solving the state transition matrix of the state transition equation of each component by the nth power to obtain the convergence matrix of each component.
In this embodiment, when the state transition matrix of the state transition equation is raised to the nth power, the expression of the convergence matrix obtained is:
wherein, the matrix p n The second-order matrix has one and only one eigenvalue, the eigenvalue is 1, four factors in the matrix are not 0, and the transition between states is arbitrary and uncontrolled, so that the transition probability may be considered not to change, that is, the state transition matrix may be considered to be a convergence matrix.
Step 203: and solving the convergence matrix of each component to obtain a second failure rate of each component.
In this embodiment, according to the characteristic of the convergence matrix, each component approaches a fixed value in the case of long-term operation, and the fixed value is used as the second failure rate of the component. Therefore, the second failure rate of the component is not affected by the initial state of the component and finally approaches to the second failure rate.
Further, the expression of the second failure rate is:
wherein λ is 2 To a second failure rate, λ 1 Is the first failure rate, μ is the repair rate.
In the present embodiment, as long as the CPU unit architecture does not change, that is, the fault tree architecture does not change, the CPUSecond failure rates of the components in the unit
Only the specific first failure rate lambda of the component is varied 1 . When the specific model of the CPU logic operation unit component changes later, the steady state failure rate of the component can be obtained under the long-term working condition only by recalculating the failure rate of the component and substituting the failure rate into the steady state failure rate formula again, so that the steady state failure rate of the CPU unit can be obtained, and the calculation step of recalculating the steady state failure rate is reduced.
Fig. 3 is a schematic structural diagram of an embodiment of a failure rate evaluation apparatus for a CPU unit of a relay protection apparatus according to the present invention, which mainly includes: a first failure rate calculation module 301, a fault tree establishment module 302, a second failure rate calculation module 303, and a third failure rate calculation module 304.
According to the invention, the specific and stable second failure rate of each component under the long-term working condition can be calculated by establishing the state transfer equation of each component and combining the first failure rate, so that various parameter changes in the working process of the components are prevented from being tracked for a long time, and the complicated calculation process is avoided.
In this embodiment, the first failure rate calculating module 301 is configured to calculate and obtain a first failure rate of each component in a CPU unit of the relay protection device according to the failure rate prediction standard and the failure rate influencing factor.
In this embodiment, the first failure rate calculation module 301 includes a standard determination unit and a first failure rate calculation unit; wherein the failure rate influencing factors comprise: temperature coefficient, electrical stress, quality factor, and steady state failure rate; the standard determining unit is used for determining a failure rate prediction standard formula according to the failure rate prediction standard; acquiring the temperature coefficient of each component, the electrical stress of each component, the quality factor of each component and the steady-state fault rate of each component; the first failure rate calculation unit is used for calculating and obtaining the first failure rate of each component according to the failure rate prediction standard formula, the temperature coefficient of each component, the electric stress of each component, the quality factor of each component and the steady-state failure rate of each component.
The fault tree building module 302 is configured to divide the CPU unit into a plurality of functional units, and build a fault tree according to the functional units.
In this embodiment, the fault tree setup module 302 includes a fault tree setup unit; wherein the functional unit comprises: the device comprises a logic unit, a memory unit, a control unit and an external interface unit; the fault tree establishing unit is used for establishing a fault tree by adopting logic or as a connection relation according to the logic unit, the memory unit, the control unit and the external interface unit; and establishing respective sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit by adopting a logic or connection relation among components in the logic unit, the memory unit, the control unit and the external interface unit.
The second failure rate calculation module 303 is configured to establish and solve a state transition equation according to the fault tree and the first failure rates of the components, and obtain second failure rates of the components.
The third failure rate calculation module 304 is configured to obtain a steady-state failure rate of the CPU unit by stacking the failure tree and the second failure rates of the components.
In the present embodiment, the third failure rate calculation module 304 includes a first superposition calculation unit and a second superposition calculation unit; the first superposition calculation unit is used for superposing to obtain the steady-state failure rates of the sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit according to the second failure rates of the components and the sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit; the second superposition calculation unit is used for superposing the steady-state failure rates of the sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit to obtain the steady-state failure rate of the CPU unit.
Referring to fig. 4, a schematic structural diagram of another embodiment of the failure rate evaluation device suitable for a CPU unit of a relay protection device provided in the present invention is shown, wherein the second failure rate calculation module 303 includes: an equation establishing unit 401, a calculating unit 402, and a matrix solving unit 403.
In this embodiment, the equation establishing unit 401 is configured to set a repair rate of the relay protection device, and establish the state transition equation of each component according to the repair rate and the first failure rate of each component.
The calculation unit 402 is configured to perform nth power on a state transition matrix of the state transition equation of each component, so as to obtain a convergence matrix of each component.
The matrix solving unit 403 is configured to solve the convergence matrix of each component, so as to obtain a second failure rate of each component.
According to the method, the first failure rate of each component of the CPU unit of the relay protection device is calculated through the failure rate prediction standard and the influence factors, and then the specific and stable second failure rate of each component under the long-term working condition is obtained through the fault tree and the state transfer equation, so that various parameter changes in the working process of the components are prevented from being tracked for a long time, and the complicated calculation process is avoided; in addition, a fault tree is established for the CPU unit, the second failure rate of each component is combined to realize accurate evaluation of the steady-state fault rate of the CPU unit, and calculation distortion caused by direct and simple superposition of the fault rate is avoided.
The above-mentioned embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above-mentioned embodiments are only examples of the present invention and are not intended to limit the scope of the present invention. It should be understood that any modifications, equivalents, improvements and the like, which come within the spirit and principle of the invention, may occur to those skilled in the art and are intended to be included within the scope of the invention.
Claims (10)
1. A failure rate evaluation method suitable for a CPU unit of a relay protection device is characterized by comprising the following steps:
calculating to obtain first failure rates of all components in a CPU unit of the relay protection device according to failure rate prediction standards and failure rate influence factors;
dividing the CPU unit into a plurality of functional units, and establishing a fault tree according to the functional units;
establishing and solving a state transfer equation according to the fault tree and the first failure rate of each component to obtain a second failure rate of each component;
and superposing to obtain the steady-state failure rate of the CPU unit according to the fault tree and the second failure rate of each component.
2. The failure rate evaluation method suitable for the CPU unit of the relay protection device according to claim 1, wherein the calculating, according to the failure rate prediction standard and the failure rate influence factor, to obtain the first failure rate of each component in the CPU unit of the relay protection device specifically includes:
wherein the failure rate influencing factors comprise: temperature coefficient, electrical stress, quality factor, and steady state failure rate;
determining a failure rate prediction standard formula according to the failure rate prediction standard; acquiring the temperature coefficient of each component, the electrical stress of each component, the quality factor of each component and the steady-state fault rate of each component;
and calculating to obtain a first failure rate of each component according to the failure rate prediction standard formula, the temperature coefficient of each component, the electrical stress of each component, the quality factor of each component and the steady-state failure rate of each component.
3. The failure rate evaluation method suitable for the CPU unit of the relay protection device according to claim 2, wherein the obtaining of the temperature coefficient of each component specifically comprises:
after running a test program in the CPU unit for a preset time, measuring the surface temperature of each component in the CPU unit by using a thermocouple temperature sensor;
calculating to obtain the actual working temperature of each component according to the surface temperature of each component, the junction temperature of each component and the power consumption of each component;
and calculating to obtain the temperature coefficient according to the actual working temperature and the environment temperature of each component.
4. The failure rate evaluation method suitable for the CPU unit of the relay protection device according to claim 1, wherein the establishing and solving a state transition equation according to the fault tree and the first failure rate of each component obtains a second failure rate of each component, specifically:
setting the repair rate of the relay protection device, and establishing the state transfer equation of each component according to the repair rate and the first failure rate of each component;
solving the state transition matrix of the state transition equation of each component by the nth power to obtain a convergence matrix of each component;
and solving the convergence matrix of each component to obtain a second failure rate of each component.
5. The failure rate evaluation method suitable for the CPU unit of the relay protection device according to claim 4, wherein the establishing the state transition equation of each component according to the repair rate and the first failure rate of each component specifically includes:
establishing the state transition equation of each component through a Markov chain according to the repair rate and the first failure rate of each component; wherein the state transition equation is:
wherein λ is 1 For the first failure rate, μ is the repair rate.
6. The failure rate evaluation method suitable for the CPU unit of the relay protection device according to claim 5, wherein the second failure rate is expressed by:
wherein λ is 2 To a second failure rate, λ 1 For the first failure rate, μ is the repair rate.
7. The failure rate evaluation method suitable for the CPU unit of the relay protection device according to any one of claims 1 to 6, wherein the establishing a fault tree according to the functional unit specifically comprises:
wherein the functional unit includes: the device comprises a logic unit, a memory unit, a control unit and an external interface unit;
establishing a fault tree by adopting logic or as a connection relation according to the logic unit, the memory unit, the control unit and the external interface unit; and establishing respective sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit by adopting a logic or connection relation among components in the logic unit, the memory unit, the control unit and the external interface unit.
8. The failure rate evaluation method suitable for the CPU unit of the relay protection device according to claim 7, wherein the obtaining of the steady-state failure rate of the CPU unit by superposition according to the fault tree and the second failure rates of the components specifically comprises:
according to the second failure rate of each component and the respective sub-fault trees of the logic unit, the memory unit, the control unit and the external interface unit, the steady-state failure rates of the respective sub-fault trees of the logic unit, the memory unit, the control unit and the external interface unit are obtained through superposition;
and superposing the steady state failure rates of the sub fault trees of the logic unit, the memory unit, the control unit and the external interface unit to obtain the steady state failure rate of the CPU unit.
9. A failure rate evaluation device suitable for a CPU unit of a relay protection device is characterized by comprising: the failure rate calculation module comprises a first failure rate calculation module, a failure tree establishment module, a second failure rate calculation module and a third failure rate calculation module;
the first failure rate calculating module is used for calculating and obtaining a first failure rate of each component in a CPU unit of the relay protection device according to a failure rate prediction standard and failure rate influence factors;
the fault tree building module is used for dividing the CPU unit into a plurality of functional units and building a fault tree according to the functional units;
the second failure rate calculation module is used for establishing and solving a state transition equation according to the fault tree and the first failure rates of the components to obtain second failure rates of the components;
and the third fault rate calculation module is used for obtaining the steady-state failure rate of the CPU unit by superposition according to the fault tree and the second failure rates of the components.
10. The failure rate evaluation device suitable for the CPU unit of the relay protection device according to claim 9, wherein the second failure rate calculation module comprises: the system comprises an equation establishing unit, a calculating unit and a matrix solving unit;
the equation establishing unit is used for setting a repair rate of the relay protection device and establishing the state transfer equation of each component according to the repair rate and the first failure rate of each component;
the calculation unit is used for solving the state transition matrix of the state transition equation of each component by the nth power to obtain the convergence matrix of each component;
the matrix solving unit is used for solving the convergence matrix of each component to obtain a second failure rate of each component.
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