CN115857653A - Control method for reducing chip power consumption - Google Patents
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- CN115857653A CN115857653A CN202211440031.XA CN202211440031A CN115857653A CN 115857653 A CN115857653 A CN 115857653A CN 202211440031 A CN202211440031 A CN 202211440031A CN 115857653 A CN115857653 A CN 115857653A
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Abstract
The invention discloses a control method for reducing chip power consumption, which detects the state of equipment through a clock control module, determines the processing mode of clock gating according to the state of the equipment and controls the clock control module to work, carries out dynamic voltage regulation and dynamic frequency modulation control on a hardware module of a functional unit through a dynamic voltage regulation and frequency modulation control module, adopts a hardware automatic monitoring method to carry out clock and voltage control, has weak software dependence and is easy to operate and control, and the application scene dependence of the embodiment of the invention is weak and convenient to expand. In addition, the embodiment of the invention can dynamically control the clock and the voltage according to the working state of the module, achieves the purpose of reducing the power consumption of the chip, and has simple control and easy realization. The embodiment of the invention can be widely applied to the technical field of low-power design of chips.
Description
Technical Field
The invention relates to the technical field of low-power-consumption chip design, in particular to a control method for reducing chip power consumption.
Background
With the rapid development of integrated circuit technology, the process size of transistors and the area of chips are continuously reduced, the integration level of chips and the performance of chips are continuously improved, the working frequency of chips is higher and higher, and the power consumption of chips is larger and larger. The increase of the power consumption of the chip has a great influence on the cruising ability of the electronic device, and currently, the low power consumption design has been taken as an important component of the chip design.
The prior art provides a low-power-consumption scheme for a special chip or scene, has weak expansibility, cannot be used for certain independent equipment, depends on external control, and cannot perform automatic processing through hardware. In addition, in the prior art, a plurality of working modes are divided by refining a working scene, and different numbers of functional units are started through the working modes, so that the design scheme in the prior art is high in complexity and occupies more circuit area.
Disclosure of Invention
In view of this, the embodiment of the present invention provides an automatic, easily controllable, and expandable control method for reducing chip power consumption.
The embodiment of the invention provides a control method for reducing chip power consumption, which comprises the following steps: detecting the equipment state through a clock control module, and determining a clock gating processing mode according to the equipment state; wherein the device state comprises at least one of: working state, idle state, delay state; controlling the clock control module to work according to the processing mode of clock gating; the clock control module comprises a state collection submodule, a command buffering submodule, a delay submodule and a clock gating submodule; the dynamic voltage regulation and frequency modulation control module is used for carrying out dynamic voltage regulation and dynamic frequency modulation control on the functional unit hardware module; the dynamic voltage and frequency regulation control module is composed of a decoding component, a state control component, a frequency regulation component and a voltage regulation component.
Optionally, the detecting, by the clock control module, the device state and determining, according to the device state, a processing mode of clock gating includes: receiving the state information and the configuration command of the functional unit through a state collection submodule; wherein the status information comprises at least one of: interrupt flag signal of functional unit, flag signal of algorithm completion, state of state machine; the configuration command includes: the host machine issues configuration information to the functional units; when the functional unit is detected to be in a busy state, the equipment state is marked as a working state, and the clock gating submodule starts clock enabling; when the functional unit is detected to be in an idle state, the equipment state is marked to be in a delay state; when the delay state ends, the clock is turned off through clock gating and the device state is marked as idle.
Optionally, the controlling the clock control module to operate according to the clock gating processing mode includes: loading a configuration command through a command buffer submodule, and counting the configuration command in a counter buffer; and when the configuration commands in the command buffering submodule are all completed and the count value in the delay counter is equal to the set threshold value, the clock of the execution unit is closed through the clock gating submodule.
Optionally, the loading the configuration command through the command buffer submodule, and counting the configuration command in a counter buffer includes: loading the configuration command, analyzing the type of the configuration command through a command recording unit, and recoding the configuration command in the command recording unit to form a first configuration command with a uniform format; and according to the type of the first configuration command, performing packet counting on the first configuration command in a counter cache.
Optionally, when the count value of the delay count submodule is equal to the set threshold and the configuration command in the command buffer submodule is completely completed, the clock gating submodule turns off the clock of the execution unit, including: when the execution of the configuration command of the execution unit is finished, clearing the configuration command in the counter cache; when the value of the command counter is cleared, a clock closing request is initiated; and closing the clock of the execution unit through the clock gating submodule.
Optionally, the dynamic voltage regulation and frequency modulation control module performs dynamic voltage regulation and dynamic frequency modulation control on the functional unit hardware module, and the method includes: setting the default state of the dynamic voltage-regulating frequency-modulating control module as an idle state; when the hardware of the functional unit needs to be regulated, the dynamic voltage and frequency regulation control module enters a voltage regulation state; when the hardware of the functional unit is judged to need frequency modulation and voltage regulation, the dynamic voltage and frequency modulation control module enters a frequency modulation state; and determining the work of the dynamic voltage and frequency regulation control module according to the state of the dynamic voltage and frequency regulation control module.
Optionally, determining the work of the dynamic voltage and frequency regulation control module according to the state of the dynamic voltage and frequency regulation control module includes: when the dynamic voltage and frequency regulation control module is in an idle state, the dynamic voltage and frequency regulation control module inquires a data table to judge whether voltage regulation and/or frequency regulation is needed; when the dynamic voltage-regulating frequency-modulating control module is in a voltage-regulating state, the dynamic voltage-regulating frequency-modulating control module initiates a voltage-regulating request to the system voltage-regulating module according to the requirement, when feedback of failed voltage regulation is received, the system enters an idle state, and when feedback of successful voltage regulation is received, the system enters a delay state; when the dynamic voltage-regulating frequency-modulating control module is in a delay state, the dynamic voltage-regulating frequency-modulating control module stabilizes voltage; and when the dynamic voltage and frequency regulation control module is in a frequency regulation state, the dynamic voltage and frequency regulation control module initiates a frequency regulation request to a system frequency regulation module.
An embodiment of the present invention further provides a control device for reducing chip power consumption, including: the first module is used for detecting the equipment state through the clock control module and determining the processing mode of clock gating according to the equipment state; the second module is used for controlling the clock control module to work according to the processing mode of the clock gating; and the third module is used for carrying out dynamic voltage regulation and dynamic frequency modulation control on the functional unit hardware module through the dynamic voltage regulation and frequency modulation control module.
An embodiment of the present invention further provides an electronic device, including a processor and a memory; the memory is used for storing programs; the processor executes the program to implement the method as described above.
Embodiments of the present invention also provide a computer-readable storage medium storing a program, which is executed by a processor to implement the method as described above.
The embodiment of the invention has the following beneficial effects: the embodiment of the invention detects the state of the equipment through the clock control module, determines the processing mode of clock gating according to the state of the equipment and controls the clock control module to work, carries out dynamic voltage regulation and dynamic frequency modulation control on the hardware module of the functional unit through the dynamic voltage regulation and frequency modulation control module, adopts a hardware automatic monitoring method to carry out clock and voltage control, has weak software dependence and is easy to operate and control, and the application scene dependence of the embodiment of the invention is weak and convenient to expand. In addition, the embodiment of the invention can dynamically control the clock and the voltage according to the working state of the module, achieves the purpose of reducing the power consumption of the chip, and has simple control and easy realization.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart of method steps provided by an embodiment of the present invention;
FIG. 2 is a block diagram of a module design provided by an embodiment of the present invention;
FIG. 3 is a flow diagram of a clock gating process provided by an embodiment of the invention;
FIG. 4 is a diagram of a clock control module according to an embodiment of the present invention;
FIG. 5 is a timing diagram for clock control provided by an embodiment of the present invention;
FIG. 6 is a diagram of a command recording unit according to an embodiment of the present invention;
FIG. 7 is a block diagram of a command flush unit provided by an embodiment of the present invention;
fig. 8 is a diagram of a dynamic voltage and frequency adjustment control module according to an embodiment of the present invention;
FIG. 9 is a flowchart of the operation of the dynamic voltage regulation and frequency modulation control module according to the embodiment of the present invention;
fig. 10 is a diagram of application of low power consumption control according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Aiming at the problems that the prior art depends on external control, cannot perform automatic processing through hardware and is high in complexity, the embodiment of the invention provides a control method for reducing chip power consumption, and referring to fig. 1, fig. 1 is a flow chart of method steps provided by the embodiment of the invention, and the method comprises the following steps: detecting the equipment state through a clock control module, and determining a clock gating processing mode according to the equipment state; wherein the device state comprises at least one of: working state, idle state, delay state. Controlling a clock control module to work according to a clock gating processing mode; the clock control module comprises a state collection submodule, a command buffering submodule, a delay submodule and a clock gating submodule; the dynamic voltage regulation and frequency modulation control module is used for carrying out dynamic voltage regulation and dynamic frequency modulation control on the functional unit hardware module; the dynamic voltage and frequency regulation control module is composed of a decoding assembly, a state control assembly, a frequency regulation assembly and a voltage regulation assembly.
Specifically, referring to fig. 2, fig. 2 is a block design structure diagram provided by the present invention, and the low power consumption control module (power _ ctrl) of the embodiment of the present invention includes a clock control module (clk _ ctrl), a dynamic voltage regulation and frequency modulation control module (dvfs _ ctrl), a configuration register, and a clock generation module; the configuration register is used for storing configuration commands and the like, and the clock generation module is used for generating clocks. The clock control module interacts with a functional unit (function module) through a general purpose I/O interface (gpio interface), wherein the functional unit may be, for example, an encryption engine, a DSP (digital signal processing), etc. The clock control module is used for completing clock gating control of the functional units, and the dynamic voltage-regulating frequency-modulating control module is used for completing dynamic voltage-regulating and dynamic frequency-modulating control. The embodiment of the invention comprises the following steps S100-S300:
and S100, detecting the equipment state through a clock control module, and determining a clock gating processing mode according to the equipment state.
Specifically, referring to fig. 3, fig. 3 is a flow chart of clock gating processing provided in the embodiment of the present invention, where a device state may include at least one of a working state, an idle state, and a delay state, and in this embodiment, referring to fig. 4, fig. 4 is a composition diagram of a clock control module provided in the embodiment of the present invention, where the clock control module includes a state collection submodule, a command buffer submodule, a delay submodule, and a clock gating submodule. Referring to fig. 3, step S100 includes the following steps S110 to S140:
s110, receiving the state information and the configuration command of the functional unit through a state collection submodule; wherein the status information includes at least one of: interrupt flag signal of functional unit, flag signal of algorithm completion, state of state machine; the configuration command includes: the host computer issues the configuration information to the functional units. According to the state information, the clock control module can detect and judge the current state of the functional unit.
And S120, when the busy state of the functional unit is detected, marking the equipment state as a working state, and starting clock enabling through the clock gating submodule.
Specifically, the clock gating sub-module is used to turn on the clock and turn off the clock. Referring to fig. 5, fig. 5 is a timing chart of clock control according to an embodiment of the present invention, when a functional unit receives a configuration command issued by a host, an internal state of the functional unit is a busy state, and when a clock control module detects the busy state of the functional unit, a device state is marked as a working state, and a clock gating sub-module starts a clock enable and keeps the clock on. The working state of the functional unit comprises a state set of pending interrupt, state machine state, command buffer clock request and the like.
And S130, when the functional unit is detected to be in the idle state, marking the equipment state as a delay state.
Specifically, in order to prevent the clock from being turned off during operation, when the functional unit is monitored to be in an idle state, the device state is marked as a delay state, the delay submodule is composed of a delay counter and is responsible for delay counting operation in the delay state, and the delay count value can be configured by the host.
And S140, when the delay state is finished, closing the clock through clock gating, and marking the equipment state as an idle state.
And S200, controlling the clock control module to work according to the clock gating processing mode.
Specifically, according to the processing mode of clock gating, a command buffer submodule in the clock control module works, referring to fig. 6 and 7, fig. 6 is a structure diagram of a command record provided in an embodiment of the present invention, fig. 7 is a structure diagram of a command clearing structure provided in an embodiment of the present invention, and the command buffer submodule includes a command record unit and a command clearing unit. The step S200 includes the following steps S210 to S220:
s210, loading the configuration command through the command buffer submodule, and counting the configuration command in the counter buffer.
Specifically, step S210 includes the following steps S211 to S212:
s211, loading the configuration command, analyzing the type of the configuration command through the command recording unit, and recoding the configuration command in the command recording unit to form a first configuration command with a uniform format.
Specifically, referring to fig. 6, fig. 6 is a structural diagram of a command recording unit, where a command buffer module loads a configuration command, performs a command parsing operation in the command recording unit, parses the type of the configuration command, and re-encodes the configuration command, where the command re-encoding unifies the format of the command to form a first configuration command with a unified format. In order to improve design versatility, the command parsing operation needs to adapt to commands of each functional unit in the SoC chip.
S212, according to the type of the first configuration command, grouping and counting the first configuration command in the counter buffer.
In particular, the counter cache performs a packet counting operation according to the type of the first configuration command. The number of packets buffered by the counter can be adjusted according to the number of command types of the functional unit.
In addition, the buffer value of the counter of each configuration command is monitored in real time through clock requirement collection operation.
The command buffering submodule can reduce the required storage capacity through command analysis, command recoding and command counting operation, and the purpose of low area consumption is achieved.
And S220, when the configuration commands in the command buffering submodule are all completed and the count value in the delay counter is equal to the set threshold value, closing the clock of the execution unit through the clock gating submodule.
In some embodiments, the host intermittently issues the configuration command, and the functional unit only performs a short operation, and after the short operation, the functional unit operates again after a short interval. The time interval from the command to the busy state of the functional unit is several clock cycles, and the clock can be closed when the count value of the delay counter is equal to the set threshold value and the command of the command buffer unit is completely finished, so that the functional unit can be prevented from being abnormal due to the clock being closed during working.
Specifically, step S220 includes the following steps S221 to S223:
s221, when the execution of the configuration command of the execution unit is completed, clearing the configuration command in the counter cache.
Specifically, the command clearing is completed by a command clearing unit of the command buffering module, referring to fig. 7, fig. 7 is a structural diagram of the command clearing unit provided in the embodiment of the present invention, and each algorithm unit of the functional unit sends a flag indicating that the command is completed to the counter cache, so that the counter cache performs a command clearing operation.
S222, when the numerical value of the command counter is cleared, a clock closing request is initiated.
Specifically, the clock request module monitors the counter value of each command in real time, and if the clearing is completed, a clock closing request can be initiated, otherwise, the clock continues to be in a working state.
And S223, when the clock closing request is received, closing the clock of the execution unit through the clock gating submodule.
Specifically, when a clock closing request is received, the clock gating submodule enters a delay state, and after the delay state is ended, the clock gating submodule closes the clock of the execution unit.
The embodiment of the invention designs a hardware automatic clock gating mechanism by the command buffering and the delay of the hardware automation to coordinate the command and the clock, controls the clock, improves the stability of the clock gating function, prevents the clock from being frequently closed, can reduce the software behavior and reduce the consumption of a clock tree.
And S300, performing dynamic voltage regulation and dynamic frequency modulation control on the hardware module of the functional unit through the dynamic voltage regulation and frequency modulation control module.
Referring to fig. 8, fig. 8 is a diagram of a dynamic voltage and frequency adjustment control module according to an embodiment of the present invention, where the dynamic voltage and frequency adjustment control module (dvfs _ ctrl) according to an embodiment of the present invention includes a decoding component, a state control component, a frequency adjustment component, and a voltage adjustment component. The functional unit passes through gpio mouth and dynamic pressure regulating frequency modulation control module and interacts, includes: the function unit sends a frequency modulation and voltage regulation request (gpio _ req) and voltage data (gpio _ data) to the dynamic frequency modulation and voltage regulation control module, and the dynamic frequency modulation and voltage regulation control module sends a feedback signal (gpio _ ack) to the function unit, wherein the voltage data includes frequency modulation information and voltage regulation information.
Specifically, the moving station voltage-regulating frequency-modulating control module in the embodiment of the present invention is configured with a VF table, and the VF table records a clock source, frequency-dividing control, and voltage information corresponding to each gear, and the VF table in the embodiment of the present invention refers to table 1, where table 1 is a VF table provided in the embodiment of the present invention:
TABLE 1
| Bit index | Description of the invention |
| 31：24 | Gear position |
| 23：16 | Clock source |
| 15：8 | Clock frequency division |
| 7：0 | Voltage of |
The VF table of the embodiment of the present invention has 32 bits, as shown in table 1, it can be understood that when looking up the table, the 0 th bit to the 7 th bit represent the voltage. And inquiring a VF table according to the voltage data gear sent by the functional unit, judging the switched clock and voltage, and further realizing the switching between the frequency and the voltage. The VF table may be specified according to the operating scenario of the functional unit. It should be noted that table 1 is only an example, and does not limit the specific data of the VF table of the present invention.
Specifically, step S300 includes the following steps S310 to S340:
and S310, setting the default state of the dynamic voltage-regulating frequency-modulating control module as an idle state.
And S320, when the hardware of the functional unit needs to be regulated, the dynamic voltage and frequency regulation control module enters a voltage regulation state.
S330, when the hardware of the functional unit is judged to need frequency modulation and voltage regulation, the dynamic voltage and frequency modulation control module enters a frequency modulation state.
And S340, determining the work of the dynamic voltage and frequency regulation control module according to the state of the dynamic voltage and frequency regulation control module.
Specifically, the dynamic voltage-regulating frequency-modulating module in the embodiment of the present invention communicates with the system voltage-regulating module and the system frequency-modulating module in a one-time handshake manner, and optionally, in other embodiments, other manners may also be used for communication. The system Voltage regulating module may be a PMU (Power Management Unit) or a VC (Voltage ctrl). Referring to fig. 9, fig. 9 is a flowchart of the operation of the dynamic voltage-regulating and frequency-modulating control module according to the embodiment of the present invention, and step S340 includes the following steps S341 to S344:
and S341, when the dynamic voltage and frequency regulation control module is in an idle state, the dynamic voltage and frequency regulation control module inquires a data table to judge whether voltage regulation and/or frequency regulation is needed.
And S342, when the dynamic voltage and frequency regulation control module is in a voltage regulation state, the dynamic voltage and frequency regulation control module initiates a voltage regulation request to the system voltage regulation module according to the requirement, when receiving the feedback of failed voltage regulation, the dynamic voltage and frequency regulation control module enters an idle state, and when receiving the feedback of successful voltage regulation, the dynamic voltage and frequency regulation control module enters a delay state.
Specifically, in the voltage regulation state, the dynamic voltage regulation and frequency modulation control module sends a voltage boost request to the system voltage regulation module, if the feedback voltage regulation fails, the dynamic voltage regulation and frequency modulation control module enters an idle state, and if the voltage regulation succeeds, the dynamic voltage regulation and frequency modulation control module enters a delay state.
And S343, when the dynamic voltage and frequency regulation control module is in a delay state, the dynamic voltage and frequency regulation control module stabilizes voltage.
And S344, when the dynamic voltage and frequency regulation control module is in a frequency regulation state, the dynamic voltage and frequency regulation control module initiates a frequency regulation request to the system frequency regulation module.
Specifically, in the frequency modulation state, the frequency increasing or reducing operation can be completed, and if the voltage is increased and the frequency is increased, the voltage is increased and then the frequency is increased; if the frequency is required to be increased without regulating the voltage, the increasing operation is directly carried out; if the frequency reduction and voltage reduction are needed, the frequency reduction is carried out first and then the voltage reduction is carried out, and the switching efficiency is ensured.
An embodiment of the present invention further provides a control device for reducing chip power consumption, including: the first module is used for detecting the equipment state through the clock control module and determining the processing mode of clock gating according to the equipment state; the second module is used for controlling the clock control module to work according to the processing mode of clock gating; and the third module is used for carrying out dynamic voltage regulation and dynamic frequency modulation control on the functional unit hardware module through the dynamic voltage regulation and frequency modulation control module.
An embodiment of the present invention further provides an electronic device, including a processor and a memory; the memory is used for storing programs; the processor executes the program to implement the method as described above.
Embodiments of the present invention also provide a computer-readable storage medium storing a program for execution by a processor to implement the method as described above.
The embodiment of the invention has the following beneficial effects:
1. the embodiment of the invention adopts the modes of hardware automatic monitoring and predefined threshold value to control the clock and the voltage, can dynamically control the clock and the voltage of the module according to the working scene, achieves the aim of reducing the power consumption of the chip, has weaker software dependence and is easy to operate and control;
2. the command buffering submodule and the delay submodule are configured to coordinate the command and the clock, so that the stability of the clock gating function can be improved, and the clock is prevented from being frequently closed to cause abnormity.
3. The embodiment of the invention can be used for conveniently designing the internal module of the SoC chip, has weak dependency of an application scene and is easy to expand.
The following is an application scenario provided by the embodiment of the present invention:
referring to fig. 10, fig. 10 is a low power consumption control application diagram provided in an embodiment of the present invention, where the embodiment of the present invention may apply a functional module in an SoC chip, detect a device state through a clock control module, and determine a processing mode of clock gating according to the device state; controlling the clock control module to work according to the processing mode of the clock gating; and the dynamic voltage regulation and frequency modulation control module is used for carrying out dynamic voltage regulation and dynamic frequency modulation control on the hardware module of the functional unit. The clocks and/or voltages of the individual functional units can be controlled with fine granularity.
In alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flow charts of the present invention are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are performed independently.
Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise indicated to the contrary, one or more of the described functions and/or features may be integrated in a single physical device and/or software module, or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary for an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be understood within the ordinary skill of an engineer given the nature, function, and interrelationships of the modules. Accordingly, those skilled in the art can, using ordinary skill, practice the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative of and not intended to limit the scope of the invention, which is defined by the appended claims and their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A control method for reducing chip power consumption is characterized by comprising the following steps:
detecting the equipment state through a clock control module, and determining a clock gating processing mode according to the equipment state; wherein the device state comprises at least one of: working state, idle state, delay state;
controlling the clock control module to work according to the processing mode of the clock gating; the clock control module comprises a state collection submodule, a command buffering submodule, a delay submodule and a clock gating submodule;
the dynamic voltage regulation and frequency modulation control module is used for carrying out dynamic voltage regulation and dynamic frequency modulation control on the functional unit hardware module; the dynamic voltage and frequency regulation control module is composed of a decoding assembly, a state control assembly, a frequency regulation assembly and a voltage regulation assembly.
2. The control method for reducing chip power consumption according to claim 1, wherein the detecting the device state by the clock control module and determining the clock gating processing mode according to the device state includes:
receiving the state information and the configuration command of the functional unit through the state collection submodule; wherein the status information comprises at least one of: interrupt flag signals of the functional units, flag signals of algorithm completion and states of the state machine; the configuration command includes: the host computer issues the configuration information of the functional unit;
when the functional unit is detected to be in a busy state, the equipment state is marked as a working state, and the clock gating submodule starts clock enabling;
when the functional unit is detected to be in an idle state, the equipment state is marked to be in a delay state;
when the delay state ends, the clock is turned off through clock gating and the device state is marked as idle.
3. The control method for reducing chip power consumption according to claim 1, wherein the controlling the clock control module to operate according to the clock gating processing mode comprises:
loading a configuration command through a command buffer submodule, and counting the configuration command in a counter buffer;
when the configuration commands in the command buffering submodule are all completed and the count value in the delay counter is equal to the set threshold value, the clock of the execution unit is closed through the clock gating submodule.
4. The control method for reducing chip power consumption according to claim 3, wherein the loading the configuration command through the command buffering sub-module and counting the configuration command in the counter buffer includes:
loading the configuration command, analyzing the type of the configuration command through a command recording unit, and recoding the configuration command in the command recording unit to form a first configuration command with a uniform format;
and according to the type of the first configuration command, performing packet counting on the first configuration command in a counter cache.
5. The control method for reducing the power consumption of the chip according to claim 3, wherein when the count value of the delay count submodule is equal to the set threshold value and the configuration commands in the command buffer submodule are all completed, the clock of the execution unit is turned off by the clock gating submodule, including:
when the execution of the configuration command of the execution unit is finished, clearing the configuration command in the counter cache;
when the numerical value of the command counter is cleared, a clock closing request is initiated;
and closing the clock of the execution unit through the clock gating submodule.
6. The control method for reducing chip power consumption according to claim 1, wherein the performing dynamic voltage regulation and dynamic frequency modulation control on the functional unit hardware module by the dynamic voltage regulation and frequency modulation control module comprises:
setting the default state of the dynamic voltage-regulating frequency-modulating control module as an idle state;
when the hardware of the functional unit needs to be regulated, the dynamic voltage and frequency regulation control module enters a voltage regulation state;
when the hardware of the functional unit is judged to need frequency modulation and voltage regulation, the dynamic voltage and frequency modulation control module enters a frequency modulation state;
and determining the work of the dynamic voltage and frequency regulation control module according to the state of the dynamic voltage and frequency regulation control module.
7. The control method for reducing chip power consumption according to claim 6, wherein the determining the operation of the dynamic voltage and frequency regulation control module according to the state of the dynamic voltage and frequency regulation control module comprises:
when the dynamic voltage and frequency regulation control module is in an idle state, the dynamic voltage and frequency regulation control module inquires a data table to judge whether voltage regulation and/or frequency regulation is needed;
when the dynamic voltage-regulating frequency-modulating control module is in a voltage-regulating state, the dynamic voltage-regulating frequency-modulating control module initiates a voltage-regulating request to the system voltage-regulating module according to the requirement, when receiving the feedback of the failed voltage regulation, the dynamic voltage-regulating frequency-modulating control module enters an idle state, and when receiving the feedback of the successful voltage regulation, the dynamic voltage-regulating frequency-modulating control module enters a delay state;
when the dynamic voltage-regulating frequency-modulating control module is in a delay state, the dynamic voltage-regulating frequency-modulating control module stabilizes voltage;
and when the dynamic voltage and frequency regulation control module is in a frequency regulation state, the dynamic voltage and frequency regulation control module initiates a frequency regulation request to a system frequency regulation module.
8. A control device that reduces power consumption of a chip, comprising:
the first module is used for detecting the equipment state through the clock control module and determining the processing mode of clock gating according to the equipment state;
the second module is used for controlling the clock control module to work according to the processing mode of the clock gating;
and the third module is used for carrying out dynamic voltage regulation and dynamic frequency modulation control on the functional unit hardware module through the dynamic voltage regulation and frequency modulation control module.
9. An electronic device comprising a processor and a memory;
the memory is used for storing programs;
the processor executing the program realizes the method of any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that the storage medium stores a program, which is executed by a processor to implement the method according to any one of claims 1 to 7.
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| CN117608388A (en) * | 2024-01-15 | 2024-02-27 | 珠海全志科技股份有限公司 | Power consumption control method and device applied to SoC system and SoC system |
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