CN115841840A - Reference unit module of nonvolatile memory and reference unit repairing method - Google Patents
Reference unit module of nonvolatile memory and reference unit repairing method Download PDFInfo
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Abstract
The application discloses a reference cell module of a nonvolatile memory and a reference cell repairing method. The reference unit repairing method comprises the following steps: performing first reference unit repair in a wafer test stage; and performing second reference cell repair in a packaging test stage, wherein the reference cell module of the non-volatile memory comprises a first sub-array and a second sub-array, and the reference cell repair comprises forming address mapping between first reference cells of the first sub-array with defects and second reference cells of the second sub-array with threshold voltages identical and without defects. The first reference unit with the defect is repaired in the wafer test stage and the packaging test stage, so that the yield of chips is improved.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a reference unit module of a nonvolatile memory and a reference unit repairing method.
Background
The nonvolatile memory is a nonvolatile solid-state storage technology which can still store data after power failure, has the advantages of low power consumption, high read-write speed and the like, and is widely applied to the fields of mobile terminal equipment, data centers and the like. Applications in different fields have different performance requirements for non-volatile memories.
When a memory cell of a nonvolatile memory chip is read, the current magnitude of a reference cell and the current magnitude of the memory cell are compared to obtain the data stored in the memory cell. For example, when the read current of the memory cell is larger than the current of the reference cell, the stored data is 1, and when the read current of the memory cell is smaller than the current of the reference cell, the stored data is 0.
Generally, in a production process of a chip of a nonvolatile memory, in order to ensure the reliability of the operation of the chip, a defective chip needs to be rejected in a test process, for example, a chip with a defective reference unit due to a production process or a stress test. As shown in fig. 1, a wafer is shown, all the non-volatile memory dies on the wafer are subjected to a series of wafer tests, the die 1 passing the tests is packaged into a non-volatile memory chip and enters a package testing step, the qualified chip is likely to be finally applied to the field of mobile terminals or data centers in the package testing step, and the die 2 not passing the tests (for example, the reference unit is damaged) or the packaged chips are rejected. Wafer yield is the ratio of the number of nonvolatile memory dies on the wafer that pass all tests to the total number of nonvolatile memory dies on the wafer. The wafer with low yield not only increases the manufacturing cost, but also wastes die resources and pollutes the environment.
Disclosure of Invention
In view of the foregoing problems, an object of the present invention is to provide a reference cell module of a non-volatile memory and a reference cell repairing method, wherein a damaged reference cell is repaired in a wafer testing step and a package testing step, thereby improving a chip yield.
According to an aspect of the present invention, there is provided a reference cell repair method of a nonvolatile memory, including: performing first reference unit repair in a wafer test stage; and performing second reference unit repair in a packaging test stage, wherein the reference unit module of the non-volatile memory comprises a first sub-array and a second sub-array, and the reference unit repair comprises forming address mapping between first reference units of the first sub-array with defects and second reference units of the second sub-array with the same threshold voltage and without defects.
Optionally, the first sub-array includes a plurality of the first reference cells, the second sub-array includes a plurality of the second reference cells, and the number of the first reference cells is the same as the number of the second reference cells.
Optionally, the first reference cell repair comprises: adjusting a threshold voltage of the first reference cell to a design value; carrying out aging test on the wafer; judging whether the first reference unit has defects according to whether the threshold voltage of the first reference unit changes; adjusting a threshold voltage of the second reference cell to the design value when the first reference cell is defective; and forming an address map with the defective first reference cell in the second reference cell and recording mapping information.
Optionally, the burn-in test comprises placing the wafer in a 250 ℃ environment for 24 hours.
Optionally, the second reference cell repairing includes: judging whether the first reference unit has defects according to whether the threshold voltage of the first reference unit changes; adjusting a threshold voltage of the second reference cell to the design value when the first reference cell is defective; and forming an address map with the defective first reference cell in the second reference cell and recording mapping information.
Optionally, the first reference cell repair comprises: adjusting a threshold voltage of the first reference cell to a design value; adjusting a threshold voltage of the second reference cell to the design value; carrying out aging test on the wafer; judging whether the first reference unit has defects according to whether the threshold voltage of the first reference unit changes; judging whether the second reference unit has defects according to whether the threshold voltage of the second reference unit changes when the first reference unit has defects; and forming an address map between the second reference unit and the first reference unit having a defect and recording mapping information when the second reference unit has no defect.
Optionally, the burn-in test comprises placing the wafer in a 250 ℃ environment for 24 hours.
Optionally, the second reference cell repairing includes: judging whether the first reference unit repair exists according to the mapping information; when the first reference unit is not repaired, judging whether the first reference unit has defects according to whether the threshold voltage of the first reference unit changes or not; judging whether the second reference unit has defects according to whether the threshold voltage of the second reference unit changes when the first reference unit has defects; and forming an address map between the second reference cell and the first reference cell having a defect and recording mapping information when the second reference cell has no defect.
Optionally, there is a second reference cell for each first reference cell having the same threshold voltage.
According to still another aspect of the present invention, there is provided a reference cell module of a nonvolatile memory, including: a first sub-array comprising a plurality of first reference cells; a second sub-array comprising a plurality of second reference cells; the reference current generation module selects the first reference unit to generate reference current according to reading conditions, and selects the corresponding second reference unit to generate the reference current when the first reference unit has defects.
Optionally, the reference unit further comprises: the repair information storage module is used for storing the address mapping information of the first reference unit and the second reference unit; and the repair information reading module is connected with the repair information storage module and provides the address mapping information to the reference current generation module.
According to the reference unit repairing method provided by the embodiment of the invention, whether the reference unit is damaged or not is judged by detecting the threshold voltage set by the first reference unit in the wafer testing link and the packaging testing link, and the address mapping is formed between the first reference unit with the defect and the second reference unit with the threshold voltage same and without the defect according to the detection result, so that the damage of the reference unit caused by the production or testing process is reduced, and the yield of chips is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic view of a wafer;
FIG. 2 shows a schematic block diagram of a prior art non-volatile memory system;
FIG. 3 shows a schematic block diagram of a non-volatile memory system according to an embodiment of the present invention;
FIG. 4 shows a flow diagram of a reference cell repair method according to an embodiment of the invention;
FIG. 5 shows a detailed flowchart of a reference cell repair method according to a first embodiment of the present invention;
fig. 6 shows a detailed flowchart of a reference cell repair method according to a second embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to". In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 2 shows a schematic block diagram of a non-volatile memory system 100 in the prior art.
The non-volatile memory system 100 includes a memory chip 110 of a non-volatile memory and a memory controller 120. Memory controller 120 transfers instructions and data between the host and memory chip 110.
The memory chip 110 includes a memory cell array 111 and a reference cell array 112. The memory cell array 111 includes, for example, a plurality of memory cells of a NAND flash memory structure or a NOR flash memory structure. The reference cell array 112 includes a plurality of reference cells of a NOR flash memory structure, for example. In contrast to NAND flash memory architectures, the transistors in NOR flash memory architectures are independently addressable. Thus, in the reference cell array 112, a single reference cell can be selected, and the threshold voltage of the single reference cell can be set, and the reference current generated by the single reference cell can be obtained.
The memory chip 110 further includes a reference current generating module 113 and a reading circuit 114. The read circuit 114 includes a plurality of sense modules 114-1 to 114-m. The reference current generation module 113 outputs a selection signal to the reference cell array 112 according to data reading (e.g., pre-program verify, erase verify, weak program verify) of different reading conditions, selects a reference cell with a corresponding threshold voltage, and applies a voltage to generate a corresponding reference current Iref. The sensing module compares the sensing current Isen of the memory cells in the memory cell array 111 with the reference current Iref. The reading circuit 114 determines the charge state in the memory cell according to the comparison result of the sensing current Isen and the reference current Iref, thereby reading the data stored in the memory cell under the corresponding condition.
The memory chip 110 further includes a control module 117, a column decoder 115, and a row decoder 116. The control module 117 provides an address interface between the address of the host or memory controller and the hardware address in the memory cell array 111. The control module 117 is connected to a column decoder 115 and a row decoder 116, the column decoder 115 addressing the memory cells via bit lines and the row decoder 116 addressing the memory cells via word lines. The control module 117 also provides the word line voltage and the bit line voltage in data operations and is coupled to the read circuit 114 to obtain the data read from the memory cells.
FIG. 3 shows a schematic block diagram of a non-volatile memory system 200 according to an embodiment of the present invention.
The non-volatile memory system 200 includes a memory chip 210 of a non-volatile memory and a memory controller 220. The memory controller 220 transfers instructions and data between the host and the memory chip 210.
The memory chip 210 includes a memory cell array 211, a reference cell block 20, a reference current generating block 213, and a reading circuit 214. The memory cell array 211 includes, for example, a plurality of memory cells of a NAND flash memory structure or a NOR flash memory structure.
The reference cell module 20 includes a first sub-array 21 and a second sub-array 22. The first sub-array 21 for example comprises a plurality of first reference cells of a NOR flash memory architecture and the second sub-array 22 for example comprises a plurality of second reference cells of a NOR flash memory architecture, the transistors in which are independently addressable compared to a NAND flash memory architecture. Thus, a single first reference cell or a corresponding second reference cell may be selected, and a single threshold voltage set, and a reference current generated by the single first reference cell or the second reference cell may be obtained. Further, since there may exist a plurality of first reference cells having different threshold voltages according to a read condition, the same number of second reference cells as the first reference cells are required to ensure that repair of all the defective first reference cells can be achieved.
The read circuit 214 includes a plurality of sense modules 214-1 to 214-m. The reference current generation module 213 outputs a selection signal to the reference cell module 20 according to data reading under different reading conditions (e.g., pre-program verify, erase verify, weak program verify), selects the first reference cell with a corresponding threshold value, and applies a voltage to generate a corresponding reference current Iref. And under the condition that the first reference unit has defects, selecting a corresponding second reference unit to generate the reference current Iref. The sense module compares the sense current Isen of the memory cells in the memory cell array 211 with the reference current Iref. The read circuit 214 determines the charge state in the memory cell according to the comparison result between the sensing current Isen and the reference current Iref, thereby reading the data stored in the memory cell under the corresponding condition.
The memory chip 210 further includes a control module 217, a column decoder 215, and a row decoder 216, which are substantially the same in structure and function as the control module 117, the column decoder 115, and the row decoder 116 of the memory chip 110 in the prior art, and detailed descriptions thereof are omitted here.
Further, the reference cell module 20 further includes a repair information storage module 23 and a repair information reading module 24. The repair information storage module 23 is configured to store address mapping information, and when detecting that any first reference unit in the first sub-array 21 has a defect in a wafer test stage or a package test stage, the repair information storage module forms address mapping with a corresponding second reference unit in the second sub-array 22 that has no defect, and stores the address mapping information in the repair information storage module 23, where threshold voltages of the first reference unit and the corresponding second reference unit are the same;
the repair information reading module 24 reads the address mapping information in the repair information storage module 23 when the chip is powered on, and outputs the address mapping information to the reference current generating module 213 after analyzing the address mapping information;
the reference current generating module receives the address mapping information analyzed by the repair information reading module 24, and selects a first reference cell in the first sub-array 21 or a second reference cell in the second sub-array 22 to generate a reference current. Specifically, there is a first reference cell corresponding to the threshold voltage according to the selection signal outputted by the reference current generation module 213, and if there is no address mapping information in the selected first reference cell, the first reference cell is provided to the reference current generation module 213; if the first reference cell has address mapping information, the corresponding second reference cell is selected and provided to the reference current generation module 213.
FIG. 4 shows a flow chart of a reference cell repair method according to the present invention, including
S1: manufacturing a wafer;
s2: repairing the reference unit for the first time in a wafer test stage;
in this step, the die is tested, whether the first reference cell in the first subarray 21 has a defect is determined, if the first reference cell has a defect, an address map is formed between the defective first reference cell and the second reference cell having the same threshold voltage and no defect, and address mapping information is recorded.
S2: packaging a chip;
in this step, the bare chip without the defect of the first reference unit and the bare chip after the first reference unit repair is completed are packaged into a memory chip.
S3: and repairing the reference unit for the second time in the packaging test stage.
In the step, the packaged memory chip is tested, whether the first reference unit is damaged or not in the packaging process is judged, if the first reference unit has a defect, address mapping is formed between the defective first reference unit and a second reference unit which has the same threshold voltage and does not have the defect, and address mapping information is recorded.
Fig. 5 and 6 are detailed flowcharts of different embodiments of a reference cell repairing method according to the present invention, and a first reference cell repairing method will be described in detail with reference to fig. 6 and 5.
Fig. 5 shows a detailed flowchart of a reference cell repair method according to a first embodiment of the present invention. In this embodiment, steps S101 to S105 correspond to step S2 shown in fig. 5, i.e., repairing the reference cell for the first time in the wafer testing stage; steps S107 to S109 correspond to step S4 shown in fig. 5, i.e., repairing the reference cell for the second time in the package test stage. The method comprises the following specific steps:
s101: adjusting the first reference cell to a design value;
in this step, the die is designed, specifically to adjust a design value of the first reference cell in the first subarray 21, for example, to adjust a threshold voltage of the first reference cell in this embodiment. Since the first reference cells with different threshold voltages need to be selected to apply voltages to generate corresponding reference currents under different reading conditions (e.g., pre-programmed verify, program verify, erase verify, weak program verify), several sets of first reference cells with different threshold voltages may need to be designed at the same time in the first sub-array 21.
S102: and (3) aging test:
in this step, the designed wafer and the die are placed in a high temperature environment for a certain time, for example, the die is placed in a high temperature environment at 250 ℃ for 24 hours, so as to accelerate the die aging.
S103: measuring whether the first reference unit design value changes;
in this step, the aged die is tested, whether the threshold voltage of each first reference unit changes is measured, if no first reference unit changes, step S106 and subsequent steps are executed, and if at least one first reference unit has a changed threshold voltage, step S104 and step S105 are executed before step S106.
S104: adjusting the second reference cell to a design value;
in this step, a second reference cell is selected in the second sub-array 22 and its threshold voltage is adjusted to the design value of the defective first reference cell. Further, when there are a plurality of defective first reference cells, a second reference cell having the same threshold voltage as the first reference cell is set for each defective first reference cell.
S105: mapping an address;
in this step, an address map is formed between the defective first reference cell and the second reference cell having the same threshold voltage and no defect, and the map information is stored in the repair information storage unit 23. The number of the second reference cells and the number of the first reference cells with defects are consistent, so that the first reference cells with defects are repaired.
S106: packaging a chip;
in the step, the bare chip with unchanged threshold voltage of each first reference unit and the bare chip with repaired first reference unit are packaged to obtain a packaging piece.
S107: measuring whether the first reference unit design value changes;
in the step, testing the packaging chip, measuring whether the threshold voltage of each first reference unit changes, and if the threshold voltage of each first reference unit does not change, ending the test and enabling the packaging chip to be qualified; if there is at least one first reference cell threshold voltage variation, step S108 and step S109 are executed.
S108: adjusting the second reference cell to a design value;
in this step, a second reference cell is selected in the second sub-array 22 and its threshold voltage is adjusted to the design value of the defective first reference cell. Further, when there are a plurality of defective first reference cells, a second reference cell having the same threshold voltage as the first reference cell is set for each defective first reference cell.
S109: address mapping
In this step, an address map is formed between the defective first reference cell and the second reference cell having the same threshold voltage and no defect, and the map information is stored in the repair information storage unit 23. The number of the second reference cells and the number of the first reference cells with defects are consistent, so that the first reference cells with defects are repaired.
The embodiment shown in FIG. 5 is implemented by replacing the second reference cell when the first reference cell is found to be unsatisfactory. Therefore, the second reference unit does not need to be fixed to the specific first reference unit during design, and the utilization rate of the second reference unit is improved; meanwhile, the second reference unit is arranged when replacement is needed, so that the test time is reduced.
Fig. 6 shows a detailed flowchart of a first reference cell repair method according to a second embodiment of the present invention. In this embodiment, steps S201 to S206 correspond to step S2 shown in fig. 5, i.e. repairing the reference cell for the first time in the wafer test stage; steps S208 to S211 correspond to step S4 shown in fig. 5, i.e., repairing the reference cell for the second time in the packaging test stage. The method comprises the following specific steps:
s201: adjusting the first reference cell to a design value;
in this step, the die is designed, specifically, the design value of the first reference cell in the first subarray 21 is designed, and in this embodiment, the design value takes the threshold voltage as an example. Since the first reference cells with different threshold voltages need to be selected to apply voltages to generate corresponding reference currents under different reading conditions (e.g., pre-program verify, erase verify, weak program verify), several sets of first reference cells with different threshold voltages may need to be designed simultaneously in the first sub-array 21.
S202: adjusting the second reference cell to a design value;
in this step, the die is designed, specifically, the design value of the second reference cells in the second subarray 22 is designed, and in this embodiment, the design value is exemplified by the threshold voltage. Such that each threshold voltage has a corresponding first reference cell in the first subarray 21 and second reference cell in the second subarray 22.
S203: and (3) aging test:
in this step, the designed wafer and the die are placed in a high temperature environment for a certain time, for example, the die is placed in a high temperature environment at 250 ℃ for 24 hours, so as to accelerate the die aging.
S204: measuring whether the first reference unit design value changes;
in this step, the aged die is tested, whether the threshold voltage of each first reference cell has changed or not is measured, if none of the first reference cells has changed, step S207 and subsequent steps are performed, and if at least one first reference cell has changed in threshold voltage, step S205 and step S206 are performed before step S207.
S205: measuring whether the second reference unit design value changes;
in the step, the aged bare chip is tested, whether the threshold voltage of the second reference unit corresponding to the defective first reference unit changes or not is measured, if the second reference unit corresponding to the defective first reference unit does not change, the step S206 and the subsequent steps are executed, and if the threshold voltage of at least one second reference unit changes, the test is ended and the packaging chip is unqualified.
S206: mapping an address;
in this step, an address map is formed between the defective first reference cell and the second reference cell having the same threshold voltage and no defect, and the map information is stored in the repair information storage unit 23.
S207: packaging a chip;
in this step, a die with unchanged design value of each first reference unit and a die with completed replacement of the first reference unit are packaged to obtain a package piece.
S208: whether or not a replacement has occurred:
in this step, it is determined whether the replacement of the first reference unit occurs in the die testing stage according to the address mapping information in the repair information storage unit 23, and if the replacement occurs, step S210 and subsequent steps are executed; if no replacement occurs, step S209 is performed before step S210.
S209: it is measured whether the first reference cell design value is changed.
In the step, the packaging chip is tested, whether the threshold voltage of the first reference unit in the packaging chip which is not replaced in the bare chip stage test is changed or not is judged, if the threshold voltage of each first reference unit is not changed, the test is finished, and the packaging chip is a qualified chip; if there is a change in at least one first reference cell design value, step S210 and the following steps are performed.
S210: it is measured whether the second reference cell design value has changed.
In the step, the replaced second reference units are tested, whether the design values of the second reference units change or not is judged, if at least one second reference unit design value changes, the test is finished, and the packaging piece is unqualified; if the design value of the second reference cell corresponding to each defective first reference cell has not changed, step S211 is executed.
S211: and (3) address mapping:
an address map is formed between the defective first reference cell and the second reference cell having the same threshold voltage and no defect, and mapping information is stored in the repair information storage unit 23.
In the first reference unit repairing method shown in the figure, in a bare chip stage, the first reference unit and the second reference unit are required to be set and tested in the bare chip stage and a packaging chip stage, whether the design values of the first reference unit and the second reference unit change or not is judged, and if the design value of the first reference unit does not change, the chip passes the test; if only the first reference unit design value changes, replacing the defective first reference unit with a corresponding second reference unit; if the design values of the first reference unit and the corresponding second reference unit are changed, the chip fails to pass the test, so that each chip passing the test can be ensured to meet the requirements.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (11)
1. A reference cell repair method of a non-volatile memory, comprising:
performing first reference unit repair in a wafer test stage; and
a second reference cell repair is performed during the package test phase,
wherein the reference cell module of the non-volatile memory includes a first sub-array and a second sub-array, and the reference cell repair includes forming an address mapping between a first reference cell of the first sub-array having a defect and a second reference cell of the second sub-array having the same threshold voltage and no defect.
2. The reference cell repair method of claim 1, wherein the first subarray includes a plurality of the first reference cells, the second subarray includes a plurality of the second reference cells, and the first reference cells are the same number as the second reference cells.
3. The reference cell repair method of claim 1 wherein the first reference cell repair comprises:
adjusting a threshold voltage of the first reference cell to a design value;
carrying out aging test on the wafer;
judging whether the first reference unit has defects according to whether the threshold voltage of the first reference unit changes;
adjusting a threshold voltage of the second reference cell to the design value when the first reference cell is defective; and
and forming an address mapping between the second reference unit and the first reference unit with defects and recording mapping information.
4. The reference cell repair method of claim 3 wherein the burn-in test comprises placing the wafer in a 250 ℃ environment for 24 hours.
5. The reference cell repair method of claim 4, wherein the second reference cell repair comprises:
judging whether the first reference unit has defects according to whether the threshold voltage of the first reference unit changes;
adjusting a threshold voltage of the second reference cell to the design value when the first reference cell is defective; and
and forming an address mapping between the second reference unit and the first reference unit with defects and recording mapping information.
6. The reference cell repair method of claim 1 wherein the first reference cell repair comprises:
adjusting a threshold voltage of the first reference cell to a design value;
adjusting a threshold voltage of the second reference cell to the design value;
carrying out aging test on the wafer;
judging whether the first reference unit has defects or not according to whether the threshold voltage of the first reference unit changes or not;
judging whether the second reference unit has defects according to whether the threshold voltage of the second reference unit changes when the first reference unit has defects; and
and forming an address map between the second reference unit and the first reference unit with defects when the second reference unit is not defective, and recording mapping information.
7. The reference cell repair method of claim 6 wherein the burn-in test comprises placing the wafer in a 250 ℃ environment for 24 hours.
8. The reference cell repair method of claim 6 wherein the second reference cell repair comprises:
judging whether the first reference unit repair exists according to the mapping information;
when the first reference unit is not repaired, judging whether the first reference unit has defects according to whether the threshold voltage of the first reference unit changes or not;
judging whether the second reference unit has defects according to whether the threshold voltage of the second reference unit changes when the first reference unit has defects; and
and forming an address mapping between the second reference unit and the first reference unit with a defect and recording mapping information when the second reference unit has no defect.
9. The reference cell repair method of any one of claims 6 to 8 wherein there is a second reference cell for each first reference cell having the same threshold voltage.
10. A reference cell module of a non-volatile memory, comprising:
a first sub-array comprising a plurality of first reference cells;
a second sub-array comprising a plurality of second reference cells;
the reference current generation module selects the first reference unit to generate a reference current according to a reading condition, and selects the corresponding second reference unit to generate the reference current when the first reference unit has a defect.
11. The reference cell module of claim 10, wherein the reference cell further comprises:
the repair information storage module is used for storing address mapping information of the first reference unit and the second reference unit;
and the repair information reading module is connected with the repair information storage module and provides the address mapping information to the reference current generation module.
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