CN115841077A - CMOS inverter single event effect prediction method based on residual error neural network - Google Patents

CMOS inverter single event effect prediction method based on residual error neural network Download PDF

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CN115841077A
CN115841077A CN202211552471.4A CN202211552471A CN115841077A CN 115841077 A CN115841077 A CN 115841077A CN 202211552471 A CN202211552471 A CN 202211552471A CN 115841077 A CN115841077 A CN 115841077A
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event effect
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cmos inverter
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王树龙
刘海宇
陈栋梁
刘伯航
曹宪法
马浩
刘诗杰
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Xidian University
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Abstract

A single event effect prediction method of a CMOS inverter based on a residual error neural network comprises the steps of designing K groups of single event effect parameter data of the CMOS inverter, simulating each group of data by using TCAD software to obtain K single event effect curves of the CMOS inverter, wherein the abscissa of each single event effect curve is time, and the ordinate of each single event effect curve is current or voltage, namely a transient current curve or a transient voltage curve; dividing time into L-1 intervals by using L time points in the simulation process, wherein each time point corresponds to a data point on a single-event effect curve, extracting a single-event effect parameter from the single-event effect curve, and taking data of the data point and a characteristic parameter of the single-event effect as a sample set; and training a residual error neural network prediction model by using the sample set, wherein the model is output as a predicted single event effect curve or a characteristic parameter of the single event effect. The invention improves the efficiency of single event effect research of the CMOS inverter.

Description

CMOS inverter single event effect prediction method based on residual error neural network
Technical Field
The invention belongs to the technical field of CMOS phase inverters, and particularly relates to a CMOS phase inverter single event effect prediction method based on a residual error neural network.
Background
CMOS inverters are the core of almost all digital integrated circuit designs, with the advantages of high fault tolerance, extremely high input resistance, extremely low static power consumption, and insensitivity to noise and interference. The CMOS phase inverter circuit consists of two enhanced MOS field effect transistors, wherein a PMOS transistor (loading transistor) is pulled up, and an NMOS transistor (driving transistor) is pulled down. Inverter cells are indispensable logic cells in various integrated circuits, and the structure and function of the inverter cells make the single event effect of the cells more common and obvious. Meanwhile, when the single event pulse is large enough, the single event transient effect triggers the state of the device to be turned over, the logic state of the inverter is influenced, and then the logic state is transmitted to the lower level of the combinational logic circuit, so that the performance of the whole circuit is influenced, and the stability and the reliability of the integrated circuit are seriously threatened. Therefore, the study of the single event effect in the CMOS inverter is particularly important. Single event effects include Single Event Upset (SEU), single Event Transient (SET), and single event latch-up (SEL). Single event effects can be classified as soft errors and hard errors depending on whether the device is physically damaged or not.
The traditional simulation mode for obtaining the single event effect in the CMOS inverter mainly comprises circuit simulation based on a circuit level model and mixed simulation based on a device numerical simulation tool TCAD model. Before the single event effect of the phase inverter is researched, a device model needs to be established based on TCAD software, a structure model needs to be established by using the software, doping is set, grids are divided, a physical model needs to be set according to the needed simulation, a mixed simulation circuit of the device model and a circuit model needs to be established, and differential equations such as a carrier continuity equation, a Poisson equation and a lattice temperature equation corresponding to the physical model are solved through a solver.
The traditional simulation mode for obtaining the single event effect in the CMOS inverter mainly comprises circuit simulation based on a circuit level model and mixed simulation based on a device numerical simulation tool TCAD model. NMOS and PMOS are modeled respectively, and then are connected into an inverter through sdevice, and then simulation can be carried out, wherein the workload is several times that of a simulation common device. However, only simulating a single-tube FinFET requires huge workload, the simulation time is long, the simulation efficiency is low, and the simulation process is difficult to converge.
Overall, the disadvantages of the prior art can be summarized as:
1. with the continuous reduction of the feature size of the device, especially after the nanometer era, the influence of the non-ideal effects in the field effect transistor, such as short channel effect, quantum effect, parasitic effect, unstable parameters, etc., on the device performance becomes more and more prominent, and the further reduction of the device is severely limited by the structure, material, working mechanism, etc. of the device. The FinFET device not only can inhibit short channel effect and improve sub-threshold characteristics by enhancing gate control capability, but also has the advantage of being compatible with the traditional process.
Single Event Effect (SEE) of finfet devices has become one of the most challenging issues affecting the reliability of modern SEE, which affects the reliability of modern electronic systems in space as well as terrestrial applications.
3. The traditional FinFET device single event effect simulation has the disadvantages of complicated steps, long simulation time, low simulation efficiency and difficulty in convergence in the simulation process.
4. The single event effect simulation of the traditional inverter needs to model NMOS and PMOS respectively, then the NMOS and the PMOS are connected into the inverter through sdevice, and then the simulation can be carried out, and the workload is several times of that of a simulation common device.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a Single Event Effect (SEE) prediction method of a Complementary Metal Oxide Semiconductor (CMOS) inverter based on a residual neural network, a single event effect curve and corresponding characteristic parameters can be quickly and accurately obtained by inputting different particle incidence conditions, a neural network model used in an experiment has higher prediction precision, and the problems of long development period, low efficiency and difficulty in convergence of the traditional single event effect research method are solved.
In order to achieve the purpose, the invention adopts the technical scheme that:
a CMOS inverter single event effect prediction method based on a residual error neural network comprises the following steps:
step 1, designing K groups of single event effect parameter data of a CMOS inverter, and simulating each group of data by using TCAD software to obtain K single event effect curves of the CMOS inverter, wherein the abscissa of the single event effect curve is time, and the ordinate is current or voltage, namely a transient current curve or a transient voltage curve; dividing time into L-1 intervals by using L time points in the simulation process, wherein each time point corresponds to a data point on a single-event effect curve, extracting a single-event effect parameter from the single-event effect curve, and taking data of the data point and a characteristic parameter of the single-event effect as a sample set;
the single event effect parameters comprise linear transmission energy (LET), an incidence position (x) of the particle, an incidence angle (theta) of the particle and a characteristic distance (Wt _ hi) of the incidence of the particle; the characteristic parameter of the single event effect comprises output current I 0 And total output charge Q 0 ；
Step 2, randomly dividing a sample set into a training set and a verification set according to a proportion; respectively carrying out standardization processing on the single event effect parameters of the training set and the verification set;
step 3, constructing a residual error neural network prediction model;
step 4, training the residual error neural network prediction model by using a training set and a verification set, and iteratively updating network parameters of the residual error neural network prediction model by using a back propagation algorithm to obtain a trained prediction model; the input is single event effect parameters, and when the single event effect parameters are used for predicting a single event effect curve, the single event effect curve which is synthesized by L data points is output; outputting the characteristic parameters of the single event effect when the characteristic parameters are used for predicting the single event effect;
and 5, inputting different single event effect parameters of the CMOS inverter into the trained residual neural network prediction model to obtain a predicted single event effect curve or characteristic parameters of the single event effect.
In the embodiment of the invention, K groups of single event effect parameter data are obtained by continuously changing the single event effect parameters of the CMOS inverter, each group of single event effect parameter data are simulated by using TCAD software, and the single event effect parameters and the characteristic parameters of the single event effect are extracted, namely a sample set with the sample capacity of K is obtained, wherein other parameters except the single event effect parameters are kept unchanged during simulation.
In the embodiment of the invention, the residual error neural network prediction model comprises an input layer, a first full-connection layer, a convolutional layer, a second full-connection layer and an output layer which are connected in sequence;
the input layer is used for inputting different single event effect parameters of the CMOS phase inverter; the number of the neurons of the input layer is the same as that of single event effect parameters of the CMOS phase inverter;
the first full-connection layer performs dimension expansion on the input vector, and the batch normalization layer is used for preventing overfitting;
the convolution layer comprises a first convolution layer and a second convolution layer and is used for performing convolution on the characteristics output by the full-connection layer;
the second full-connection layer reduces the dimension of the output vector, and the batch normalization layer is used for preventing overfitting;
the output layer is used for outputting a single event effect transient characteristic curve or a single event effect characteristic parameter of the CMOS inverter; the number of the neurons of the output layer is the same as the number of data points taken by a single-event effect transient characteristic curve of the CMOS inverter or the number of single-event effect characteristic parameters of the CMOS inverter.
Compared with the prior art, the method uses the residual error neural network to research the relation between the single event effect influence factor and the transient current curve or the transient voltage curve of the CMOS inverter, so that the transient current curve or the transient voltage curve can be quickly predicted according to the single event effect influence factor, characteristic parameters of the curve can be quickly predicted according to the single event effect influence factor, the single event effect of the CMOS inverter can be accurately and quickly predicted, the problems of long time consumption, non-convergence and the like of the traditional research method for modeling the CMOS inverter based on simulation software and single event effect simulation are solved, and the efficiency of single event effect research of the CMOS inverter is improved.
Drawings
Fig. 1 is a schematic structural diagram of a CMOS inverter used in embodiment 1 of the present invention.
Fig. 2 is a CMOS inverter transfer characteristic curve according to embodiment 1 of the present invention.
Fig. 3 is a schematic diagram illustrating the influence of different single event effect parameters on the transfer characteristic curve of the CMOS inverter in embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of the residual neural network prediction model of the present invention. Wherein (a) is the residual neural network prediction model of example 1, and (b) is the residual neural network prediction model of example 2.
FIG. 5 is a comparison graph of the predicted value of the single event effect transient voltage curve of the test set CMOS inverter and the true value of the single event effect transient voltage curve of the test set CMOS inverter in embodiment 1 of the present invention; fig. 5 (a) - (f) are diagrams showing the predicted value and the true value of six randomly selected single event effect transient voltage curves.
Fig. 6 is a graph comparing the Mean Square Error (MSE) graph of the predicted value and the true value with the prediction result of the residual neural network and the machine learning in embodiment 1 of the present invention.
FIG. 7 is a comparison graph of the predicted value of the single-event effect transient current curve of the test set CMOS inverter and the true value of the single-event effect transient current curve of the test set CMOS inverter in embodiment 1 of the present invention; fig. 5 (a) - (f) are diagrams showing the comparison between predicted values and actual values of six randomly selected single event effect transient current curves.
Fig. 8 is a comparison graph of Mean Square Error (MSE) graph of predicted value and true value and prediction result of residual neural network and machine learning in embodiment 1 of the present invention.
FIG. 9 is a schematic view ofIn embodiment 2 of the present invention, a comparison graph of a predicted value and a true value of a characteristic parameter of a single-particle effect, and a comparison graph of a prediction result of a residual neural network and machine learning are shown; wherein (a) - (b) are total current I 0 And total charge Q 0 A comparison graph of the predicted value and the true value of (1); (c) - (d) predicting the total current I for the residual neural network and the machine learning, respectively 0 And total charge Q 0 The results of (A) are compared with the graphs.
Description of reference numerals: 1High-k dielectric, 2 source region, 3 drain region, 4 field oxide layer and 5 substrate.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention.
Example 1
The CMOS inverter single event effect prediction method based on the residual error neural network comprises the following steps:
step 1, acquiring a plurality of groups of single event effect curves of the CMOS inverter, and extracting data (voltage or current) of data points on the curves to be used as a sample set. The single event effect curve may be a transient voltage curve or a transient current curve.
The single-event-effect parameters of the CMOS inverter comprise linear transmission energy (LET), an incident position (x) of a particle, an incident angle (theta) of the particle and a characteristic distance (Wt _ hi) of the particle incidence.
Referring to fig. 1, a schematic structural diagram of the CMOS inverter according to this embodiment is shown, where the CMOS inverter is composed of two enhancement MOS field effect transistors, where a PMOS transistor (loading transistor) is pulled up and an NMOS transistor (driving transistor) is pulled down. The PMOS tube is a P-type FinFET device, and the NMOS tube is an N-type FinFET device. The device comprises a High-k dielectric 1, a source region 2, a drain region 3, a field oxide layer 4 and a substrate 5. The FinFET device has the following parameters:
the thickness of the High-k dielectric 1 is 2nm. The uniform doping concentration of the source region 2 is 1 × 10 20 /cm 3 . The drain region 3 has a uniform doping concentration of 1 × 10 20 /cm 3 . The gate length LG is 30nm. Fin height of 40nm. The Fin width is 14nm in length. The work function WF across the device is 4.5V. The substrate 5 has a uniform doping concentration of 1 × 10 17 /cm 3 . In this embodiment, the dopant species may be phosphorus or boron, resulting in a P-type or N-type FinFET device.
Referring to fig. 2, the basic characteristics and transient voltage curves of the CMOS inverter of the present invention are shown.
According to the method, a single event effect transient current curve and a characteristic parameter data set of the CMOS inverter are obtained in a TCAD device model hybrid simulation mode.
Referring to fig. 3, a schematic diagram of an influence of different single event effect parameters on a transient voltage curve of a CMOS inverter in embodiment 1 of the present invention is shown.
3000 groups of data are obtained by continuously changing the single event effect parameters of the CMOS inverter, and the values of the parameters are as follows:
the Linear Energy Transfer (LET) is 10MeV/cm, 20MeV/cm, 30MeV/cm, 40MeV/cm, 50MeV/cm, 60MeV/cm, 70MeV/cm, 80MeV/cm, 90MeV/cm, 100MeV/cm. The incident position (x) of the particle is 25nm, 50nm, 75nm, 100nm, 125nm, 150nm, 175nm, 200nm, and 225nm. The incident angle (theta) of the particle is-30 degrees, -15 degrees, 0 degrees, 15 degrees and 30 degrees respectively. The characteristic distances (Wt _ hi) of particle incidence are respectively 5nm, 10nm, 15nm, 20nm, 25nm, 30nm and 35nm.
The combination can obtain 3150 groups of data, and after some irregular data are sorted and deleted, 3000 groups of data are reserved.
And then, simulating each group of parameter data by using TCAD software (other parameters except the parameters are kept unchanged), obtaining 3000 single-event effect curves of the CMOS inverter, and extracting corresponding single-event effect parameters and data (current or voltage) of data points, namely obtaining a sample set with the sample capacity of 3000.
Specifically, a transient current curve and a transient voltage curve obtained by TCAD simulation software, that is, the abscissa of a single-event effect curve is time, and the ordinate is current or voltage, in the simulation process, the single-event effect curve is divided into 200 intervals within a fixed time, that is, 201 time points divide the time into 200 intervals, and each time point corresponds to a data point on the single-event effect curve, so that the curve predicted by the neural network model is also a curve formed by connecting 201 points.
Step 2, randomly dividing 3000 groups of data of the sample set into a training set, a verification set and a test set according to the proportion of 8; and respectively carrying out standardization processing on the single event effect parameters of the CMOS inverters of the training set and the verification set.
The normalization process is to transform the data into a distribution with a mean value of 0 and a standard deviation of 1, and the conversion function is expressed by the following equation:
Figure BDA0003981879480000071
the normalization process is to change a list of data to some fixed interval or range, usually this interval is 0,1]The common transfer function is shown as formula: />
Figure BDA0003981879480000072
The normalization or normalization of the data is performed to eliminate the effect of different features of the sample having different magnitudes.
And 3, constructing a residual error neural network prediction model.
Specifically, the input of the residual error neural network prediction model is a single event effect parameter of the CMOS inverter, and the output of the residual error neural network prediction model is a transient current curve of the single event effect of the CMOS inverter, that is, the single event effect curve of the present invention.
The structure of the residual error neural network adopted by the invention is optimized, and the single event effect transient current curve and the characteristic parameters of the CMOS inverter can be quickly and accurately obtained. Referring to fig. 4 (a), the residual neural network prediction model includes an input layer, a first fully-connected layer, a convolutional layer, a second fully-connected layer, and an output layer, which are connected in sequence.
The input layer is used for inputting different single event effect parameters of the CMOS phase inverter; the number of the neurons of the input layer is the same as that of single event effect parameters of the CMOS phase inverter;
the first full-connection layer consists of two full-connection layers, dimension expansion can be carried out on input vectors, and the batch normalization layer is used for preventing overfitting;
the convolution layer comprises a first convolution layer and a second convolution layer and is used for performing convolution on the characteristics output by the full-connection layer;
the second full-connection layer consists of three full-connection layers, the output vector is subjected to dimensionality reduction, and the batch normalization layer is used for preventing overfitting;
the output layer is used for outputting a single event effect transient characteristic curve of the CMOS inverter; the number of the neurons of the output layer is the same as the number of data points taken by a single event effect transient characteristic curve of the CMOS inverter.
In the residual neural network prediction model constructed in this embodiment, the number of neurons in the input layer is 4, the dimensionality is expanded to 600 by two fully-connected layers of the first fully-connected layer, the feature convolution output to the fully-connected layers by the first convolution layer and the second convolution layer is 64 × 150, the dimensionality is reduced to 201 neurons by three fully-connected layers of the second fully-connected layer, and the obtained result is output by the output layer.
Step 4, training the residual error neural network prediction model by using the training set and the verification set, and iteratively updating the network parameters of the residual error neural network prediction model by using a back propagation method to obtain a trained prediction model;
specifically, in the training process, data of a single-event effect transient current curve or a transient voltage curve of the CMOS inverter in the training set and the verification set are used as labels; and (3) calculating a loss function ReLu of each batch of training, and performing back propagation on the optimized network parameters by adopting an SGD (generalized minimum) optimizer until the residual neural network prediction model converges to obtain the trained residual neural network prediction model.
And 5, inputting single event effect parameters of the CMOS inverter of the test set into the trained residual neural network prediction model to obtain a predicted transient current curve of the single event effect of the CMOS inverter.
Referring to fig. 5, it can be seen that the residual neural network of this embodiment 1 can well predict the transient voltage curve of the single event effect of the CMOS inverter.
Referring to fig. 6, it can be seen that the prediction capability of the residual neural network in this embodiment 1 on the single-event-effect transient voltage curve of the CMOS inverter is much stronger than that of other machine learning algorithms, and the prediction mean square error of the residual neural network on the single-event-effect transient voltage curve of the CMOS inverter is not large.
Referring to fig. 7, it can be seen that the residual error neural network of this embodiment 1 can well predict the transient current curve of the single event effect of the CMOS inverter;
referring to fig. 8, it can be seen that the prediction capability of the residual neural network in this embodiment 1 on the single-event-effect transient current curve of the CMOS inverter is much stronger than that of other machine learning algorithms, and the prediction mean square error of the residual neural network on the single-event-effect transient current curve of the CMOS inverter is not large.
Example 2
The CMOS inverter single event effect prediction method based on the residual error neural network comprises the following steps:
step 1, acquiring a plurality of groups of single event effect curves of a CMOS inverter, and extracting single event effect parameters and characteristic parameters of the single event effect as a sample set;
the single event effect parameters of the CMOS inverter comprise linear transmission energy (LET), an incident position (x) of a particle, an incident angle (theta) of the particle and a characteristic distance (Wt _ hi) of the particle incidence; the characteristic parameter of the single event effect of the CMOS inverter comprises an output current I 0 And total output charge Q 0 ；
In particular, the output current I 0 The formula (1) is as follows:
Figure BDA0003981879480000091
in the formula (1), q is an electronic charge,. Mu. n Is the electron mobility, N a Is the doping concentration of the channel, N is the linear density of electron-hole pairs, ε is the dielectric constant, x p Is the width of the PN junction depletion region;
the total output charge Q 0 The formula (2) is as follows:
Figure BDA0003981879480000092
in the formula (2), I drain Is the source-drain current of the FinFET device;
the linear transmission energy (LET) calculation formula is as follows:
Figure BDA0003981879480000093
in formula (3), the unit is MeV/cm, where dE Δ Is the energy lost by impact ionization with the material when a single particle is incident at distance dx.
Step 2, randomly dividing 3000 groups of data of the sample set into a training set, a verification set and a test set according to the proportion of 8; respectively carrying out standardization processing on the single event effect parameters of the CMOS inverters of the training set and the verification set;
step 3, constructing a residual error neural network prediction model;
specifically, the input of the residual error neural network prediction model is a single event effect parameter of the CMOS inverter, and the output of the residual error neural network prediction model is a characteristic parameter of the single event effect of the CMOS inverter;
referring to fig. 4 (b), the residual neural network prediction model includes an input layer, a fully-connected layer, a convolutional layer, a fully-connected layer, and an output layer, which are connected in sequence.
The input layer is used for inputting different single event effect parameters of the CMOS phase inverter; the number of the neurons of the input layer is the same as that of single event effect parameters of the CMOS phase inverter;
the first full-connection layer consists of two full-connection layers, dimension expansion can be carried out on input vectors, and the batch normalization layer is used for preventing overfitting;
the convolution layer part comprises two convolution layers, and the convolution unit is used for performing convolution on the characteristics output by the full connection layer;
the second full-connection layer consists of three full-connection layers, the output vector is subjected to dimensionality reduction, and the batch normalization layer is used for preventing overfitting;
the output layer is used for outputting the characteristic parameters of the single event effect of the CMOS inverter; the number of the neurons of the output layer is the same as the number of the single event effect characteristic parameters of the CMOS phase inverter.
In the residual neural network prediction model constructed in this embodiment, the number of neurons in the input layer is 4, the dimensionality is expanded to 200 by two fully-connected layers of the first fully-connected layer, the characteristics output to the fully-connected layers by the first convolutional layer and the second convolutional layer are convolved to 32 × 50, the dimensionality is reduced to 2 neurons by three fully-connected layers of the second fully-connected layer, and the obtained result is output by the output layer.
Step 4, training the residual error neural network prediction model by using the training set and the verification set, and iteratively updating the network parameters of the residual error neural network prediction model by using a back propagation method to obtain a trained prediction model;
specifically, in the training process, the characteristic parameters of the single event effect of the CMOS inverters in the training set and the verification set are used as labels; and (3) calculating a loss function ReLu of each batch of training, and performing back propagation on the optimized network parameters by adopting an SGD (generalized minimum) optimizer until the residual neural network prediction model converges to obtain the trained residual neural network prediction model.
The neural network training mode adopted by the invention comprises the selection of a loss function and the use of an early stopping method, so that overfitting can be prevented and a better training effect can be obtained.
And 5, inputting the single event effect parameters of the CMOS inverter of the test set into the trained residual neural network prediction model to obtain the predicted characteristic parameters of the single event effect of the CMOS inverter.
Referring to fig. 9, it can be seen that the residual neural network of this embodiment 2 can well predict the characteristic parameters of the single event effect of the CMOS inverter, and the prediction capability of the residual neural network for the characteristic parameters of the single event effect of the CMOS inverter is much higher than that of other machine learning algorithms.
The data set input data value selected by the invention can reflect the working conditions and device parameters of the actual CMOS inverter, and has a generalization meaning, so that the trained residual neural network model can be expanded to the application requirements of actual prediction.
Although the present invention has been described in detail in this specification with reference to specific embodiments and illustrative embodiments, it will be apparent to those skilled in the art that modifications and improvements can be made thereto based on the present invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims (7)

1. A single event effect prediction method of a CMOS inverter based on a residual error neural network is characterized by comprising the following steps:
step 1, designing K groups of single event effect parameter data of a CMOS inverter, simulating each group of data by using TCAD software to obtain K single event effect curves of the CMOS inverter, wherein the abscissa of the single event effect curve is time, and the ordinate of the single event effect curve is current or voltage, dividing the time into L-1 intervals by L time points in the simulation process, each time point corresponds to a data point on the single event effect curve, and extracting single event effect parameters, data of the data points and characteristic parameters of the single event effect from the single event effect curve to serve as a sample set;
the single event effect parameters comprise linear transmission energy (LET), an incidence position (x) of the particle, an incidence angle (theta) of the particle and a characteristic distance (Wt _ hi) of the incidence of the particle; the characteristic parameter of the single event effect comprises output current I 0 And total output charge Q 0 ；
Step 2, randomly dividing the sample set into a training set and a verification set according to a proportion; respectively carrying out standardization processing on the single event effect parameters of the training set and the verification set;
step 3, constructing a residual error neural network prediction model;
step 4, training the residual error neural network prediction model by using a training set and a verification set, and iteratively updating network parameters of the residual error neural network prediction model by using a back propagation algorithm to obtain a trained prediction model; the input is single event effect parameters, and when the single event effect parameters are used for predicting a single event effect curve, the single event effect curve which is synthesized by L data points is output; outputting the characteristic parameters of the single event effect when the characteristic parameters are used for predicting the single event effect;
and 5, inputting different single event effect parameters of the CMOS inverter into the trained residual neural network prediction model to obtain a predicted single event effect curve or characteristic parameters of the single event effect.
2. The residual neural network-based single event effect prediction method for CMOS inverter according to claim 1, wherein the output current I is 0 The calculation formula of (a) is as follows:
Figure FDA0003981879470000021
wherein q is an electronic charge,. Mu. n Is electron mobility, N a Is the doping concentration of the channel, N is the linear density of electron-hole pairs, ε is the dielectric constant, x p Is the width of the PN junction depletion region;
the total output charge Q 0 The calculation formula of (a) is as follows:
Figure FDA0003981879470000022
in the formula I drain Is the source-drain current of the FinFET device;
the linear transmission energy (LET) calculation formula is as follows:
Figure FDA0003981879470000023
wherein the unit is MeV/cm, where dE Δ Is the energy lost by impact ionization with the material when a single particle is incident at distance dx.
3. The method for predicting the single event effect of the CMOS inverter based on the residual neural network as claimed in claim 1, wherein the CMOS inverter circuit is composed of two enhancement type MOS field effect transistors, wherein a PMOS transistor is pulled up, an NMOS transistor is pulled down, the PMOS transistor is a P-type FinFET device, and the NMOS transistor is an N-type FinFET device.
4. The method for predicting the single event effect of the CMOS inverter based on the residual error neural network according to claim 1, wherein K groups of single event effect parameter data are obtained by continuously changing the single event effect parameters of the CMOS inverter, TCAD software is used for simulating the single event effect parameter data of each group, and the single event effect parameters and the characteristic parameters of the single event effect are extracted, namely a sample set with the sample capacity of K is obtained, wherein other parameters except the single event effect parameters are kept unchanged during simulation.
5. The method for predicting the single event effect of the CMOS inverter based on the residual neural network according to claim 1, wherein the residual neural network prediction model comprises an input layer, a first fully-connected layer, a convolutional layer, a second fully-connected layer and an output layer which are sequentially connected;
the input layer is used for inputting different single event effect parameters of the CMOS phase inverter; the number of the neurons of the input layer is the same as that of single event effect parameters of the CMOS phase inverter;
the first full-connection layer performs dimension expansion on the input vector, and the batch normalization layer is used for preventing overfitting;
the convolution layer comprises a first convolution layer and a second convolution layer and is used for performing convolution on the characteristics output by the full-connection layer;
the second full-connection layer reduces the dimension of the output vector, and the batch normalization layer is used for preventing overfitting;
the output layer is used for outputting a single event effect transient characteristic curve or a single event effect characteristic parameter of the CMOS inverter; the number of the neurons of the output layer is the same as the number of data points taken by a single-event effect transient characteristic curve of the CMOS inverter or the number of single-event effect characteristic parameters of the CMOS inverter.
6. The single event effect prediction method of the CMOS inverter based on the residual neural network as claimed in claim 5, wherein when the method is used for predicting a single event effect curve, in the residual neural network prediction model, the number of neurons in an input layer is 4, the first fully-connected layer has two layers, the dimension is expanded to 600, the feature output by the convolution layer to the first fully-connected layer is convolved to 64 x 150, the second fully-connected layer has three layers, the dimension is reduced to 201 neurons, and the obtained result is output through an output layer.
7. The single event effect prediction method of the CMOS inverter based on the residual neural network according to claim 5, wherein when the prediction model is used to predict the characteristic parameters of the single event effect, the number of neurons in the input layer is 4, the first fully-connected layer has two layers, the dimension is extended to 200, the feature output by the convolutional layer to the first fully-connected layer is convolved to 32 × 50, the second fully-connected layer has three layers, the dimension is reduced to 2 neurons, and the result is output through the output layer.
CN202211552471.4A 2022-12-05 2022-12-05 CMOS inverter single event effect prediction method based on residual error neural network Pending CN115841077A (en)

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