CN115835767A - Method for preparing Josephson junction and superconductive electronic device - Google Patents

Abstract

The invention provides a Josephson junction and a preparation method of a superconducting electronic device, wherein a first superconducting layer and a second superconducting layer with different thicknesses are prepared, after the Josephson junction is predefined, the second superconducting layer can be subjected to primary over-etching to form a first superconducting strip line, an insulating protective layer is directly grown and stripped, a third superconducting layer is prepared, etching of the second superconducting strip line is carried out, and the second superconducting layer, namely the first superconducting strip line, is subjected to secondary over-etching simultaneously, so that the preparation method of the Josephson junction with submicron or deep submicron scale is provided through a double over-etching process, the problem of accuracy limitation of existing process equipment can be solved, the cost of process equipment is reduced, and the preparation method is suitable for reliably preparing a high-performance practical superconducting quantum interference device and other superconducting electronic devices based on the Josephson junction.

Description

Method for preparing Josephson junction and superconductive electronic device

Technical Field

The invention belongs to the technical field of superconduction, and relates to a preparation method of a Josephson junction and a superconducting electronic device.

Background

A common josephson junction is a superconducting-insulating-superconducting (SIS) sandwich structure, and is also a quantum device with a josephson tunneling effect. For example, a superconducting magnetic sensor called a superconducting quantum interference device (SQUID) can be formed using a Josephson junction and a superconducting ring, and has high sensitivity and low noise, and the magnetic field noise can be as low as<1fT/Hz ^1/2 (fT＝10 ^-15 T), is the most sensitive practical magnetic sensor at present, and has wide application in the fields of biomagnetic detection, extremely low field nuclear magnetic resonance, geophysical exploration and the like.

The existing preparation of the Josephson junction and the SQUID benefits from the rapid development of a semiconductor process, namely, the chip development is carried out by utilizing mature planar micro-nano processing processes such as thin film photoetching, etching and the like. The smaller size of semiconductor transistors is being pursued, and therefore, the demand for equipment such as a lithography machine is becoming higher and the equipment cost is increasing.

For the preparation of josephson junctions and SQUIDs, technical means such as electron beams, focused ion beams, step projection lithography (stepper), contact ultraviolet lithography and the like can be adopted, but when the wafer-level batch chip preparation is oriented, stepper is preferred in terms of process precision and efficiency. At present, stepper with process accuracy at the hundred nanometer level needs about ten million RMB, which becomes the heavy cost of chip iteration and process upgrading. In the future, the increase in equipment cost has become a significant issue in the progression to deep submicron josephson junction processes.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a josephson junction and a method for manufacturing a superconducting electronic device, which are used to solve the problem of limitation of the lithography precision of semiconductor devices encountered in the prior art when manufacturing josephson junctions.

To achieve the above and other related objects, the present invention provides a method for preparing a josephson junction, comprising the steps of:

providing a substrate;

forming a first superconducting layer, an insulating barrier layer and a second superconducting layer stacked from bottom to top on the substrate, wherein the first superconducting layer has a first thickness, the second superconducting layer has a second thickness, and the first thickness is greater than the second thickness;

etching the second superconducting layer and the insulating barrier layer to expose part of the first superconducting layer;

etching the exposed first superconducting layer to form a lower layer leading-out electrode, and simultaneously etching the second superconducting layer to form a first superconducting strip line on the insulating barrier layer;

forming an insulating protection layer, wherein the insulating protection layer covers the insulating barrier layer and exposes the surface of the first superconducting strip line and the surface of the lower-layer extraction electrode;

forming a third superconducting layer on the first superconducting strip line;

and etching the third superconducting layer to form a second superconducting strip line and an upper extraction electrode, simultaneously etching the first superconducting strip line to expose the insulating barrier layer, and enabling the second superconducting strip line and the first superconducting strip line to be crossed to form a Josephson junction.

Optionally, the ratio of the thickness of the second superconducting layer to the thickness of the first superconducting layer is in the range of 1.

Optionally, the first superconducting layer has a thickness of 100nm to 200nm, and the second superconducting layer has a thickness of 50nm to 100nm.

Optionally, the second superconducting strip line is formed perpendicular to the first superconducting strip line.

Optionally, the josephson junction is formed in a size range of 300nm to 600nm.

Optionally, the insulating protection layer includes one or a combination of a silicon oxide layer, a silicon dioxide layer, and a silicon nitride layer.

Optionally, the substrate comprises one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate, and a silicon carbide substrate; the substrate comprises a wafer level substrate.

Optionally, the first superconducting layer comprises at least one of a niobium nitride layer and a niobium layer; the second superconducting layer comprises at least one of a niobium nitride layer and a niobium layer; the third superconducting layer comprises at least one of a niobium nitride layer and a niobium layer; the insulating barrier layer includes at least one of an aluminum layer, an aluminum oxide layer, and an aluminum nitride layer.

The present invention also provides a method of manufacturing a superconducting electronic device, the method of manufacturing the superconducting electronic device comprising manufacturing a josephson junction using any one of the above methods of manufacturing a josephson junction.

Optionally, the superconducting electronic device is a superconducting quantum interference device, and further includes a step of forming a passivation layer covering the insulating protection layer after the insulating protection layer is formed, and the step of preparing the passivation layer is after a resistive layer of the superconducting quantum interference device is formed.

As described above, according to the method for manufacturing a josephson junction and a superconducting electronic device of the present invention, by manufacturing the first superconducting layer and the second superconducting layer having different thicknesses, after the josephson junction is predefined, the first superconducting stripe line can be formed by performing the first over-etching on the second superconducting layer, and the growth and the peeling of the insulating protection layer are directly performed, and then the third superconducting layer is manufactured, and the etching of the second superconducting stripe line is performed, and at the same time, the second superconducting layer, i.e., the first superconducting stripe line, is performed the second over-etching, so that the method for manufacturing a josephson junction in submicron to deep submicron scale is provided through the double over-etching process, which can solve the accuracy limitation of the existing process equipment, thereby reducing the cost of the process equipment, and is suitable for the reliable manufacturing of high-performance practical superconducting quantum interference devices and other superconducting electronic devices based on josephson junctions.

Drawings

FIG. 1 is a schematic diagram of a process for preparing a Josephson junction according to an embodiment of the present invention.

Fig. 2 is a schematic view showing a structure after forming a second superconducting layer in the embodiment of the present invention.

Fig. 3 is a schematic structural diagram illustrating a josephson junction at a predetermined position after etching the second superconducting layer and the insulating barrier layer according to an embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a lower extraction electrode and a first superconducting strip line formed according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram illustrating a structure after forming an insulating protection layer according to an embodiment of the invention.

Fig. 6 is a schematic structural view after an upper extraction electrode and a second superconducting strip line are formed in the embodiment of the invention.

FIG. 7 is a scanning electron microscope photograph of area A of FIG. 6.

Description of the element reference numerals

100. Substrate

200. First superconducting layer

201. Lower extraction electrode

300. Insulating barrier layer

400. Second superconducting layer

401. First superconducting strip line

500. Insulating protective layer

601. Upper extraction electrode

602. Second superconducting strip line

700. Josephson junction

Region A

S1 to S7

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In which an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Expressions such as "between 8230 \\8230"; "between 8230"; "may be used herein, inclusive, and expressions such as" plurality "may be used, inclusive, and expressions such as two or more, unless specifically limited otherwise. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, this embodiment provides a method for preparing a josephson junction, comprising the steps of:

s1: providing a substrate;

s2: forming a first superconducting layer, an insulating barrier layer and a second superconducting layer stacked from bottom to top on the substrate, wherein the first superconducting layer has a first thickness, the second superconducting layer has a second thickness, and the first thickness is greater than the second thickness;

s3: etching the second superconducting layer and the insulating barrier layer to expose part of the first superconducting layer;

s4: etching the exposed first superconducting layer to form a lower layer leading-out electrode, and simultaneously etching the second superconducting layer to form a first superconducting strip line on the insulating barrier layer;

s5: forming an insulating protection layer, wherein the insulating protection layer covers the insulating barrier layer and exposes the surface of the first superconducting strip line and the surface of the lower-layer extraction electrode;

s6: forming a third superconducting layer on the first superconducting strip line;

s7: and etching the third superconducting layer to form a second superconducting strip line and an upper extraction electrode, simultaneously etching the first superconducting strip line to expose the insulating barrier layer, and enabling the second superconducting strip line and the first superconducting strip line to be crossed to form a Josephson junction.

The following will be further described with reference to fig. 2 to 7, in which the preparation of the josephson junction specifically includes:

first, as shown in fig. 2, steps S1 and S2 are performed, a substrate 100 is provided, and a first superconducting layer 200, an insulating barrier layer 300, and a second superconducting layer 400 are formed on the substrate 100 from bottom to top, wherein the first superconducting layer 200 has a first thickness, the second superconducting layer has a second thickness, and the first thickness is greater than the second thickness.

As an example, the substrate 100 may include one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate, and a silicon carbide substrate, which may be selected according to needs. The substrate 100 may be a wafer-level substrate, such as a 6-inch, 8-inch, 12-inch, etc., or a small sample substrate with irregular shape or regular shape, and the shape and size of the substrate 100 are not limited herein.

As an example, the first superconducting layer 200 may include at least one of a niobium nitride layer and a niobium layer; the second superconducting layer 400 may include at least one of a niobium nitride layer and a niobium layer; the insulating barrier layer 300 can include at least one of an aluminum layer, an aluminum oxide layer, and an aluminum nitride layer.

Specifically, the first superconducting layer 200, the insulating barrier layer 300, and the second superconducting layer 400 may be grown by using a magnetron sputtering technique, in this embodiment, the material of each of the first superconducting layer 200 and the second superconducting layer 400 is commonly niobium (Nb), and the material of the insulating barrier layer 300 is aluminum oxide formed by oxidizing aluminum in oxygen, where the oxidation time and the oxidation pressure determine the thickness of the aluminum oxide and the critical current density of a subsequently prepared josephson junction, but the selection of the material of the first superconducting layer 200, the insulating barrier layer 300, and the second superconducting layer 400 is not limited thereto.

In the three-layer film, the first superconducting layer 200 and the second superconducting layer 400 have different film thicknesses, and the second superconducting layer 400 located at the upper layer is thinner than the first superconducting layer 200 located at the lower layer, as required by the subsequent over-etching process.

As an example, the ratio of the thickness of the second superconducting layer 400 to the thickness of the first superconducting layer 200 may range from 1.

Specifically, for the requirement of the subsequent over-etching process, the ratio of the thickness of the second superconducting layer 400 to the thickness of the first superconducting layer 200 may range from 1.

Wherein the first superconducting layer 200 may have a thickness of 100nm to 200nm, such as 100nm, 150nm, 200nm, etc., and the second superconducting layer 400 may have a thickness of 50nm to 100nm, such as 50nm, 80nm, 100nm, etc.

Next, as shown in fig. 3, step S3 is performed to etch the second superconducting layer 400 and the insulating barrier layer 300, and expose a portion of the first superconducting layer 200.

Specifically, after removing a portion of the second superconducting layer 400 and the insulating barrier layer 300 by using photolithography and etching techniques, the position of the josephson junction to be subsequently prepared may be predefined, where the method for etching the second superconducting layer 400 may use reactive ion etching, and the method for etching the insulating barrier layer 300 may use ion beam etching techniques, but is not limited thereto, and this step is an early preparation work for the preparation of the josephson junction.

Next, as shown in fig. 4, step S4 is performed, in which the exposed first superconducting layer 200 is etched to form a lower extraction electrode 201, and the second superconducting layer 400 is etched to form a first superconducting strip line 401 on the insulating barrier layer 300.

Specifically, the first superconducting strip line 401 may be formed by etching the second superconducting layer 400 at the predefined position formed in step S3 by using photolithography and etching techniques, and the outside of the predefined position is etched and removed except for the necessary electrode, so as to form the lower extraction electrode 201 by etching the first superconducting layer 200.

In the etching process, the second superconducting layer 400 on the upper layer at the predefined position and the first superconducting layer 200 on the lower layer outside the predefined position are etched at the same time, but because the first superconducting layer 200 and the second superconducting layer 400 have different thicknesses, the thinner second superconducting layer 400 on the upper layer is subjected to the first etching, and thus the actual etching size of the formed first superconducting strip line 401 is smaller than the design size. During the over-etching, the insulating barrier layer 300 at the predefined location may be applied as an etch stop layer to prevent the over-etching from affecting the first superconducting layer 200 at the predefined location.

Next, as shown in fig. 5, step S5 is performed to form an insulating protection layer 500, where the insulating protection layer 500 covers the insulating barrier layer 300 and exposes the surface of the first superconducting stripe line 401 and the surface of the lower extraction electrode 201.

Specifically, after step S4 is performed, a photoresist mask (not shown) applied in the etching process and located on the surfaces of the lower extraction electrode 201 and the first superconducting strip line 401 may not be removed, but the growth of the insulating protection layer 500 is performed, and after the growth of the insulating protection layer 500 is completed, a stripping operation of the photoresist mask may be performed to expose the surfaces of the first superconducting strip line 401 and the lower extraction electrode 201 again.

As an example, the insulating protection layer 500 may include one or a combination of a silicon oxide layer, and a silicon nitride layer.

Specifically, the insulating protection layer 500 can provide a good protection effect, and the insulating protection layer 500 can be a single layer or a stack of different materials according to requirements, which is not limited herein.

Next, as shown in fig. 6, steps S6 and S7 are performed, a third superconducting layer (not shown) is formed on the first superconducting strip line 401, and the third superconducting layer is etched to form a second superconducting strip line 602 and an upper extraction electrode 601, and the first superconducting strip line 401 is etched to expose the insulating barrier layer 300, and the second superconducting strip line 602 crosses the first superconducting strip line 401 to form a josephson junction 700.

Specifically, while the etching is performed with respect to the second superconducting strip line 602, in addition to the portion that remains overlapping with the first superconducting strip line 401, the other portion of the first superconducting strip line 401 needs to be removed to expose the insulating barrier layer 300, which is also the second over-etching of the second superconducting layer 400 located on the upper layer.

As an example, the third superconducting layer may include at least one of a niobium nitride layer and a niobium layer.

Specifically, for the preparation of the third superconducting layer, the selection of the material, and the like, reference may be made to the above description of the first superconducting layer 200 and the second superconducting layer 400, which is not repeated herein.

As an example, the second superconducting strip line 602 is formed perpendicular to the first superconducting strip line 401.

Specifically, in order to further reduce the size of the formed josephson junction 700 in this embodiment, the second superconducting strip line 602 is preferably perpendicular to the first superconducting strip line 401, but the included angle between the second superconducting strip line 602 and the first superconducting strip line 401 is not limited thereto.

As an example, the josephson junction 700 is formed in a size range of 300nm to 600nm.

Specifically, the josephson junction 700 may be formed to have a size of 300nm, 400nm, 500nm, 600nm, etc. In the embodiment, a mode of crossing strip lines is utilized, and the junction size of the Josephson junction is further reduced by carrying out twice over-etching. As shown in fig. 4 and 6, the first over-etching on the second superconducting layer 400 can be understood as an over-etching in the horizontal direction, and the second over-etching on the second superconducting layer 400 can be understood as an over-etching in the vertical direction, so that the second superconducting layer 400 can be over-etched from two vertical directions to reduce the size of the formed josephson junction 700.

As can be seen from the SEM image shown in FIG. 7, the size of the junction region at the overlapping position of the two strip lines can reach 575nm × 384nm, which is smaller than the lithographic precision (700 nm) of the used equipment, so that the junction area with smaller size can be realized, and the precision limit of the lithographic equipment can be even broken through. Therefore, based on the method, the cost of process equipment can be reduced, and a feasible technical scheme is provided for the preparation of the submicron Josephson junction and even the deep submicron Josephson junction.

The present embodiment also provides a method of manufacturing a superconducting electronic device, which includes manufacturing a josephson junction using the above method of manufacturing a josephson junction, thereby manufacturing a superconducting electronic device based on the josephson junction.

In particular, reference is made to the above description for the preparation of said josephson junctions, which is not described in detail herein.

As an example, the superconducting electronic device may be a superconducting quantum interference device (SQUID), and of course, the superconducting electronic device may also be other superconducting electronic devices based on a josephson junction, wherein, when the superconducting electronic device is a SQUID, it is preferable that a step of forming a passivation layer (not shown) covering the insulating protection layer 500 is further included after 500 after the insulating protection layer is formed, and the step of preparing the passivation layer may be performed after a resistive layer (not shown) of the superconducting quantum interference device is formed, so that the insulating protection of the edge region of the predefined position may be further improved based on the passivation layer, and meanwhile, the passivation layer may be prepared after the resistive layer is placed in the manufacturing process of the SQUID, and may also have an effect of electrically isolating the resistor from a subsequent metal layer. The passivation layer may include, for example, one or a combination of a silicon oxide layer, a silicon dioxide layer, and a silicon nitride layer, which is not limited herein. The particular type of superconducting electronic device and other related components are not overly limited herein and may be selected and fabricated in accordance with known techniques.

In summary, according to the methods for manufacturing a josephson junction and a superconducting electronic device of the present invention, after the josephson junction is predefined, the first superconducting stripe line can be formed by performing the first over-etching on the second superconducting layer, and the insulating protective layer is directly grown and peeled off, and then the third superconducting layer is manufactured, and the second superconducting stripe line is etched, and at the same time, the second superconducting layer, i.e., the first superconducting stripe line, is subjected to the second over-etching, so that the method for manufacturing a josephson junction in submicron or deep submicron scale can be provided through the double over-etching process, and the accuracy limitation of the existing process equipment can be solved, thereby reducing the cost of the process equipment, and the method is suitable for reliably manufacturing a high-performance practical superconducting quantum interference device and other superconducting electronic devices based on the josephson junction.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (10)

1. A method of making a josephson junction comprising the steps of:

providing a substrate;

forming a first superconducting layer, an insulating barrier layer and a second superconducting layer stacked from bottom to top on the substrate, wherein the first superconducting layer has a first thickness, the second superconducting layer has a second thickness, and the first thickness is greater than the second thickness;

etching the second superconducting layer and the insulating barrier layer to expose part of the first superconducting layer;

etching the exposed first superconducting layer to form a lower layer extraction electrode, and etching the second superconducting layer to form a first superconducting strip line on the insulating barrier layer;

forming an insulating protection layer, wherein the insulating protection layer covers the insulating barrier layer and exposes the surface of the first superconducting strip line and the surface of the lower-layer extraction electrode;

forming a third superconducting layer on the first superconducting strip line;

and etching the third superconducting layer to form a second superconducting strip line and an upper layer extraction electrode, and simultaneously etching the first superconducting strip line to expose the insulating barrier layer, wherein the second superconducting strip line is crossed with the first superconducting strip line.

2. A method of preparing a josephson junction according to claim 1, wherein: the ratio of the thickness of the second superconducting layer to the thickness of the first superconducting layer ranges from 1.

3. A method of preparing a josephson junction according to claim 1, wherein: the thickness of the first superconducting layer is 100 nm-200 nm, and the thickness of the second superconducting layer is 50 nm-100 nm.

4. A method of preparing a josephson junction according to claim 1, wherein: the second superconducting strip line is formed perpendicular to the first superconducting strip line.

5. A method of preparing a josephson junction according to claim 1, wherein: the size range of the formed Josephson junction is 300 nm-600 nm.

6. The method of making a josephson junction according to claim 1, wherein: the insulating protective layer comprises one or a combination of a silicon oxide layer, a silicon dioxide layer and a silicon nitride layer.

7. A method of preparing a josephson junction according to claim 1, wherein: the substrate comprises one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate and a silicon carbide substrate; the substrate comprises a wafer level substrate.

8. A method of preparing a josephson junction according to claim 1, wherein: the first superconducting layer comprises at least one of a niobium nitride layer and a niobium layer; the second superconducting layer comprises at least one of a niobium nitride layer and a niobium layer; the third superconducting layer comprises at least one of a niobium nitride layer and a niobium layer; the insulating barrier layer includes at least one of an aluminum layer, an aluminum oxide layer, and an aluminum nitride layer.

9. A method for manufacturing a superconducting electronic device, comprising: a method of manufacturing the superconducting electronic device comprising manufacturing a josephson junction using the method of manufacturing a josephson junction according to any one of claims 1 to 8.

10. A method of manufacturing a superconducting electronic device according to claim 9, characterized in that: the superconducting electronic device is a superconducting quantum interference device, the step of forming a passivation layer covering the insulating protection layer is further included after the insulating protection layer is formed, and the step of preparing the passivation layer is performed after the resistive layer of the superconducting quantum interference device is formed.

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