CN115835642A - Three-dimensional memory device and method of fabricating the same - Google Patents

Abstract

The invention discloses a three-dimensional memory device, which comprises a substrate, a stacked structure arranged on the substrate, and a memory string structure penetrating through the stacked structure. The stacked structure includes a plurality of conductive layers and a plurality of dielectric layers alternately arranged. The memory string structure comprises a conductive pillar and a memory layer which is arranged between the conductive pillar and the stacked structure and surrounds the conductive pillar, wherein the memory layer comprises a plurality of first bulges which are respectively filled in a plurality of first recesses at the junction of the conductive layer and the dielectric layer, so that the electrical isolation between memory cells can be improved, and the signal interference problem between adjacent memory cells during writing or reading is reduced.

Description

Three-dimensional memory device and method of fabricating the same

Technical Field

The present invention relates to semiconductor devices, and more particularly, to a three-dimensional memory device and a method for fabricating the same.

Background

In modern electronic products, memories play an indispensable and important role. The memory is used for storing user's data and storing program codes executed by the CPU and information to be temporarily stored during operation. Memories typically include an array of memory cells (memory array) and peripheral circuits (peripheral circuits) for reading (read), sensing (sense), writing (write) or programming (program) the information of the memory cells. The memory cell of a binary system has two logic states, representing a logic 1 and a logic 0. Other memory system memory cells may include more logic states.

The currently developed memory classes can be classified into volatile memory (volatile memory) and non-volatile memory (non-volatile memory). Common volatile memories include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), which disappear when power is turned off and must be re-entered when power is next applied. Non-volatile memories include Read Only Memories (ROMs) and flash memories (flash memories), which store data that is still present even when power is cut off, and thus may directly read valid data stored earlier after power is re-supplied. In order to meet the specification requirements of various advanced electronic products in terms of area efficiency, read/write speed, reliability, power consumption, manufacturing cost, and the like, the art continues to improve the structure and manufacturing method of the memory.

Disclosure of Invention

The invention aims to provide a three-dimensional memory device and a manufacturing method thereof, wherein memory cells are vertically arranged on a substrate in a mode of being connected in series into a memory string structure, and the area efficiency of the memory device can be improved. In addition, the memory layer is filled into the recess of the side wall of the through hole to form the convex parts on the upper side and the lower side of the memory unit, so that the electrical isolation between the memory units can be improved, and the signal interference problem between the adjacent memory units during writing or reading is reduced.

An embodiment of the invention provides a three-dimensional memory device, which comprises a substrate, a stacked structure arranged on the substrate, and a memory string structure penetrating through the stacked structure. The stacked structure includes a plurality of conductive layers and a plurality of dielectric layers alternately arranged. The memory string structure includes a conductive pillar and a memory layer disposed between the conductive pillar and the stacked structure and surrounding the conductive pillar, wherein the memory layer includes a plurality of first protrusions respectively filling a plurality of first recesses at an interface between the conductive layer and the dielectric layer.

Another embodiment of the present invention provides a method of manufacturing a three-dimensional memory device, including the following steps. Firstly, a substrate is provided, and a stacked structure including a plurality of conductive layers and a plurality of dielectric layers which are alternately arranged is formed on the substrate. Then, an etching process is carried out to form a through hole penetrating through the stacking structure, and a plurality of first recesses are formed on the side wall of the through hole and are respectively positioned at the boundary of the conducting layer and the dielectric layer. Then, a memory layer is formed, covering along the sidewall of the stacked structure, and filling the first recess. And finally, forming a conductive column to fill the through hole.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These drawings and description are included to explain the principles of some embodiments. It should be noted that all the drawings are schematic drawings, and the relative sizes and proportions are adjusted for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 7 are schematic views illustrating steps of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention, in which fig. 3 is a partially enlarged view of the structure shown in fig. 2, and fig. 7 is a partially enlarged view of the structure shown in fig. 6.

Fig. 8 is a partial perspective view of the three-dimensional memory device shown in fig. 6.

Wherein the reference numerals are as follows:

12. stacking structure

100. Substrate

103. Contact pad

110. Cushion layer

112. Metal oxide layer

114. Silicon oxide layer

120. Conductive-dielectric layer pair

122. Interface layer

124. Conductive layer

126. Dielectric layer

132. First recess

134. Second recess

140. Storage layer

142. First projecting part

144. Second projecting part

150. Conductive pole

152. Barrier layer

154. Conductive material

103a surface

124a corner

124b base angle

D1 Depth of field

D2 Depth of

E1 Etching process

E2 Etching process

MC memory cell

MCL memory string structure

OP through hole

SW sidewall

Thickness of T1

Thickness of T2

Thickness of T3

T4 thickness

T5 thickness

TL tangent line

Width of W1

Width of W2

Width W3

Width of W4

Width of W5

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, several preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Those skilled in the art to which the invention relates will appreciate that the features of the various embodiments can be interchanged, recombined, mixed and modified to achieve other embodiments without departing from the spirit of the invention as defined by the appended claims.

Fig. 1 to 7 are schematic views illustrating steps of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. First, as shown in fig. 1, a substrate 100 is provided, a pad layer 110 is formed on the substrate 100, and then a stacked structure 12 including alternately stacked conductive layers 124 and dielectric layers 126 is formed on the pad layer 110.

The substrate 100 may include a semiconductor substrate and circuit elements and interconnect structures that have been fabricated on the semiconductor substrate by semiconductor processes. The semiconductor substrate may be a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The circuit elements may include active or passive elements such as transistors, diodes, resistors, capacitors, but are not limited thereto. The interconnect structure may include an interlevel dielectric layer and conductive structures, such as metal interconnects, contact plugs, and conductive pads, disposed in the interlevel dielectric layer. In some embodiments, as shown in fig. 1, a surface of the substrate 100 may be provided with a plurality of contact pads 103 separated from each other for electrically connecting circuit elements of the substrate 100 with elements (e.g., the memory string structure MCL shown in fig. 6) subsequently fabricated on the substrate 100. The contact pad 103 may include a conductive material, such as a metal, e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), etc., or a compound, alloy, and/or composite layer thereof, but is not limited thereto. According to an embodiment of the present invention, the contact pad 103 mainly comprises tungsten (W).

The liner layer 110 may be formed of a single layer or multiple layers of dielectric material, and suitable dielectric materials may include silicon oxide (SiO) ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high dielectric constant (high-k) dielectric materials such as hafnium oxide (HfO) ₂ ) Hafnium silicon oxide (HfSiO) ₄ ) Hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO) zinc oxide (ZrO) ₂ ) Titanium oxide (TiO) ₂ ) Such as metal oxide dielectrics, or combinations of the above materials, but is not limited thereto. According to an embodiment of the present invention, as shown in fig. 1, the pad layer 110 includes a multi-layer structure, which is composed of a metal oxide layer 112 (e.g., alumina) and a silicon oxide layer 114, wherein the metal oxide layer 112 is preferably located at the lower layer and covers the surface of the contact pad 103. In other embodiments, the pad layer 110 may be composed of a single metal oxide layer.

Each conductive layer 124 of the stacked structure 12 and the dielectric layer 126 thereon together form a conductive-dielectric layer pair 120. The number of conductive-dielectric layer pairs 120 included in the whole stacked structure 12 may be adjusted according to design requirements, and may include, for example, 5 to 10 conductive-dielectric layer pairs 120, but is not limited thereto. The conductive layer 124 includes a conductive material, such as a metal or a non-metal conductive material, e.g., aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W), titanium and titanium nitride (Ti/TiN), polysilicon (poly silicon), doped silicon (silicon), silicide (silicon), or any combination thereof, but is not limited thereto. According to an embodiment of the invention, the material of the conductive layer 124 includes tungsten (W). The dielectric layer 126 comprises a dielectric material, such as silicon oxide (SiO) ₂ ) Dielectric materials such as silicon nitride (SiN), silicon oxynitride (SiON), or any combination thereof, but not limited thereto. In accordance with an embodiment of the present invention,the material of the dielectric layer 126 includes silicon oxide (SiO) ₂ ). In some embodiments, the conductive layers 124 on the upper layer of the stacked structure 12 may have a thicker thickness, for example, referring to fig. 1, the conductive layers 124 on the uppermost layer to the lowermost layer have thicknesses T5, T4, T3, T2 and T1, respectively, and T5>T4>T3>T2>T1。

The pad layer 110 and the conductive layer 124 and the dielectric layer 126 of the stacked structure 12 are formed by a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, or any other suitable deposition process. In some embodiments, the formation of each conductive layer 124 may include forming an interface layer 122 on the surface of the dielectric layer 126, and then forming the conductive layer 124 thereon using the interface layer 122 as a seed layer. The interfacial layer 122 may help to adjust the microstructure (e.g., crystalline state and grain size) of the conductive layer 124 to achieve a desired resistivity. In some embodiments, the interface layer 122 also functions as a diffusion barrier layer to prevent reaction gases used in the deposition of the conductive layer 124 from diffusing into the dielectric layer 126 and affecting product reliability. The material of the interface layer 122 may include, but is not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium Tungsten (TiW), titanium silicon (TiSi), tungsten nitride (WN), tungsten silicide (WSi), tungsten silicide nitride (WSiN), tungsten carbide nitride (WCN), or a combination thereof. According to an embodiment of the present invention, the material of the interface layer 122 may include tungsten silicide (WSi).

Please refer to fig. 2 and fig. 3. Next, an etching process E1, such as plasma etching or Reactive Ion Etching (RIE), is performed on the stacked structure 12 to form a plurality of vias OP aligned with the contact pads 103 and penetrating through the stacked structure 12. In some embodiments, the bottom of the via OP may pass through the pad layer 110 and expose the contact pad 103. In other embodiments, the pad layer 110 may serve as an etch stop layer for the etching process E1, such that the bottom of the via OP is stopped in the pad layer 110 (e.g., stopped on the metal oxide layer 112) without exposing the contact pad 103, and then another etching process (e.g., the etching process E2 of fig. 5) is performed to remove the pad layer 110 remaining at the bottom of the via OP to expose the contact pad 103. The shape of the through hole OP may be substantially a circular hole (refer to fig. 8), but is not limited thereto. In some embodiments, the through hole OP may have a tapered size, such as a tapered diameter, from top to bottom. For example, as shown in fig. 2, the tangent line TL is a tangent line substantially cutting through a portion of the conductive layer 124 exposed from the sidewall SW of the via OP, and may have a slope with respect to the surface of the substrate 100 rather than being perpendicular to the surface of the substrate 100. The width of the portion of the via OP penetrating through each conductive layer 124 is W5, W4, W3, W2, and W1 from top to bottom, and W5> W4> W3> W2> W1.

It is noted that the present invention can adjust the etching process E1 or perform a wet etching process after the etching process E1 to generate a more significant lateral etching at the boundary of different material layers of the sidewall SW of the via hole OP, so as to form a plurality of first recesses 132 and second recesses 134 on the sidewall SW, wherein the first recesses 132 are located at the respective boundaries of the conductive layer 124 and the dielectric layer 126, and the second recesses 134 are located between the bottom surface of the conductive layer 124, the dielectric layer 126 and the interface layer 122. In some embodiments, the second recess 134 is deeper in the stacked structure 12 than the first recess 132 because a portion of the interface layer 122 is more easily removed by lateral etching. For example, as shown in fig. 3, if the tangent line TL is used as a reference line for measuring the recess depth, the first recess 132 may have a depth D1, the second recess 134 has a depth D2, and the depth D2 may be greater than or equal to the depth D1. The top corner 124a of the conductive layer 124 exposed from the first recess 132 and the bottom corner 124b exposed from the second recess 134 may have rounded profiles, respectively.

Please refer to fig. 4. Next, a deposition process, such as any suitable deposition process, e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, etc., is performed to form a storage layer 140 covering the sidewalls SW and the bottom surface of the stacked structure 12 and the via OP, and filling the first recess 132 and the second recess 134. As shown in fig. 4, if the contact pad 103 is exposed from the bottom of the via OP after the etching process E1, the memory layer 140 is in direct contact with the contact pad 103.

The material of the memory layer 140 is selected according to the kind of the memory device, and may include a single layer or a multi-layer structure. In some embodiments, the storage layer 140 may comprise a dielectric material, such as silicon oxide (SiO) ₂ ) Silicon nitride (SiN), nitrogenSilicon oxide (SiON), silicon carbide nitride (SiCN), high dielectric constant (high-k) dielectric materials such as hafnium oxide (HfO) ₂ ) Hafnium silicon oxide (HfSiO) ₄ ) Hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO) zinc oxide (ZrO) ₂ ) Titanium oxide (TiO) ₂ ) Or a combination of the foregoing, but is not limited thereto. According to an embodiment of the present invention, the memory utilizes the memory layer 140 as a charge storage layer for storing data, and the memory layer 140 may comprise a high dielectric constant dielectric or an ONO composite layer composed of silicon oxide-silicon nitride-silicon oxide. In other embodiments of the present invention, if applied to a Phase Change Memory (PCM), the storage layer 140 may include a phase change material such as a chalcogenide alloy (chalcogenide alloy). If applied to a variable resistance RAM (ReRAM), the memory layer 140 may include a variable resistance material such as a transition metal oxide (TMD).

Please refer to fig. 5. Next, an etching process E2, such as plasma etching or Reactive Ion Etching (RIE), is performed to remove the memory layer 140 covering the surface of the stacked structure 12 and the bottom of the via OP, exposing the surface 103a of the contact pad 103.

Please refer to fig. 6 and fig. 7 and 8. Next, a deposition process, such as any suitable deposition process, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, etc., is performed to form a barrier layer 152 conformal to the memory layer 140 and the surface 103a of the contact pad 103 on the sidewall SW of the via OP, and then a conductive material 154 is formed to fill the via OP. Next, an etching process or a polishing removal process is performed to remove the excess barrier layer 152 and the conductive material 154 outside the via OP, so as to obtain the conductive pillars 150 respectively filled in the via OP. The material of the barrier layer 152 may include, but is not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium Tungsten (TiW), titanium silicon (TiSi), tungsten nitride (WN), tungsten silicide (WSi), tungsten silicide nitride (WSiN), tungsten carbide nitride (WCN), or a combination thereof. According to an embodiment of the present invention, the material of the barrier layer 152 may include titanium nitride (TiN). The conductive material 154 may include a metal or non-metal conductive material such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W), titanium and titanium nitride (Ti/TiN), polysilicon (poly silicon), doped silicon (polysilicon), silicide (silicide), or any combination thereof, but is not limited thereto. According to an embodiment of the present invention, the conductive material 154 includes tungsten (W). In other embodiments of the present invention, if applied to a NAND memory, conductive pillars 150 may comprise a semiconductor material, such as polysilicon.

Please continue to refer to fig. 6 and fig. 7 and 8. At this point, the three-dimensional memory device of the present invention is obtained, which includes a substrate 100, a contact pad 103 disposed in the substrate 100 and exposed from a surface of the substrate 100, a stacked structure 12 disposed on the substrate 100 and including a plurality of conductive layers 124 and a plurality of dielectric layers 126 alternately disposed, and a memory string structure (memory column) MCL vertically penetrating the stacked structure 12 and directly contacting the contact pad 103. As shown in fig. 6, the memory string structure MCL includes conductive pillars 150 and a memory layer 140, wherein the memory layer 140 is located between the conductive pillars 150 and the stacked structure 12 and surrounds the conductive pillars 150. The memory string structure MCL may have a size that is tapered from top to bottom, and the width of the top (away from the substrate 100) is greater than the width of the bottom (near the substrate 100). The portion of the memory layer 140 sandwiched between the conductive layer 124 and the conductive pillar 150 (e.g., the portion indicated by the dotted line in fig. 7) is a memory cell MC. The electric field applied to the memory cell MC by the conductive layer 124 and the conductive pillar 150 can switch the state of the memory cell MC (e.g., between charge/discharge states, or between high resistance/low resistance states) for the purpose of storing data. By forming the first recess 132 and the second recess 134 in the sidewall SW of the through hole OP, the subsequently formed memory layer 140 fills the first recess 132 and the second recess 134, thereby obtaining the first protrusion 142 and the second protrusion 144 respectively located on the upper side and the lower side of the memory cell MC. In some embodiments, as shown in fig. 8, memory cell MC, first protrusion 142, and second protrusion 144 may each be a closed ring structure surrounding conductive pillar 150. The first protruding portion 142 and the second protruding portion 144 can improve the electrical isolation between the memory cells MC, and reduce the signal interference between the adjacent memory cells MC during writing or reading. In addition, the top corner 124a and the bottom corner 124b of the conductive layer 124 are rounded by forming the first recess 132 and the second recess 134, so that the top corner 124a and the bottom corner 124b have rounded profiles, respectively, thereby generating a more controllable electric field in the memory layer 140 by the conductive layer 124, reducing the damage defects of the memory layer 140, and further improving the device reliability.

In summary, the memory cells of the three-dimensional memory device of the present invention are vertically disposed on the substrate in a manner of being serially connected into a memory string structure, which can improve the area efficiency of the memory device. In addition, before the memory string structure is formed in the through hole, a recess is formed at the boundary of the conducting layer and the dielectric layer exposed from the side wall of the through hole, so that the memory layer is filled in the recess, and a convex part is formed between the memory units, thereby improving the electrical isolation between the memory units and reducing the signal interference problem between the adjacent memory units during writing or reading.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (20)

1. A three-dimensional memory device, comprising:

a substrate;

a stacked structure disposed on the substrate, including a plurality of conductive layers and a plurality of dielectric layers alternately disposed; and

a memory string structure extending through the stacked structure and comprising:

a conductive post; and

a memory layer interposed between and surrounding the conductive pillars and the stacked structure, wherein the memory layer includes a plurality of first protrusions respectively filling a plurality of first recesses at an interface between the conductive layer and the dielectric layer.

2. The three-dimensional memory device of claim 1, wherein the stacked structure further comprises a plurality of interface layers respectively located between the bottom surface of the conductive layer and the dielectric layer.

3. The three-dimensional memory device of claim 2, wherein the memory layer further comprises a plurality of second protrusions respectively filling a plurality of second recesses between the conductive layer, the dielectric layer, and the interface layer, wherein the depth of the second recesses is greater than the depth of the first recesses.

4. The three-dimensional memory device of claim 2, wherein the material of the conductive layer and the conductive pillar comprises tungsten, the material of the interfacial layer comprises tungsten silicide, and the material of the dielectric layer comprises silicon oxide.

5. The three-dimensional memory device of claim 1, further comprising:

a contact pad disposed in the substrate; and

a pad layer disposed between the stack structure and the substrate, wherein the memory string structure passes through the pad layer and directly contacts the contact pad.

6. The three-dimensional memory device of claim 5, wherein the liner layer comprises a metal oxide layer.

7. The three-dimensional memory device of claim 1, wherein the memory layer comprises a high dielectric constant dielectric.

8. The three-dimensional memory device of claim 1, wherein the portion of the conductive layer in contact with the first protrusion comprises a rounded profile.

9. The three-dimensional memory device of claim 1, wherein a top width of the memory string structure is greater than a bottom width.

10. The three-dimensional memory device of claim 1, wherein the thickness of the upper one of the plurality of conductive layers is thicker.

11. A method of fabricating a three-dimensional memory device, comprising:

providing a substrate;

forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of conducting layers and a plurality of dielectric layers which are alternately arranged;

performing an etching process to form a through hole penetrating through the stacked structure, and forming a plurality of first recesses on the side wall of the through hole, wherein the first recesses are respectively positioned at the junctions of the conductive layer and the dielectric layer;

forming a memory layer covering along the sidewall of the stacked structure and filling the first recess; and

and forming a conductive column to fill the through hole.

12. The method of claim 11, wherein the stacked structure further comprises a plurality of interface layers respectively located between the bottom surface of the conductive layer and the dielectric layer.

13. The method of claim 12, further comprising forming a plurality of second recesses in the sidewalls of the via by the etching process, between the conductive layer, the dielectric layer, and the interface layer, respectively, wherein a depth of the second recesses is greater than a depth of the first recesses.

14. The method of claim 12, wherein the conductive layer and the conductive pillars comprise tungsten, the interface layer comprises tungsten silicide, and the dielectric layer comprises silicon oxide.

15. The method of fabricating a three-dimensional memory device according to claim 11, further comprising, prior to forming the stacked structure:

forming a contact pad embedded in the substrate; and

a liner layer is formed on the substrate and covers the contact pad, wherein the via penetrates through the liner layer and exposes a surface of the contact pad.

16. The method of claim 15, wherein the liner layer comprises a metal oxide layer.

17. The method of fabricating a three-dimensional memory device of claim 11, wherein the memory layer comprises a high dielectric constant dielectric.

18. The method of claim 11, wherein the portion of the conductive layer exposed by the first recess comprises a rounded profile.

19. The method of claim 11, wherein a top width of the via is greater than a bottom width.

20. The method of claim 11, wherein the thickness of the upper layer of the plurality of conductive layers is thicker.

Images