CN115834898B - Transmission method for carrying alpha channel value during HDMI transmission - Google Patents
Transmission method for carrying alpha channel value during HDMI transmission Download PDFInfo
- Publication number
- CN115834898B CN115834898B CN202310153874.XA CN202310153874A CN115834898B CN 115834898 B CN115834898 B CN 115834898B CN 202310153874 A CN202310153874 A CN 202310153874A CN 115834898 B CN115834898 B CN 115834898B
- Authority
- CN
- China
- Prior art keywords
- channel
- bit
- bits
- alpha
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention relates to the technical field of signal transmission, and discloses a transmission method for carrying an alpha channel value in HDMI transmission, wherein data of the alpha channel value is replaced with partial component data in a video stream transmitted by HDMI in a pixel coding mode of Y\Cb\Cr4:2:2, and the total bit number after replacement and the pre-replacement bit number are kept consistent. The invention solves the problems that the alpha channel value cannot be transmitted in the Y/Cb/Cr4:2:2 transmission mode in the prior art.
Description
Technical Field
The invention relates to the technical field of signal transmission, in particular to a transmission method for carrying an alpha channel value during HDMI transmission.
Background
HDMI transmits video, audio, and control data mainly through three TMD channels 0, 1, and 2.
HDMI, when transmitting video, has three Pixel encodings: R\G\B4:4, Y\Cb\Cr4:2:2, Y\Cb\Cr4:4:4. The mode of Y\Cb\Cr4:2:2 data transmission in the conventional HDMI is shown in FIG. 1.
Each TMDS channel 8bits, transmitted in Y, cb, Y, cr, Y … order, Y/Cb/Cr 4:2Y 12bits and C12 bits, and it can be seen from FIG. 1 that the 0-3 bits of TMDS0 channel transmit the 0-3 bits of Y, the 4-7 bits of TMDS0 channel transmit the 0-3 bits of C, the 0-7 bits of TMDS1 channel transmit the 4-11 bits of Y, and the 0-7 bits of TMDS2 channel transmit the 4-11 bits of C.
The prior art has the problem that an Alpha channel value (namely an Alpha channel value) cannot be transmitted in a HDMY\Cb\Cr4:2 transmission mode.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a transmission method for carrying an alpha channel value during HDMI transmission, which solves the problems that the alpha channel value cannot be transmitted in a Y\Cb\Cr4:2:2 transmission mode in the prior art.
The invention solves the problems by adopting the following technical scheme:
a transmission method for carrying an alpha channel value in HDMI transmission is characterized in that under a pixel coding mode of Y\Cb\Cr4:2:2, partial component data in a video stream transmitted by HDMI is replaced by data of the alpha channel value, and the total bit number after replacement and the bit number before replacement are kept consistent.
As a preferable technical scheme, the video stream of each TMDS channel occupies 8bits, the video streams of three TMDS channels occupy 24bits, and the data of the alpha channel value is used for replacing part of the data of the Y component and the C component in the video stream; wherein, the three TMDS channels are respectively named as TMDS0 channel, TMDS1 channel and TMDS2 channel, and C represents Cb or Cr.
As a preferable technical scheme, 8-bit data of an alpha channel value is used for replacing 0-3 bits of Y and 0-3 bits of C in a video stream to form a Y\Cb\Cr\alpha 4:2:2:4 video stream.
As a preferred technical solution, in the 1 st 24-bit video stream:
0-3 bit transfer Y for TMDS0 channel i In the range of 0 to 3 bits of the formula,
4-7 bit transfer Cb for TMDS0 channel p In the range of 0 to 3 bits of the formula,
0-3 bit transfer Y for TMDS1 channel i In the order of 4-7 bits of the sequence,
4-7 bit transfer Cb for TMDS1 channel p In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel i 0-7 of (C);
in the 2 nd 24-bit video stream:
0-3 bit transfer Y for TMDS0 channel i+1 In the range of 0 to 3 bits of the formula,
4-7 bit transmission Cr of TMDS0 channel p In the range of 0 to 3 bits of the formula,
0-3 bit transfer Y for TMDS1 channel i+1 In the order of 4-7 bits of the sequence,
4-7 bit transmission Cr of TMDS1 channel p In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel i+1 0-7 of (C);
where f denotes the number of the video stream, i denotes the number of the alpha channel value, alpha i Represents the ith alpha channel value, Y i Represents the ith Y component, cb p Represents the p-th Cb component, cr p Representing the p-th Cr component, wherein i and p are both more than or equal to 0 and are integers, and f is more than or equal to 1 and is an integer; i. the initial value of p is 0 and the initial value of f is 1.
As a preferred solution, when i=i+1,
，
。
as a preferable technical scheme, 8-bit data of an alpha channel value is used for replacing 0-3 bits of Y and 0-3 bits of C in a video stream to form a Y\CbCr\alpha 4:4:4 video stream.
As a preferable technical scheme, 8-bit data of an alpha channel value is used for replacing 0-3 bits of Y and 0-3 bits of C in a video stream, and Cb and Cr are put into the same channel to form a Y\CbCr\alpha 4:4:4 video stream.
As a preferred technical solution, in the 1 st 24-bit video stream:
0-7 bit transfer Y for TMDS0 channel i In the range of 0 to 7 bits of the formula,
0-3 bit transfer Cb of TMDS1 channel p In the range of 0 to 3 bits of the formula,
4-7 bit transmission Cr of TMDS1 channel p In the range of 0 to 3 bits of the formula,
0-7 bit transmission alpha of TMDS2 channel i 0-7 of (C);
in the 2 nd 24 th bit data transmission,
0-7 bit transfer Y for TMDS0 channel i+1 In the range of 0 to 7 bits of the formula,
0-3 bit transfer Cb of TMDS1 channel p In the order of 4-7 bits of the sequence,
4-7 bit transmission Cr of TMDS1 channel p In the order of 4-7 bits of the sequence,
TM0-7 bit transmission alpha of DS2 channel i+1 0-7 of (C);
where f denotes the number of the video stream, i denotes the number of the alpha channel value, alpha i Represents the ith alpha channel value, Y i Represents the ith Y component, cb p Represents the p-th Cb component, cr p Representing the p-th Cr component, wherein i and p are both more than or equal to 0 and are integers, and f is more than or equal to 1 and is an integer; i. the initial value of p is 0 and the initial value of f is 1.
As a preferred solution, when i=i+1,
，
。
compared with the prior art, the invention has the following beneficial effects:
(1) In the HDMIY\Cb\Cr4:2:2 transmission mode, the method of the invention obtains YCbCr+alpha channel value by adjusting the occupied bits of each component (discarding 0-3 bit of original Y and C, changing from 12bits to 8 bits) and adding 8bits of alpha channel value to form Y\Cb\Cr\alpha 4:2:2:4, but keeping the total bit number and original Cb and Cr consistent (still 24 bits) according to each 24bits staggered transmission;
(2) Under the condition of Y\Cb\Cr4:2:2, the method of the invention obtains the YCbCr+alpha channel value by adjusting the occupied bits of each component (discarding 0-3 bits of original Y and C, changing from 12bits to 8 bits), putting Cb and Cr into the same channel and adding 8bits of alpha channel value to form Y\CbCr\alpha 4:4:4, wherein the total bits and the original Cb and Cr are kept consistent (still 24 bits) and are not transmitted in a staggered way according to each 24 bits;
(3) The storage modes of Y, cb, cr and alpha data in the TMDS channel are pointed out in the method.
Drawings
FIG. 1 is a schematic diagram of a prior art transmission in a Y\Cb\Cr4:2:2 pixel coding mode;
fig. 2 is a transmission schematic diagram of a transmission method for carrying an α -channel value during HDMI transmission in embodiment 1;
fig. 3 is a transmission diagram of a transmission method for carrying an α -channel value during HDMI transmission in embodiment 2.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but embodiments of the present invention are not limited thereto.
Example 1
As shown in fig. 1 to 3, transmission scheme 1 is as follows:
TMDS 8bits per lane, passed in the order Y, cb, α, Y, cr, α, Y ….
In the 1 st 24-bit video stream:
0-3 bit transfer Y for TMDS0 channel 0 In the range of 0 to 3 bits of the formula,
4-7 bit transfer Cb for TMDS0 channel 0 In the range of 0 to 3 bits of the formula,
0-3 bit transfer Y for TMDS1 channel 0 In the order of 4-7 bits of the sequence,
4-7 bit transfer Cb for TMDS1 channel 0 In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel 0 0-7 of (C);
in the 2 nd 24-bit video stream:
0-3 bit transfer Y for TMDS0 channel 1 In the range of 0 to 3 bits of the formula,
4-7 bit transmission Cr of TMDS0 channel 0 In the range of 0 to 3 bits of the formula,
0-3 bit transfer Y for TMDS1 channel 1 In the order of 4-7 bits of the sequence,
4-7 bit transmission Cr of TMDS1 channel 0 In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel 1 0-7 of (C);
the 24bits of the three channels sequentially comprise Y, cb, alpha/Y, cr and alpha three types of data, and after each 48bits, the subscripts of Cb and Cr are added by 2, as shown in figure 2.
The method is equivalent to that under the condition of Y\Cb\Cr4:2:2, 8bits of an alpha channel value are added by adjusting the occupied bits of each component (discarding 0-3 bits of original Y and C and changing from 12bits to 8 bits), so that Y\Cb\Cr\alpha 4:2:2:4 is formed, but the total bit number and the original Cb and Cr are kept consistent (still 24 bits) and are transmitted in a staggered way according to each 24 bits.
Further, the above scheme is further expanded as follows:
in the 1 st 24-bit video stream:
0-3 bit transfer Y for TMDS0 channel i In the range of 0 to 3 bits of the formula,
4-7 bit transfer Cb for TMDS0 channel p In the range of 0 to 3 bits of the formula,
0-3 bit transfer Y for TMDS1 channel i In the order of 4-7 bits of the sequence,
4-7 bit transfer Cb for TMDS1 channel p In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel i 0-7 of (C);
in the 2 nd 24-bit video stream:
0-3 bit transfer Y for TMDS0 channel i+1 In the range of 0 to 3 bits of the formula,
4-7 bit transmission Cr of TMDS0 channel p In the range of 0 to 3 bits of the formula,
0-3 bit transfer Y for TMDS1 channel i+1 In the order of 4-7 bits of the sequence,
4-7 bit transmission Cr of TMDS1 channel p In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel i+1 0-7 of (C);
where f denotes the number of the video stream, i denotes the number of the alpha channel value, alpha i Represents the ith alpha channel value, Y i Represents the ith Y component, cb p Represents the p-th Cb component, cr p Representing the p-th Cr component, wherein i and p are both more than or equal to 0 and are integers, and f is more than or equal to 1 and is an integer; i. the initial value of p is 0 and the initial value of f is 1. When i=i+1,
，
。
example 2
As shown in fig. 1 to 3, transmission scheme 2 is as follows:
TMDS 8bits per lane, delivered in the order Y, cb, cr, α, Y ….
In the 1 st 24-bit video stream:
0-7 bit transfer Y for TMDS0 channel 0 In the range of 0 to 7 bits of the formula,
0-3 bit transfer Cb of TMDS1 channel 0 In the range of 0 to 3 bits of the formula,
4-7 bit transmission Cr of TMDS1 channel 0 In the range of 0 to 3 bits of the formula,
0-7 bit transmission alpha of TMDS2 channel 0 0-7 of (C);
in the 2 nd 24 th bit data transmission,
0-7 bit transfer Y for TMDS0 channel 1 In the range of 0 to 7 bits of the formula,
0-3 bit transfer Cb of TMDS1 channel 0 In the order of 4-7 bits of the sequence,
4-7 bit transmission Cr of TMDS1 channel 0 In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel 1 0-7 of (C);
the 24bits of the three channels each time comprise four types of data of Y, cb, cr and alpha, and the subscripts of Cb and Cr are added with 2 after each 48bits, as shown in figure 3.
The method is equivalent to that under the condition of Y\Cb\Cr4:2:2, the occupied bits of each component are regulated, (0-3 bits of original Y and C are discarded, the high 8bits are taken, 12bits are changed into 8 bits), cb and Cr are put into the same channel (TMDS 2), 8bits of an alpha channel value are added, Y\CbCr\alpha 4:4:4 is formed, but the total bit number and the original Cb and Cr are kept consistent (still 24 bits) and are not transmitted in a staggered way according to every 24 bits.
Further, the above scheme is further expanded as follows:
in the 1 st 24-bit video stream:
0-7 bit transfer Y for TMDS0 channel i In the range of 0 to 7 bits of the formula,
0-3 bit transfer Cb of TMDS1 channel p In the range of 0 to 3 bits of the formula,
4-7 bit transmission Cr of TMDS1 channel p In the range of 0 to 3 bits of the formula,
0-7 bit transmission alpha of TMDS2 channel i 0-7 of (C);
in the 2 nd 24 th bit data transmission,
0-7 bit transfer Y for TMDS0 channel i+1 In the range of 0 to 7 bits of the formula,
TMDS1 general0-3 bit transfer Cb of a track p In the order of 4-7 bits of the sequence,
4-7 bit transmission Cr of TMDS1 channel p In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel i+1 0-7 of (C);
where f denotes the number of the video stream, i denotes the number of the alpha channel value, alpha i Represents the ith alpha channel value, Y i Represents the ith Y component, cb p Represents the p-th Cb component, cr p Representing the p-th Cr component, wherein i and p are both more than or equal to 0 and are integers, and f is more than or equal to 1 and is an integer; i. the initial value of p is 0 and the initial value of f is 1. When i=i+1,
，
。/>
to sum up:
the method is an improvement under the mode of HDMI transmission Y\Cb\Cr4:2:2, and supports the transmission of the alpha channel value in HDMI, wherein the maximum upper limit of the data quantity input by each component of Y, cb and Cr is 12 bits. The traditional Y\Cb\Cr4:4 can only take 8bits of data as input generally, when each component is transmitted by 12bits, taking 24bits of single TMS clock as an example, because the data coding in the video stage is serial transmission, after 8bits of each channel are full, the data of high 4bits are discharged into the corresponding channel of the next 24bits, which is equivalent to 3 TMS clocks, can only finish three-component transmission of 2 pixels, (12 (each component bits) ×3 (component) ×2 (two pixels) =24 (three channel bits) ×3 (TMDS clock)), and the method not only carries alpha channel values in the transmission process of each component 12bits, but also can realize the transmission of +2 alpha channel values in the three-component transmission of 2 pixels.
The invention mainly provides two specific methods for carrying Alpha channel values in a mode of HDMIY\Cb\Cr4:2:2.
The invention has the following characteristics:
1. in the HDMIY\Cb\Cr4:2:2 transmission mode, the method of the invention obtains YCbCr+alpha channel value by adjusting the occupied bits of each component (discarding 0-3 bit of original Y and C, changing from 12bits to 8 bits) and adding 8bits of alpha channel value to form Y\Cb\Cr\alpha 4:2:2:4, but keeping the total bit number and original Cb and Cr consistent (still 24 bits) according to each 24bits staggered transmission;
2. under the condition of Y\Cb\Cr4:2:2, the method of the invention obtains the YCbCr+alpha channel value by adjusting the occupied bits of each component (discarding 0-3 bits of original Y and C, changing from 12bits to 8 bits), putting Cb and Cr into the same channel and adding 8bits of alpha channel value to form Y\CbCr\alpha 4:4:4, wherein the total bits and the original Cb and Cr are kept consistent (still 24 bits) and are not transmitted in a staggered way according to each 24 bits;
3. the storage modes of Y, cb, cr and alpha data in the TMDS channel are pointed out in the method.
As described above, the present invention can be preferably implemented.
All of the features disclosed in all of the embodiments of this specification, or all of the steps in any method or process disclosed implicitly, except for the mutually exclusive features and/or steps, may be combined and/or expanded and substituted in any way.
The foregoing description of the preferred embodiment of the invention is not intended to limit the invention in any way, but rather to cover all modifications, equivalents, improvements and alternatives falling within the spirit and principles of the invention.
Claims (1)
1. In the pixel coding mode of YCbCr4:2, replacing partial component data in video stream transmitted by HDMI with data of alpha channel value, and keeping the total bit number and the bit number before replacement consistent after replacement;
the video stream of each TMDS channel occupies 8bits, the video streams of the three TMDS channels occupy 24bits, and partial data of Y component and C component in the video stream are replaced by data of alpha channel value; wherein, the three TMDS channels are respectively marked as TMDS0 channel, TMDS1 channel and TMDS2 channel, and C represents Cb or Cr;
the specific alternative method comprises the following steps:
replacing the 8-bit data of the alpha channel value with the 0-3 bit of Y and the 0-3 bit of C in the video stream to form a YCbCr alpha 4:2:2:4 video stream;
in the 1 st 24-bit video stream:
0-3 bit transfer Y for TMDS0 channel i In the range of 0 to 3 bits of the formula,
4-7 bit transfer Cb for TMDS0 channel p In the range of 0 to 3 bits of the formula,
0-3 bit transfer Y for TMDS1 channel i In the order of 4-7 bits of the sequence,
4-7 bit transfer Cb for TMDS1 channel p In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel i 0-7 of (C);
in the 2 nd 24-bit video stream:
0-3 bit transfer Y for TMDS0 channel i+1 In the range of 0 to 3 bits of the formula,
4-7 bit transmission Cr of TMDS0 channel p In the range of 0 to 3 bits of the formula,
0-3 bit transfer Y for TMDS1 channel i+1 In the order of 4-7 bits of the sequence,
4-7 bit transmission Cr of TMDS1 channel p In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel i+1 0-7 of (C);
where f denotes the number of the video stream, i denotes the number of the alpha channel value, alpha i Represents the ith alpha channel value, Y i Represents the ith Y component, cb p Represents the p-th Cb component, cr p Representing the p-th Cr component, wherein i and p are both more than or equal to 0 and are integers, and f is more than or equal to 1 and is an integer; i. the initial value of p is 0, and the initial value of f is 1;
when i=i+1,
，/>
；
or;
replacing 0-3 bits of Y and 0-3 bits of C in the video stream with 8-bit data of an alpha channel value, and putting Cb and Cr in the same channel to form a YCbCr alpha 4:4:4 video stream;
in the 1 st 24-bit video stream:
0-7 bit transfer Y for TMDS0 channel i In the range of 0 to 7 bits of the formula,
0-3 bit transfer Cb of TMDS1 channel p In the range of 0 to 3 bits of the formula,
4-7 bit transmission Cr of TMDS1 channel p In the range of 0 to 3 bits of the formula,
0-7 bit transmission alpha of TMDS2 channel i 0-7 of (C);
in the 2 nd 24 th bit data transmission,
0-7 bit transfer Y for TMDS0 channel i+1 In the range of 0 to 7 bits of the formula,
0-3 bit transfer Cb of TMDS1 channel p In the order of 4-7 bits of the sequence,
4-7 bit transmission Cr of TMDS1 channel p In the order of 4-7 bits of the sequence,
0-7 bit transmission alpha of TMDS2 channel i+1 0-7 of (C);
where f denotes the number of the video stream, i denotes the number of the alpha channel value, alpha i Represents the ith alpha channel value, Y i Represents the ith Y component, cb p Represents the p-th Cb component, cr p Representing the p-th Cr component, wherein i and p are both more than or equal to 0 and are integers, and f is more than or equal to 1 and is an integer; i. the initial value of p is 0, and the initial value of f is 1;
when i=i+1,
，/>
。/>
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310153874.XA CN115834898B (en) | 2023-02-23 | 2023-02-23 | Transmission method for carrying alpha channel value during HDMI transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310153874.XA CN115834898B (en) | 2023-02-23 | 2023-02-23 | Transmission method for carrying alpha channel value during HDMI transmission |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115834898A CN115834898A (en) | 2023-03-21 |
| CN115834898B true CN115834898B (en) | 2023-05-12 |
Family
ID=85522184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310153874.XA Active CN115834898B (en) | 2023-02-23 | 2023-02-23 | Transmission method for carrying alpha channel value during HDMI transmission |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115834898B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018205878A1 (en) * | 2017-05-11 | 2018-11-15 | 腾讯科技（深圳）有限公司 | Method for transmitting video information, terminal, server and storage medium |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7649539B2 (en) * | 2004-03-10 | 2010-01-19 | Microsoft Corporation | Image formats for video capture, processing and display |
| US8189908B2 (en) * | 2005-09-02 | 2012-05-29 | Adobe Systems, Inc. | System and method for compressing video data and alpha channel data using a single stream |
| RU2013118988A (en) * | 2013-04-24 | 2014-11-10 | Общество С Ограниченной Ответственностью "Э-Студио" | VIDEO STREAM PROCESSING |
| KR102642797B1 (en) * | 2019-01-14 | 2024-03-05 | 삼성전자주식회사 | Electronic apparatus and control method thereof |
| WO2021237569A1 (en) * | 2020-05-28 | 2021-12-02 | 深圳市大疆创新科技有限公司 | Encoding method, decoding method, apparatus and system |
| GB2601504B (en) * | 2020-12-01 | 2023-03-29 | Imagination Tech Ltd | Data compression and packing |
| CN115550624B (en) * | 2022-12-02 | 2023-07-18 | 成都索贝数码科技股份有限公司 | HDMI video data transmission method carrying alpha channel value |
-
2023
- 2023-02-23 CN CN202310153874.XA patent/CN115834898B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018205878A1 (en) * | 2017-05-11 | 2018-11-15 | 腾讯科技（深圳）有限公司 | Method for transmitting video information, terminal, server and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| Single color image super-resolution using sparse representation and color constraint;XU Zhigang;MA Qiang;YUAN Feixiang;;Journal of Systems Engineering and Electronics(第02期);全文 * |
| 多层图像叠加处理的低功耗自适应流水线设计;谭腾飞;马德;黄凯;马琪;;浙江大学学报(工学版)(01);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115834898A (en) | 2023-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10805648B2 (en) | Image transmission device, image transmission method, image reception device, and image reception method | |
| KR100568950B1 (en) | Method and system for reducing inter-symbol interference effects in transmission over a serial link with mapping of each word in a cluster of received words to a single transmitted word | |
| US8378860B2 (en) | Method and system for generating high definition multimedia interface (HDMI) codewords using a TMDS encoder/decoder | |
| US8638285B2 (en) | Image data transfer to cascade-connected display panel drivers | |
| CN1947332A (en) | Method and circuit for adaptive equalization of multiple signals in response to a control signal generated from one of the equalized signals | |
| CN102385844B (en) | Display system and display device driver | |
| US7995696B1 (en) | System and method for deskewing data transmitted through data lanes | |
| JP6008141B2 (en) | Baseband video data transmission device, reception device, and transmission / reception system | |
| DE102013105559A1 (en) | A method of detecting a bit depth and interface device for a display device using the same | |
| US20160205416A1 (en) | Radio frequency interference reduction in multimedia interfaces | |
| KR101199056B1 (en) | Method and Appratus for channel coding and modulation for Unequal Error Protection in transmitting uncompressed video over wideband high frequency wireless system | |
| KR101617325B1 (en) | Display apparatus and method for driving the same | |
| US8854289B2 (en) | Intra-system interface unit of flat panel display | |
| CN115834898B (en) | Transmission method for carrying alpha channel value during HDMI transmission | |
| US20080040765A1 (en) | Bidirectional communication protocol between a serializer and a deserializer | |
| CN115550624B (en) | HDMI video data transmission method carrying alpha channel value | |
| CN106664402A (en) | Caching of capabilities information of counterpart device for efficient handshaking operation | |
| CN101334989A (en) | Image display apparatus | |
| US11252372B2 (en) | Payload mapper and payload mapping method | |
| KR101605181B1 (en) | Method for correction of error code included in control signal of hdmi/mhl | |
| CN116896423A (en) | Transceiver device, display system, and method of driving transceiver device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |