CN115831914A - System-level chip of three-dimensional package - Google Patents

Abstract

The invention relates to an overall structure of a three-dimensional packaged system-level chip. The system-level chip of the three-dimensional package adopts the plastic package body to fix the circuit board assembly, the outer part of the plastic package body can cover 1-6 conductive layers, the conductive layers of a plurality of surfaces can be utilized to respectively lead out the electric signals of the internal circuit board assembly, the internal circuit board assembly is reinforced and fixed, the whole structure of the chip is simple, the hidden danger of easy short circuit of pins is eliminated, and the system-level chip has various advantages of high density, high integration level, high reliability and the like.

Description

System-level chip of three-dimensional package

Technical Field

The invention relates to the field of semiconductor packaging, in particular to a three-dimensional packaged system-level chip.

Background

In the semiconductor field, a conventional bare chip only contains elements such as diodes, triodes, resistors and the like which can only be directly formed on a silicon chip, the realized function is limited, and the application of the bare chip in a system is limited, so that other electronic elements such as inductors, capacitors and the like are required to be equipped in the actual application of the current chip, namely, the electronic elements are installed on a circuit board and a circuit board assembly, namely, the chip is formed, the size of the whole system is directly increased, and the protection safety is weak.

In addition, when the main board is manufactured, a chip needs to be mounted on a substrate, pins are conventionally arranged on the chip, the chip is connected with the substrate through the pins, a pin connection structure is disordered, and particularly under the condition that the number of pins of the chip is large, the whole structure of the main board is more complex, and the pins are easy to contact with each other to cause short-circuit and other faults.

Disclosure of Invention

In view of the above, it is necessary to provide a system on chip for a three-dimensional package to address at least some of the above problems.

A system-on-chip in a three-dimensional package, comprising:

the circuit board assembly comprises a circuit board and an electronic element electrically connected with the circuit board;

the plastic package body is packaged and covered on the circuit board assembly and comprises an upper plastic package surface, a lower plastic package surface and a plastic package side wall, wherein the upper plastic package surface and the lower plastic package surface are spaced from the circuit board, and the plastic package side wall is arranged around the edge of the circuit board;

the edge of circuit board is equipped with at least one electrically conductive position, and the internal conductor of circuit board extends to electrically conductive position and with electrically conductive position contact, electrically conductive position and neighbouring the plastic envelope lateral wall surface covering at electrically conductive position has first conducting layer, first conducting layer is configured to extend to or mould the front cover down, and with laminate in or mould the outside mainboard electricity of front cover down and be connected, in order to realize the internal conductor with electricity between the outside mainboard is connected.

In some embodiments, at least one surface of the upper and lower plastic covers is covered with a second conductive layer, and the internal lead of the circuit board assembly is electrically connected with the second conductive layer; and the edge of the second conducting layer is provided with a first interval area, and the second conducting layer is separated from at least one first conducting layer through the first interval area.

In some embodiments, the first spacer is arc-shaped or fold-shaped and extends around the part where the first conductive layer is connected with the upper plastic sealing surface and/or the lower plastic sealing surface.

In some embodiments, the second conductive layer is in contact with at least one of the first conductive layers to electrically connect to the internal leads of the circuit board through the first conductive layer.

In some embodiments, the plastic-sealed side wall adjacent to the first conductive layer is communicated with the first spacer.

In some embodiments, the conductive portion of the circuit board is recessed to form a conductive groove, the internal lead of the circuit board extends to the bottom of the conductive groove, the leading-out terminal of the internal lead is arranged on the surface of the conductive groove, and the first conductive layer covers the leading-out terminal to realize electrical contact with the leading-out terminal; at least one side edge of the circuit board is provided with two or more conductive parts; .

In some embodiments, the edge of the circuit board and the plastic package side wall arranged around the edge of the circuit board are in a continuous wave shape, and the conductive grooves are formed in the conductive parts respectively.

In some embodiments, the semiconductor device further includes a third conductive layer covering the plastic package sidewall and separated from the first conductive layer by a second spacing region on the plastic package sidewall where no conductive layer is laid.

In some embodiments, at least one of the upper and lower plastic covers a second conductive layer, and the internal leads of the circuit board assembly are electrically connected with the second conductive layer; a first spacer is arranged at the edge of the second conducting layer, and the second conducting layer is separated from the first conducting layer through the first spacer; the third conductive layer is connected to the second conductive layer.

In some embodiments, the second conductive layer is disposed on the upper plastic sealing surface and/or the lower plastic sealing surface at intervals, and the interval part is a third interval region which does not cover the second conductive layer, and the third interval region is connected to two second interval regions on two opposite plastic sealing sidewalls.

The system-on-chip of the three-dimensional package at least has the following beneficial technical effects:

(1) In the embodiment, the circuit board assembly is fixed by adopting the plastic package body, and the double surfaces of the circuit board assembly are sealed into a cuboid, so that the circuit board assembly is positioned in the cuboid, and electronic elements are prevented from being directly exposed;

meanwhile, the internal lead of the circuit board is led out through the first conducting layer and is electrically connected with the external mainboard, so that the internal lead horizontally arranged in the circuit board is vertically led out and is in contact with the external mainboard, a pin structure is not required to be arranged, and the phenomena of chip structure disorder, complex connection structure with multiple pins of the mainboard and short circuit among the pins caused by the adoption of the pins are avoided; the whole structure is simple, the hidden trouble of pin short circuit is eliminated, and therefore the system-level chip has high density, high integration level, miniaturization and high reliability while the normal realization of the function is ensured.

(2) The plastic package body can be covered with 1-6 conductive layers, and the electric signals of the internal circuit board assembly can be respectively led out by utilizing the conductive layers on the multiple surfaces. The external conducting layer can shield the internal circuit board assembly, avoid external signal interference and send out signals to interfere external electric devices; the conducting layer can also strengthen heat dissipation and strengthen fixation to the internal circuit board assembly.

Drawings

Fig. 1 is a schematic diagram of a system-on-chip of a three-dimensional package according to an embodiment of the invention;

FIG. 2 isbase:Sub>A sectional view taken along line A-A in FIG. 1;

fig. 3 is a side view of a system-on-chip of a three-dimensional package according to an embodiment of the invention;

fig. 4 is a top view of a circuit board assembly in a system-on-chip of a three-dimensional package according to an embodiment of the invention;

fig. 5 is a schematic structural diagram of a motherboard according to an embodiment of the present invention;

in the figure, 10, chip architecture;

100. a circuit board assembly; 110. a circuit board; 120. an electronic component; 121. a capacitor; 122. a magnetic core; 101. a conductive site; 103. a lead-out terminal;

200. molding the body; 210. a plastic cover is arranged; 220. a plastic cover is arranged; 230. plastic packaging the side wall;

310. a first conductive layer; 320. a second conductive layer; 330. a third conductive layer;

410. a first spacer region; 420. a second spacer region; 430. a third spaced-apart region;

500. a conductive section;

20. an external motherboard.

Detailed Description

The invention will be further described with reference to the accompanying drawings.

To facilitate an understanding of the invention, various embodiments of the invention defined by the claims are described more fully below with reference to the accompanying drawings. While the preferred embodiments of the present invention have been illustrated in the accompanying drawings, and described in detail to facilitate this understanding, such details are to be regarded as illustrative only. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Accordingly, those of ordinary skill in the art will recognize that changes and modifications of the various embodiments described herein can be made without departing from the scope of the invention, which is defined by the appended claims. Moreover, descriptions of well-known functions and constructions may be omitted for clarity and conciseness.

It will be apparent to those skilled in the art that the following descriptions of the various embodiments of the present invention are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims.

Throughout the description and claims of this specification, the words "comprise" and variations of the words, for example "comprising" and "comprises", mean "including but not limited to", and are not intended to (and do not) exclude other components, integers or steps. Features, integers or characteristics described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith.

It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The expression "comprising" and/or "may comprise" as used in the present invention is intended to indicate the presence of corresponding functions, operations or elements, and is not intended to limit the presence of one or more functions, operations and/or elements. Furthermore, in the present invention, the terms "comprises" and/or "comprising" are intended to indicate the presence of the features, amounts, operations, elements, and components disclosed in the specification, or combinations thereof. Thus, the terms "comprising" and/or "having" should be interpreted as presenting additional possibilities for one or more other features, quantities, operations, elements, and components, or combinations thereof.

In the present invention, the expression "or" comprises any and all combinations of the words listed together. For example, "A or B" may comprise A or B, or may comprise both A and B.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present; when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

References herein to "upper", "lower", "left", "right", etc., are merely intended to indicate relative positional relationships, which may change when the absolute position of the object being described changes.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1 to 5, in an embodiment of the present invention, a system on chip of a three-dimensional package is provided, including:

a circuit board assembly 100 including a circuit board 110 and an electronic component 120 electrically connected to the circuit board 110;

the plastic package body 200 is packaged and coated on the circuit board assembly 100, and the plastic package body 200 comprises an upper plastic package surface and a lower plastic package surface which are spaced from the circuit board 110, and a plastic package side wall 230 which is arranged around the edge of the circuit board 110;

the edge of circuit board 110 is equipped with at least one electrically conductive position 101, and the internal conductor of circuit board 110 extends to electrically conductive position and with electrically conductive position contact, electrically conductive position 101 and neighbouring the plastic envelope lateral wall 230 surface covering of electrically conductive position 101 has first conducting layer 310, first conducting layer 310 is configured to extend to last plastic envelope cover 210 or lower plastic envelope surface 220, and with the laminating in the outside mainboard 20 electricity of upper and lower plastic envelope cover be connected, in order to realize the internal conductor with the electricity between the outside mainboard 20 is connected.

Specifically, the circuit board assembly 100 is a component having a specific function, which is formed by using one or more layers of circuit boards 110 as a carrier, and fixing a plurality of electronic components such as capacitors 121, inductors or resistors on two sides of the carrier, and placing a plurality of magnetic cores 122 penetrating through the circuit boards 110 in the middle; of course, various other types of electronic components such as transformers and the like may be provided, and are not particularly limited herein.

It should be noted that the wiring board 110 as the framework may be one layer, two layers or even more layers, and may include a plurality of through holes, blind holes and semi-buried holes therein; the capacitance 121, resistance, inductance may include but are not limited to die, patch, discrete, etc.; core 122 may include, but is not limited to, various shapes and may be made of various magnetic materials; the connection between the circuit board 110 and the electronic component 120 includes, but is not limited to, laser welding, eutectic welding, soldering, molecular bonding, etc.; the internal lead wires are led out by means of, but not limited to, probes, copper sheets, gold wires, and the like.

The plastic package body 200 is a structure that the circuit board assembly 100 is sealed in the middle by using a special plastic package material, and can protect the circuit board assembly 100 inside and dissipate heat. The plastic package body 200 may be made of various materials having a similar expansion coefficient to a silicon wafer and a good sealing performance, such as resin, and is not limited herein.

The system-on-chip structure of the present embodiment has the following advantages:

in the system-on-chip structure 10 of the present embodiment, the circuit board assembly 100 formed by combining the capacitor 121, the magnetic core 122 and other elements with the circuit board 110 is packaged and fixed by the plastic package body 200; the first conductive layer 310 covers the conductive portion 101 and the surface of the plastic-molded sidewall 230 adjacent to the conductive portion 101, and is electrically connected to the internal wires of the circuit board 110, so that electrical signals in the internal wires of the circuit board 110 can be led out, the electrical signals can be led out upwards or downwards along the extending direction of the first conductive layer 310, and the electrical signals can be directly led to the external motherboard 20 because the first conductive layer 310 extends upwards and downwards and then is connected to the external motherboard 20 attached to the upper or lower plastic-molded cover through a pad or the like.

In the embodiment, the circuit board assembly 100 is fixed by the plastic package body 200, and the two sides of the circuit board assembly 100 are sealed into an approximate cuboid in a plastic package manner, so that the circuit board assembly 100 is positioned in the cuboid, and the electronic component 120 is prevented from being directly exposed; the external conductive layer can shield and protect the internal circuit board assembly 100, avoid external signal interference and send signals to interfere external electric devices, and can also enhance heat dissipation;

meanwhile, the internal lead of the circuit board 110 is led out through the first conductive layer 310 and is electrically connected with the external main board 20, so that the internal lead horizontally arranged in the circuit board 110 is vertically led out and is in contact with the external main board 20, a pin structure is not required to be arranged, and the phenomena of disordered chip structure, complicated connection structure with multiple pins of the main board and short circuit among the pins caused by the adoption of the pins are avoided; the whole structure is simple, the hidden trouble of pin short circuit is eliminated, and therefore the system-level chip has high density, high integration level, miniaturization and high reliability while the normal realization of the function is ensured.

Referring to fig. 1 and 2, in some embodiments, at least one of the upper molding surface 210 and the lower molding surface 220 is covered with a second conductive layer 320, and the internal leads of the circuit board assembly 100 are electrically connected to the second conductive layer 320; and the edge of the second conductive layer 320 is provided with a first spacer 410, and the second conductive layer 320 is separated from at least one first conductive layer 310 by the first spacer 410.

Specifically, the second conductive layer 320 is disposed on the upper and lower plastic covers 210 and 220, and the internal wires of the circuit board assembly 100 are electrically connected to the second conductive layer 320, so that the internal circuit board assembly 100 can be directly connected to the pads of the external motherboard 20 through the upper and lower surfaces of the entire chip structure 10; and is separated from the first conductive layer 310 on the molding sidewall 230 for independent conduction.

By adopting the structural arrangement of the embodiment, 6 surfaces such as the side wall, the upper surface and the lower surface of the plastic-encapsulated cuboid can respectively and independently lead out the electric signals of all the internal leads of the circuit board assembly 100, and the electric connection with the external main board 20 is not limited to be in one plane, so that the use is more convenient; meanwhile, the second conductive layers 320 of the upper plastic cover 210 and the lower plastic cover 220 are separated from the first conductive layers 310 on the plastic side walls 230 by the first spacers 410, the first conductive layers 310 and the second conductive layers 320 are not in contact with each other and are independently conductive, and safety is absolutely reliable. In addition, through setting up first conducting layer 310 and second conducting layer 320, realize the encirclement to the cuboid that the plastic envelope becomes, can make inside circuit board components isolated with external signal, play the effect of signal shielding protection, also strengthened the heat dissipation.

In some embodiments, the second conductive layer 320 is in contact with at least one of the first conductive layers 310 to make electrical connection with the internal leads of the circuit board through the first conductive layer 310.

Specifically, since the first conductive layer 310 itself is connected to the internal leads of the circuit board, in this embodiment, the second conductive layer 320 is connected to one of the first conductive layers 310 (the first conductive layer 310 is different from the "first conductive layer separated from the second conductive layer 320 for independent conduction" in the previous embodiment), and thus, the second conductive layer 320 can be electrically connected to the internal leads of the circuit board. This embodiment design benefit for the second conducting layer also is connected with the internal conductor electricity through first conducting layer 310, does not need to design other circuit connection structure, and the structure is simple and easy.

Referring to fig. 1, in some embodiments, the first spacer 410 is arc-shaped or zigzag-shaped and extends around a portion where the first conductive layer 310 is connected to the upper molding surface 210 and/or the lower molding surface 220. Specifically, the space occupied by the first spacer 410 arranged in a linear manner on the upper molding surface 210 and/or the lower molding surface 220 is small, so that the arrangement area occupied by the second conductive layer 320 is reduced to the maximum extent, the surface area of the second conductive layer 320 can be maximized, and the stable electrical connection effect is ensured.

Referring to fig. 1, in some embodiments, the molding sidewall 230 adjacent to the first conductive layer 310 is in communication with the first spacer 410. In this embodiment, the plastic package sidewall 230 beside the first conductive layer 310 is communicated with the first spacers 410 on the upper and lower plastic package surfaces, so that the boundary between the first conductive layer 310 and the second conductive layer 320 is clearly separated, and the short circuit connection caused by the deviation of the processing precision between the two layers is avoided; meanwhile, the interval between the two is clear, so that the requirement on the processing precision of the coating position of each conducting layer is favorably reduced, and the operation, processing and production are facilitated.

After a conventional chip is connected to a motherboard by using a plurality of pins on the edge, other electronic components are mounted on the motherboard, and the other electronic components are easily contacted with the plurality of pins on the edge of the chip, so that short circuit occurs. In view of this problem, referring to fig. 4 and 5, in some embodiments, at least one side edge of the circuit board 110 is provided with two or more conductive portions 101, and the conductive portions 101 of the circuit board 110 are recessed to form conductive grooves, and the surfaces of the conductive grooves are provided with lead-out terminals 103 of the internal leads; that is, the internal lead of the circuit board 110 extends to the bottom of the conductive groove, and the end of the internal lead is provided with the leading-out terminal 103, and the leading-out terminal 103 is a metal layer attached to or plated on the surface of the conductive groove, so that the first conductive layer 310 can be electrically connected with the internal lead through the leading-out terminal 103 after covering the leading-out terminal 103.

Specifically, since the leading-out terminal 103 of the internal lead is arranged on the surface of the conductive groove, the first conductive layer 310 covers the leading-out terminal 103, and then a larger contact area is formed between the leading-out terminal 103 and the first conductive layer, so that the electrical connection is stable; because the conductive portions 101 are all recessed into conductive grooves, the probability of contact between the conductive portions 101 located on the same side edge is smaller, and even if other electronic components are attached to the edge of the chip structure 10, the electronic components are difficult to contact the recessed conductive portions 101, and even more unlikely to contact multiple recessed conductive portions 101 at the same time, so that the probability of short-circuit connection of the multiple conductive portions 101 is greatly reduced.

Referring to fig. 4 and 5, in some embodiments, the edge of the circuit board 110 and the plastic-molded sidewall 230 disposed around the edge of the circuit board 110 are continuous waves, and the conductive grooves are formed on each conductive portion 101. Specifically, compared with a linear design, each conductive part 101 forms a conductive groove, so that each conductive part 101 can be protected and short circuit caused by being arranged at the edge of a straight line or after being protruded can be avoided; in addition, the wavy edge of the circuit board 110 is convenient for die sinking processing, and the processing cost cannot be increased.

Referring to fig. 1, in some embodiments, the package substrate further includes a third conductive layer 330 covering the molding sidewall 230 and separated from the first conductive layer 310 by a second separation region 420 where no conductive layer is disposed on the molding sidewall 230.

Specifically, a third conductive layer 330 is disposed on the surface of the plastic-sealed sidewall 230 at a position spaced apart from the first conductive layer 310. The third conductive layer 330 coated on the surface of the plastic package sidewall 230 can improve the shielding, isolation and heat dissipation effects of the system-on-chip; meanwhile, the third conductive layer 330 is separated from the first conductive layer 310, so that the short circuit of the internal wires connected with the first conductive layer 310 caused by the accidental contact between the external electronic component 120 and the third conductive layer 330 can be avoided.

Referring to fig. 1, in some embodiments, at least one of the upper molding surface 210 and the lower molding surface 220 is covered with a second conductive layer 320, and the internal conductive wires of the circuit board assembly 100 are electrically connected to the second conductive layer 320; the edge of the second conductive layer 320 is provided with a first spacer 410, and the second conductive layer 320 is separated from the first conductive layer 310 by the first spacer 410; the third conductive layer 330 is connected to the second conductive layer 320.

In this embodiment, not only the upper and lower surfaces of the entire chip structure 10, and the first conductive layers 310 on the four walls, are independently connected to the pads of the external motherboard 20, respectively, but also the third conductive layer 330 additionally disposed on the surface of the plastic package sidewall 230 is used to improve the shielding isolation and heat dissipation effects of the system-level chip; in addition, since the third conductive layer 330 is connected to the second conductive layer 320, the area of the second conductive layer 320 is expanded, that is, the conductive area of the second conductive layer 320 on the upper surface or the lower surface is increased, even if the pads on the external motherboard 20 and the second conductive layer 320 are offset relative to each other and connected to the third conductive layer 330 on the plastic package sidewall 230 during assembly, the external motherboard 20 can be electrically connected to the second conductive layer 320 stably through the third conductive layer 330, and the requirement of assembly accuracy is reduced.

Referring to fig. 1, in some embodiments, the second conductive layer 320 is disposed at an interval on the upper molding surface 210 and/or the lower molding surface 220, and the interval is a third interval area 430 that does not cover the second conductive layer 320, and the third interval area 430 is connected to two second interval areas 420 on two opposing molding sidewalls 230. Specifically, the third partition 430 is designed to divide the second conductive layer 320 of the upper and lower cover plates 220 into a plurality of second conductive layers 320 along the length direction, and the plurality of second conductive layers 320 can be independently connected to pads in different areas on the external motherboard 20, so as to further expand the electrical connection function of the second conductive layers 320, and different parts of the second conductive layers 320 separated on the same plane can be connected to pads in different areas on the external motherboard 20, thereby implementing different functions; and because the third spacing zone 430 is connected with the two second spacing zones 420 on the two opposite plastic package side walls 230, the conductive area of the second conductive layer 320 on the upper and lower surfaces is expanded by using the third conductive layer 330 additionally arranged on the surface of the plastic package side wall 230, so that the whole chip structure 10 forms a plurality of conductive sections 500 along the length direction with the connected second spacing zones 420 and third spacing zones 430 as boundaries, the conductive layers wrapped on the periphery of the conductive sections 500 form conductive sleeves respectively used for connecting different pads on a mainboard, of course, the conductive sleeves have large area, and the shielding isolation and heat dissipation effects of the system-level chip are also improved.

Referring to fig. 1, in some embodiments, the upper molding surface 210 is disposed parallel to the lower molding surface 220.

In some embodiments, the conductive layer includes, but is not limited to, copper, aluminum, gold, etc., and has good conductivity, shielding, isolation, and heat dissipation.

In an embodiment of the present invention, a motherboard structure is further provided, which includes a motherboard and the above-mentioned three-dimensional packaged system-on-chip, wherein a portion of the first conductive layer 310 of the three-dimensional packaged system-on-chip extending to the upper or lower plastic package surface 220 is electrically connected to the external motherboard 20 attached to the upper or lower plastic package surface 220.

In another embodiment of the present invention, a method for manufacturing a system-level chip is provided, which includes the following steps:

the operation electronic component 120 is electrically connected with the circuit board 110 to form the circuit board assembly 100, and the internal conducting wire of the circuit board 110 is operated to extend to the conducting part of the circuit board 110;

operating the packaging filler to wrap the circuit board assembly 100 to form a plastic package body 200;

the surfaces of the conductive portion 101 at the edge of the circuit board 110 and the plastic package side wall 230 adjacent to the conductive portion 101 are covered with a first conductive layer 310, and the first conductive layer 310 extends to the upper or lower plastic package surface 220.

The system-on-chip structure 10 of the present invention can be manufactured by the above manufacturing method.

In the above description, although it is possible to describe respective elements of the present invention using expressions such as "first" and "second", they are not intended to limit the corresponding elements. For example, the above expressions are not intended to limit the order or importance of the corresponding elements. The above expressions are used to distinguish one element from another.

The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular references include plural references unless there is a significant difference in context, scheme or the like between them.

The above description is intended to be illustrative of the present invention and not to limit the scope of the invention, which is defined by the claims appended hereto.

Those skilled in the art will appreciate that various features of the above-described embodiments may be omitted, added, or combined in any way, and for the sake of brevity, all possible combinations of features of the above-described embodiments will not be described, however, so long as there is no contradiction between these combinations of features, and simple variations and structural variations which are adaptive and functional to the prior art, which can occur to those skilled in the art, should be considered within the scope of this description.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that while the present invention has been shown and described with reference to various embodiments, it will be understood by those skilled in the art that various changes and modifications in form and detail may be made without departing from the spirit of the invention and these are within the scope of the invention as defined by the appended claims. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A system-on-chip of a three-dimensional package, comprising:

the circuit board assembly comprises a circuit board and an electronic element electrically connected with the circuit board;

the plastic package body is packaged and covered on the circuit board assembly and comprises an upper plastic package cover, a lower plastic package cover and a plastic package side wall, wherein the upper plastic package cover and the lower plastic package cover are spaced from the circuit board, and the plastic package side wall is arranged around the edge of the circuit board;

the edge of circuit board is equipped with at least one electrically conductive position, and the internal conductor of circuit board extends to electrically conductive position and with electrically conductive position contact, electrically conductive position and neighbouring the plastic envelope lateral wall surface covering at electrically conductive position has first conducting layer, first conducting layer is configured to extend to or mould the front cover down, and with laminate in or mould the outside mainboard electricity of front cover down and be connected, in order to realize the internal conductor with electricity between the outside mainboard is connected.

2. The system-on-chip of the three-dimensional package according to claim 1, wherein at least one of the surfaces of the upper and lower cover covers is covered with a second conductive layer, and the internal wires of the circuit board assembly are electrically connected to the second conductive layer; and the edge of the second conducting layer is provided with a first interval area, and the second conducting layer is separated from at least one first conducting layer through the first interval area.

3. The system-on-chip of claim 2, wherein the first spacer is arc-shaped or fold-shaped and extends around a portion of the first conductive layer connected to the upper molding surface and/or the lower molding surface.

4. The system-on-chip of the three-dimensional package according to claim 2, wherein the second conductive layer is in contact with at least one of the first conductive layers to electrically connect to the internal leads of the circuit board through the first conductive layer.

5. The system-on-chip of claim 2, wherein the plastic-encapsulated sidewall adjacent to the first conductive layer is in communication with the first spacer.

6. The system-on-chip of the three-dimensional package according to claim 1, wherein the conductive portion of the circuit board is recessed to form a conductive groove, the internal lead of the circuit board extends to the bottom of the conductive groove, the lead-out terminal of the internal lead is disposed on the surface of the conductive groove, and the first conductive layer covers the lead-out terminal to make electrical contact therewith; at least one side edge of the circuit board is provided with two or more conductive parts.

7. The system-on-chip of claim 6, wherein the edge of the circuit board and the side walls of the plastic package surrounding the edge of the circuit board are continuous waves, and the conductive grooves are formed on the conductive portions respectively.

8. The system-on-chip of claim 1, further comprising a third conductive layer covering the molding sidewall and separated from the first conductive layer by a second spacer region on the molding sidewall without the conductive layer.

9. The system-on-chip of the three-dimensional package according to claim 8, wherein at least one of the surfaces of the upper and lower cover covers is covered with a second conductive layer, and the internal wires of the circuit board assembly are electrically connected to the second conductive layer; a first spacer is arranged at the edge of the second conducting layer, and the second conducting layer is separated from the first conducting layer through the first spacer; the third conductive layer is connected to the second conductive layer.

10. The system-on-chip of the three-dimensional package according to claim 9, wherein the second conductive layer is disposed on the upper molding surface and/or the lower molding surface at an interval, and the interval is a third interval region not covered by the second conductive layer, and the third interval region connects the two second interval regions on the two opposing molding sidewalls.

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