CN115828817A - Modeling method and modeling system of semiconductor device model - Google Patents
Modeling method and modeling system of semiconductor device model Download PDFInfo
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- CN115828817A CN115828817A CN202211565432.8A CN202211565432A CN115828817A CN 115828817 A CN115828817 A CN 115828817A CN 202211565432 A CN202211565432 A CN 202211565432A CN 115828817 A CN115828817 A CN 115828817A
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Abstract
The disclosure relates to a modeling method and a modeling system of a semiconductor device model. The modeling method of the semiconductor device model comprises the following steps: and respectively carrying out electrical test on each transistor in the semiconductor device under different measurement conditions to obtain the electrical parameters of each transistor. And fitting the curve of the electrical parameters of each transistor to obtain the model parameters of each transistor. And describing the measurement conditions, the electrical parameters of each transistor and the model parameters of each transistor to obtain the transistor model of each transistor. A semiconductor device model is constructed based on a transistor model for each transistor. The modeling method of the semiconductor device model greatly increases the accuracy of the semiconductor device model, and is further beneficial to the circuit design and simulation of an integrated circuit designer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a modeling method and a modeling system of a semiconductor device model.
Background
A Static Random Access Memory (SRAM) is a widely used semiconductor Memory device, and is composed of an SRAM cell array and peripheral circuits. One common SRAM cell includes two pull-up transistors, two pull-down transistors, and two pass transistors. To describe the performance of transistors in an SRAM cell, an SRAM cell model needs to be constructed.
The conventional SRAM cell model is composed of three independent transistor models, a pull-up transistor, a pull-down transistor and a pass transistor. However, the performance of six transistors cannot be fully described by three independent transistor models, so that the characteristics of the SRAM cell, such as read stability, write capability, power dissipation, and the like, cannot be accurately obtained.
Therefore, how to improve the accuracy of the SRAM cell model is an urgent problem to be solved.
Disclosure of Invention
Based on the above-mentioned shortcomings of the prior art, the present application aims to provide a modeling method and a modeling system for a semiconductor device model, and aims to solve the problem of how to improve the accuracy of an SRAM cell model.
The embodiment of the application provides a modeling method of a semiconductor device model, which comprises the following steps: and respectively carrying out electrical test on each transistor in the semiconductor device under different measurement conditions to obtain the electrical parameters of each transistor. And fitting the curve of the electrical parameters of each transistor to obtain the model parameters of each transistor. Describing the measurement conditions, the electrical parameters of each transistor and the model parameters of each transistor to obtain a transistor model of each transistor; a semiconductor device model is constructed based on a transistor model for each transistor.
In the embodiment of the application, each transistor in the semiconductor device is subjected to electrical test, and then the curve of the electrical parameter of each transistor is fitted to extract the model parameter of each transistor. Finally, in view of the small difference of each transistor in the same semiconductor device, the measurement conditions, the electrical parameters of each transistor and the model parameters of each transistor are described to obtain the transistor model of each transistor, so as to obtain the semiconductor device model. In this way, the above modeling method for the semiconductor device model measures the electrical parameters of each transistor in the semiconductor device, and describes the measurement conditions, the electrical parameters of each transistor, and the model parameters of each transistor. Therefore, the accuracy of the semiconductor device model is greatly increased, and the circuit design and simulation of an integrated circuit designer are facilitated.
Optionally, the modeling method of the semiconductor device model further includes: and carrying out electrical measurement on the semiconductor device under different measurement conditions to obtain electrical parameters of the semiconductor device. And simulating the electrical parameters of the semiconductor device according to the semiconductor device model to obtain an electrical parameter simulation curve. And comparing the electrical parameter simulation curve with the electrical parameters of the semiconductor device, wherein if the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device, the semiconductor device model is a target model.
In the embodiment of the present application, the modeling method of the semiconductor device model further introduces an electrical parameter simulation curve of the semiconductor device, that is, introduces a process corner parameter of the semiconductor device, on the basis of measuring an electrical parameter of each transistor in the semiconductor device. Therefore, the accuracy of the semiconductor device model is further improved, and the circuit design and simulation of an integrated circuit designer are facilitated.
Optionally, the modeling method of the semiconductor device model further includes: if the electrical parameter simulation curve is not matched with the electrical parameters of the semiconductor device, repeating the steps from fitting the electrical parameter simulation curve of each transistor to comparing the electrical parameter simulation curve with the electrical parameters of the semiconductor device for a plurality of times until the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device.
Optionally, fitting the curve of the electrical parameter of each transistor to obtain the model parameter of each transistor includes: and performing polynomial fitting on the curve of the electrical parameter of each transistor to obtain the model parameter of each transistor.
Optionally, the measurement conditions include temperature and voltage.
Optionally, the electrical parameters include current and voltage.
Optionally, the electrical parameters include static noise margin, read current, write margin, and static leakage current.
Based on the same inventive concept, the embodiment of the application also provides a modeling system of the semiconductor device model, which comprises a measuring module, a fitting module, a first modeling module and a second modeling module. The measuring module is used for respectively carrying out electrical test on each transistor in the semiconductor device under different measuring conditions so as to obtain electrical parameters of each transistor. The fitting module is connected with the measuring module and used for fitting the curves of the electrical parameters of the transistors to obtain the model parameters of the transistors. The first modeling module is connected with the measuring module and the fitting module and is used for describing the measuring conditions, the electrical parameters of each transistor and the model parameters of each transistor so as to obtain the transistor model of each transistor. The second modeling module is connected with the first modeling module and used for building a semiconductor device model based on the transistor model of each transistor.
In the embodiment of the present application, the modeling system of the semiconductor device model is constructed by using the modeling method of the semiconductor device model according to any one of the foregoing aspects. The modeling method of the semiconductor device model in the foregoing embodiment has technical advantages, and the modeling system of the semiconductor device model also has technical advantages, which are not described in detail herein.
Optionally, the measurement module is further configured to perform electrical measurement on the semiconductor device under different measurement conditions to obtain electrical parameters of the semiconductor device; the modeling system of the semiconductor device model further comprises a simulation module and a model output module. The simulation module is used for simulating the electrical parameters of the semiconductor device according to the semiconductor device model so as to obtain an electrical parameter simulation curve. The model output module is connected with the simulation module and used for comparing the electrical parameter simulation curve with the electrical parameters of the semiconductor device and outputting the semiconductor device model as a target model when the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device.
In the embodiment of the present application, the modeling system of the semiconductor device model further introduces an electrical parameter simulation curve of the semiconductor device, that is, introduces a process corner parameter of the semiconductor device, on the basis of measuring an electrical parameter of each transistor in the semiconductor device. Therefore, the accuracy of the semiconductor device model is further improved, and the circuit design and simulation of an integrated circuit designer are facilitated.
Optionally, the modeling system of the semiconductor device model further comprises a feedback module. The feedback module is connected with the model output module and the fitting module and used for feeding back a feedback signal to the fitting module when the electrical parameter simulation curve is not matched with the electrical parameters of the semiconductor device.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a flow chart of a method for modeling a model of a semiconductor device provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a semiconductor device model provided in an embodiment of the present application;
FIG. 3 (a) is a graph comparing an input current-voltage curve of a transistor in a semiconductor device model and a current-voltage curve of the transistor model provided in an embodiment of the present application; FIG. 3 (b) is a graph comparing a transistor output current-voltage curve and a transistor model current-voltage curve in a semiconductor device model provided in an embodiment of the present application;
FIG. 4 (a) is a graph comparing an input current-voltage curve of another transistor in a semiconductor device model provided in an embodiment of the present application with a current-voltage curve of the transistor model; FIG. 4 (b) is a graph comparing an output current-voltage curve of another transistor in a semiconductor device model and a current-voltage curve of the transistor model provided in an embodiment of the present application;
FIG. 5 (a) is a graph comparing an input current-voltage curve of a further transistor in a model of a semiconductor device provided in an embodiment of the present application with a current-voltage curve of the model of the transistor; FIG. 5 (b) is a graph comparing an output current-voltage curve of a further transistor in a semiconductor device model with a current-voltage curve of a transistor model provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of a modeling system for a semiconductor device model provided in an embodiment of the present application.
Description of the reference numerals:
1-a measurement module; 2-a fitting module; 3-a first modeling module; 4-a second modeling module; 5-a simulation module; 6-a model output module; 7-feedback module.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Embodiments of the present disclosure are presented in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
As used herein, a "Deposition" process includes, but is not limited to, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
A Static Random Access Memory (SRAM) is a widely used semiconductor Memory device, and is composed of an SRAM cell array and peripheral circuits. One common SRAM cell includes two pull-up transistors, two pull-down transistors, and two pass transistors. To describe the performance of transistors in an SRAM cell, an SRAM cell model needs to be constructed.
The conventional SRAM cell model is composed of three independent transistor models, a pull-up transistor, a pull-down transistor and a pass transistor. From the above, the traditional SRAM cell model only extracts one model for two symmetrical transistors, that is, two pull-up transistors share one model, two pull-down transistors share one model, and two pass transistors share one model, so that six transistors share three transistor models.
However, even though there are small electrical differences between transistors within the same SRAM cell array, the magnitude of the differences generally depends on the manufacturing process, but no matter how small the differences have an effect on the overall performance of the SRAM. Therefore, the performance of six transistors cannot be fully described by three independent transistor models, so that the characteristics of the SRAM, such as read stability, write capability, power dissipation, and the like, cannot be accurately obtained.
Therefore, how to improve the accuracy of the SRAM cell model is an urgent problem to be solved.
Based on this, the present application intends to provide a solution to the above technical problem, the details of which will be explained in the following embodiments.
Referring to fig. 1, an embodiment of the present application provides a modeling method of a semiconductor device model, which includes steps S10 to S30.
S10: and respectively carrying out electrical test on each transistor in the semiconductor device under different measurement conditions to obtain the electrical parameters of each transistor.
In some examples, the measurement conditions include temperature and voltage. And respectively carrying out electrical test on each transistor in the semiconductor device under different temperatures and voltages to obtain electrical parameters of each transistor.
In some examples, the electrical parameters include current and voltage. Each transistor in the semiconductor device is electrically tested under different measurement conditions to obtain the current and voltage of each transistor.
Accordingly, in some examples, the electrical parameters include static noise margin, read current, write margin, and static leakage current.
S20: and fitting the curve of the electrical parameters of each transistor to obtain the model parameters of each transistor.
In some examples, fitting the curve of the electrical parameter of each transistor to obtain the model parameter of each transistor includes: and performing polynomial fitting on the curve of the electrical parameter of each transistor to obtain the model parameter of each transistor.
For example, an industry standard modeling software may be used to perform a polynomial fit on the curve of the first electrical parameter to obtain model parameters of each transistor.
S30: describing the measurement conditions, the electrical parameters of each transistor and the model parameters of each transistor to obtain a transistor model of each transistor; a semiconductor device model is constructed based on a transistor model for each transistor.
In some examples, the measurement conditions, the electrical parameters of each transistor, and the model parameters of each transistor may be described in a hardware description language to obtain a transistor model of each transistor.
In the embodiment of the application, each transistor in the semiconductor device is subjected to electrical test, and then the curve of the electrical parameter of each transistor is fitted to extract the model parameter of each transistor. Finally, in view of the small difference of each transistor in the same semiconductor device, the measurement conditions, the electrical parameters of each transistor and the model parameters of each transistor are described to obtain the transistor model of each transistor, so as to obtain the semiconductor device model. In this way, the above modeling method for the semiconductor device model measures the electrical parameters of each transistor in the semiconductor device, and describes the measurement conditions, the electrical parameters of each transistor, and the model parameters of each transistor. Therefore, the accuracy of the semiconductor device model is greatly increased, and the circuit design and simulation of an integrated circuit designer are facilitated.
In some examples, the method of modeling a semiconductor device model further includes steps S40 to S60.
S40: and carrying out electrical measurement on the semiconductor device under different measurement conditions to obtain electrical parameters of the semiconductor device.
In some examples, the measurement conditions include temperature and voltage. And respectively carrying out electrical test on each transistor in the semiconductor device under different temperatures and voltages to obtain electrical parameters of each transistor.
In some examples, the electrical parameters include current and voltage. And respectively carrying out electrical test on each transistor in the semiconductor device under different measurement conditions to obtain the current and the voltage of each transistor.
Accordingly, in some examples, the electrical parameters include static noise margin, read current, write margin, and static leakage current.
S50: and simulating the electrical parameters of the semiconductor device according to the semiconductor device model to obtain an electrical parameter simulation curve.
In some examples, simulation software may be used to simulate electrical parameters of a semiconductor device to obtain an electrical parameter simulation curve.
S60: and comparing the electrical parameter simulation curve with the electrical parameters of the semiconductor device, wherein if the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device, the semiconductor device model is a target model.
The modeling method of the semiconductor device model introduces the electrical parameter simulation curve of the semiconductor device on the basis of measuring the electrical parameters of each transistor in the semiconductor device, namely introduces the process angle parameters of the semiconductor device. Therefore, the accuracy of the semiconductor device model is further improved, and the circuit design and simulation of an integrated circuit designer are facilitated.
In some examples, the method of modeling a semiconductor device model further comprises:
s70: if the electrical parameter simulation curve is not matched with the electrical parameters of the semiconductor device, repeating the steps from fitting the electrical parameter simulation curve of each transistor to comparing the electrical parameter simulation curve with the electrical parameters of the semiconductor device for a plurality of times until the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device.
Therefore, the semiconductor device model is guaranteed to be the target model until the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device.
In some examples, referring to fig. 2, the semiconductor device includes an SRAM, and the SRAM cell includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass transistor PG1, and a second pass transistor PG2.
As an example, referring to fig. 3 (a) and 3 (b), a first transfer transistor model is established based on the first transfer transistor PG 1. The maximum error displayed by the input curve of the measured data of the first transfer transistor PG1 and the contrast value of the first transfer transistor model is 2.46%, and the maximum error displayed by the output curve of the measured data of the first transfer transistor PG1 and the contrast value of the first transfer transistor model is 4.88%. Referring to fig. 4 (a) and 4 (b), if the second transfer transistor PG2 and the first transfer transistor PG1 share the first transfer transistor model, the maximum error shown by the input curve of the measured data of the second transfer transistor PG2 and the contrast value of the first transfer transistor model is 8.52%, and the maximum error shown by the output curve of the measured data of the second transfer transistor PG2 and the contrast value of the first transfer transistor model is 8.93%. From the above, the error is larger when the first pass transistor model is used to describe the second pass transistor PG2. Further, referring to fig. 5 (a) and 5 (b), a second pass transistor model is established based on the second pass transistor PG2. The results show that the input curve of the second pass transistor PG2 is reduced from a maximum error of 8.52% to 2.25%, and the output curve of the second pass transistor PG2 is reduced from a maximum error of 8.93% to 4.46%.
From the above, in the embodiment of the present application, the first transfer transistor PG1 and the second transfer transistor PG2 respectively and independently establish a first transfer transistor model and a second transfer transistor model, and although the workload is increased to some extent, the accuracy of each transistor model can be improved. The method is also used for independently modeling the first pull-up transistor PU1 and the second pull-up transistor PU2 and independently modeling the first pull-down transistor PD1 and the second pull-down transistor PD2, so that the accuracy of each transistor model is improved.
Based on the same inventive concept, please refer to fig. 6, an embodiment of the present application further provides a modeling system of a semiconductor device model, which is constructed by using the modeling method of the semiconductor device model described in any of the above embodiments. The modeling system of the semiconductor device model includes a measurement module 1, a fitting module 2, a first modeling module 3, and a second modeling module 4. The measurement module 1 is configured to perform an electrical test on each transistor in the semiconductor device under different measurement conditions, so as to obtain an electrical parameter of each transistor. The fitting module 2 is connected with the measuring module 1 and is used for fitting the curve of the electrical parameter of each transistor to obtain the model parameter of each transistor. The first modeling module 3 is connected with the measurement module 1 and the fitting module 2, and is used for describing measurement conditions, electrical parameters of each transistor and model parameters of each transistor so as to obtain a transistor model of each transistor. The second modeling module 4 is connected to the first modeling module 3 for building a model of the semiconductor device based on the transistor models of the respective transistors.
In the embodiment of the present application, a modeling system of a semiconductor device model is constructed by using the modeling method of a semiconductor device model according to any one of the above-mentioned aspects. The modeling method of the semiconductor device model in the foregoing embodiment has technical advantages, and the modeling system of the semiconductor device model also has technical advantages, which are not described in detail herein.
In some examples, the measurement conditions include temperature and voltage. And respectively carrying out electrical test on each transistor in the semiconductor device at different temperatures and voltages to obtain electrical parameters of each transistor.
In some examples, the electrical parameters include current and voltage. And respectively carrying out electrical test on each transistor in the semiconductor device under different measurement conditions to obtain the current and the voltage of each transistor.
Accordingly, in some examples, the electrical parameters include static noise margin, read current, write margin, and static leakage current.
In some examples, the fitting module 2 fits a curve of the electrical parameter of each transistor to obtain a model parameter of each transistor includes: the fitting module 2 performs polynomial fitting on the curve of the electrical parameter of each transistor to obtain a model parameter of each transistor.
For example, the fitting module 2 may perform polynomial fitting on the curve of the first electrical parameter by using industry standard modeling software to obtain model parameters of each transistor.
In some examples, the first modeling module 3 may describe the measurement conditions, the electrical parameters of each transistor, and the model parameters of each transistor in a hardware description language to obtain a transistor model of each transistor.
Optionally, with reference to fig. 1, the measurement module 1 is further configured to perform electrical measurement on the semiconductor device under different measurement conditions to obtain electrical parameters of the semiconductor device. The modeling system of the semiconductor device model further includes a simulation module 5 and a model output module 6. The simulation module 5 is configured to simulate an electrical parameter of the semiconductor device according to the semiconductor device model to obtain an electrical parameter simulation curve. The model output module 6 is connected to the simulation module 5, and is configured to compare the electrical parameter simulation curve with the electrical parameter of the semiconductor device, and output the semiconductor device model as a target model when the electrical parameter simulation curve matches the electrical parameter of the semiconductor device.
In some examples, the measurement conditions under which the measurement module 1 performs electrical measurements on semiconductor devices include temperature and voltage. And respectively carrying out electrical test on each transistor in the semiconductor device under different temperatures and voltages to obtain electrical parameters of each transistor.
In some examples, the electrical parameters include current and voltage. And respectively carrying out electrical test on each transistor in the semiconductor device under different measurement conditions to obtain the current and the voltage of each transistor.
Accordingly, in some examples, the electrical parameters include static noise margin, read current, write margin, and static leakage current.
In some examples, the simulation module 5 is connected with the measurement module 1 and the second modeling module 4.
For example, the simulation module 5 may use simulation software to simulate the electrical parameters of the semiconductor device to obtain an electrical parameter simulation curve.
In the embodiment of the present application, the modeling system of the semiconductor device model further introduces an electrical parameter simulation curve of the semiconductor device, that is, introduces a process corner parameter of the semiconductor device, on the basis of measuring an electrical parameter of each transistor in the semiconductor device. Therefore, the accuracy of the semiconductor device model is further improved, and the circuit design and simulation of an integrated circuit designer are facilitated.
Optionally, with continued reference to fig. 1, the modeling system for the semiconductor device model further includes a feedback module 7. The feedback module 7 is connected with the model output module 6 and the fitting module 2, and is configured to feed back a feedback signal to the fitting module 2 when the electrical parameter simulation curve is not matched with the electrical parameter of the semiconductor device.
In the embodiment of the present application, when the electrical parameter simulation curve is not matched with the electrical parameter of the semiconductor device, the feedback signal is fed back to the fitting module 2, until the electrical parameter simulation curve is matched with the electrical parameter of the semiconductor device, the semiconductor device model is the target model. Therefore, the accuracy of the semiconductor device model is further improved, and the circuit design and simulation of an integrated circuit designer are facilitated.
In the description of the present specification, various technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present disclosure, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the concept of the present disclosure, and these changes and modifications are all within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the appended claims.
Claims (10)
1. A modeling method of a semiconductor device model is characterized by comprising the following steps:
respectively carrying out electrical test on each transistor in the semiconductor device under different measurement conditions to obtain electrical parameters of each transistor;
fitting a curve of the electrical parameters of each transistor to obtain model parameters of each transistor;
describing the measurement condition, the electrical parameters of each transistor and the model parameters of each transistor to obtain a transistor model of each transistor;
a semiconductor device model is constructed based on the transistor model for each of the transistors.
2. The method of modeling a semiconductor device model of claim 1, further comprising:
carrying out electrical measurement on the semiconductor device under different measurement conditions to obtain electrical parameters of the semiconductor device;
simulating the electrical parameters of the semiconductor device according to the semiconductor device model to obtain an electrical parameter simulation curve;
and comparing the electrical parameter simulation curve with the electrical parameters of the semiconductor device, wherein if the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device, the semiconductor device model is a target model.
3. The method of modeling a semiconductor device model of claim 1, further comprising:
if the electrical parameter simulation curve is not matched with the electrical parameters of the semiconductor device, repeating the steps from fitting the curve of the electrical parameters of each transistor to comparing the electrical parameter simulation curve with the electrical parameters of the semiconductor device for a plurality of times until the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device.
4. The method of claim 1, wherein said fitting a curve of electrical parameters of each of said transistors to obtain model parameters of each of said transistors comprises: and performing polynomial fitting on the curve of the electrical parameter of each transistor to obtain the model parameter of each transistor.
5. A modeling method of a semiconductor device model according to any one of claims 1 to 4, characterized in that the measurement conditions include temperature and voltage.
6. A method of modelling a semiconductor device model according to any of claims 1 to 4, wherein the electrical parameters comprise current and voltage.
7. A modeling method of a semiconductor device model according to claim 6, characterized in that the electrical parameters include static noise margin, read current, write margin and static leakage current.
8. A modeling system for a semiconductor device model, comprising:
the measuring module is used for respectively carrying out electrical test on each transistor in the semiconductor device under different measuring conditions so as to obtain electrical parameters of each transistor;
the fitting module is connected with the measuring module and used for fitting the curve of the electrical parameters of each transistor to obtain the model parameters of each transistor;
the first modeling module is connected with the measuring module and the fitting module and is used for describing the measuring conditions, the electrical parameters of the transistors and the model parameters of the transistors so as to obtain a transistor model of each transistor;
and the second modeling module is connected with the first modeling module and used for building a semiconductor device model based on the transistor model of each transistor.
9. The modeling system of a semiconductor device model of claim 8, wherein the measurement module is further configured to perform electrical measurements on the semiconductor device under different measurement conditions to obtain electrical parameters of the semiconductor device; the modeling system of the semiconductor device model further includes:
the simulation module is used for simulating the electrical parameters of the semiconductor device according to the semiconductor device model so as to obtain an electrical parameter simulation curve;
and the model output module is connected with the simulation module and used for comparing the electrical parameter simulation curve with the electrical parameters of the semiconductor device and outputting the semiconductor device model as a target model when the electrical parameter simulation curve is matched with the electrical parameters of the semiconductor device.
10. The modeling system of a semiconductor device model of claim 9, further comprising:
and the feedback module is connected with the model output module and the fitting module and used for feeding back a feedback signal to the fitting module when the electrical parameter simulation curve is not matched with the electrical parameters of the semiconductor device.
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| CN117236260A (en) * | 2023-11-13 | 2023-12-15 | 广东芯聚能半导体有限公司 | Modeling method and device for semiconductor device, computer equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117236260A (en) * | 2023-11-13 | 2023-12-15 | 广东芯聚能半导体有限公司 | Modeling method and device for semiconductor device, computer equipment and storage medium |
| CN117236260B (en) * | 2023-11-13 | 2024-03-12 | 广东芯聚能半导体有限公司 | Modeling method and device for semiconductor device, computer equipment and storage medium |
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